JPH04127711A - Delay circuit - Google Patents

Abstract

PURPOSE:To reduce energy consumption by parallelly arranging plural delay elements so as not to operate them simultaneously. CONSTITUTION:An input changeover switch 6 is changed over to apply input signals to delay elements (shift registers) 41-4i to which a frequency divider 5 applies the significant part of a shift clock. The input signals are successively supplied to the respective shift registers 41-4i synchronously with the input clock, and the shift registers 41-4i supplied the input signals shift internal data. An output changeover switch 7 is changed over to apply the outputs of the shift registers 41-4i to a data output terminal 3 in the order of executing shift operation. Thus, since the respective shift registers 41-4i are operated by the shift clock outputted from the frequency divider 5 so as to execute time division operations, the energy consumption can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a delay circuit that delays an input signal by a plurality of clock pulses.

[Conventional technology]

FIG. 7 is a block diagram showing an example of a conventional delay circuit. In the figure, 1 is a data input terminal to which an input signal is input, 2 is a clock input terminal to which a shift clock is input, and 3 is delayed data. A data output terminal that outputs
4 is a shift register which is an example of a delay element.

Next, the operation will be explained. The input signal input to the data input terminal 1 is taken into the shift register 4 in synchronization with the shift clock input to the clock input terminal 2, and is shifted one stage at a time within each shift register 4. Assuming that the number of stages of the shift register 4 is n, the input signal input to the data input terminal 1 is output from the data output terminal 3 after a time corresponding to the clock pulse of the shift clock. That is, the input signal is delayed by n clocks.

[Problem to be solved by the invention]

Since the conventional delay device is configured as described above, all stages of the shift register 4 must operate every time the shift clock is input, which results in high power consumption, especially when operating on batteries. The problem was that it was not suitable for portable devices.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a delay circuit that can suppress power consumption by operating only a portion of all shift stages during a shift.

[Means to solve the problem]

The delay circuit according to the present invention includes a splitter that creates a plurality of shift clocks having different phases from an input clock;
Provided corresponding to each of multiple shift clocks,
delay elements each introducing a corresponding shift clock; input switching means for sequentially supplying an input signal to each delay element in synchronization with the input clock; and output selection means for sequentially selecting an output of each delay element. It is equipped with the following.

[For production]

Each delay element in the present invention performs a time division operation by being operated by a shift clock output from a frequency divider.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, 41 to 41 are shift registers each having a number of stages, 5 is a frequency divider that divides the input clock and generates shift clocks that have mutually different phases and whose frequency is 17 i of the input clock frequency, and 6 is a frequency divider An input selector switch (
7 is an output changeover switch (output selection means) which sequentially selects the outputs of the shift registers 41 to 41 and supplies them to the data output terminal 3; the other parts are denoted by the same reference numerals and shown in FIG. This is the same as shown in .

Next, the operation will be explained. Based on the input clock input to the clock input terminal 2, the frequency divider 5 generates i shift clocks whose frequency is 1/i of the input clock frequency and whose phases differ by one clock of the input clock. generate. Each shift register 41-41 introduces any one of the i shift clocks. On the other hand, the input selector switch 6 is switched so that the frequency divider 5 provides an input signal to the shift registers 41-4I, which provide a significant portion of the shift clock. For example, in Figure 2,
If the output of the first frequency divider is connected to the shift register 41, the input signal input when the first frequency divider output is at a high level is switched to be applied to the shift register 41. .

In this way, the input signal is sequentially supplied to each shift register 41-41 in synchronization with the input clock, and the shift registers 41-41 to which the input signal is supplied shift the internal data. That is, only one shift register 41 to 41 operates in response to one pulse of the input clock.

The output changeover switch 7 is switched in synchronization with the input clock so as to apply the outputs of the shift registers 41 to 41 to the data output terminal 3 in the order in which the shift operations were performed.

In this way, the number of stages of each shift register 41 to 41 is j,
Shift register 41 with output changeover switch 7 operating
~41 is selected, the input signal delayed by ix) pulses of the input clock is output to the data output terminal 3.
taken from.

FIG. 3 shows a delay circuit using a serial-parallel converter 8 on the input side and a parallel-serial converter 9 on the output side.

In this case, the serial/parallel converter 8 converts the input signal into 1-pit parallel data in synchronization with the input clock. Then, the frequency divider 5 has a frequency l of the input clock frequency.
/ Generates a shift clock of i. Each of the shift registers 41 to 41 inputs one of the outputs of the serial-to-parallel converter 8 and shifts internal data according to the shift clock. Since this shift clock also serves as a load input to the parallel-to-serial converter 9, the parallel-to-serial converter 9 takes in the outputs of each of the shift registers 41 to 41 at once using this shift clock.

Then, each piece of captured data is applied one by one to the data output terminal 3 in synchronization with the input clock.

In this case, although the shift registers 41 to 41 operate simultaneously, they operate only K1 times during a period corresponding to 7 l-pulses of the input clock, so that the same effect as shown in FIG. 1 is achieved.

FIG. 4 shows a delay circuit using a Puarbort RAM 12 as a delay element.

In this case, the counter 10 counts the read/write clock (output of the divider 5) whose frequency is l/i of the input clock frequency, and provides the counted value to the dual port RAM 12 as a write address. Further, a predetermined value is added to the count value of the counter 10 in an adder 11. The added value is the difference between the read address and the write address, and the added value is given to the pool port RAM as the read address. FIG. 4 shows a case where the difference between the write address and the read address is "1".

Therefore, the i-pit parallel data is stored in dual port RAM.
Parallel data is written to address 0 or 1 of the RAM 120, and at the same time, parallel data is read from address 0 or address 0 of the pool port RAM 1201, and the read parallel data is taken into the parallel-serial converter 9.

The parallel-to-serial converter 9 provides parallel data one by one to the data output terminal 3 in synchronization with the input clock. In addition,
In FIG. 4, the counter 10 whose count value can take rOJ[J and the adder 11 whose addition value is rtJ are shown.
If the added value is set to a value greater than or equal to "l", the amount of delay can be further increased.

Further, since the write operation and read operation of the dual port RAM 12 are performed only once in a period corresponding to 7 l-pulses of the input clock, power consumption can also be suppressed in this case.

FIG. 5 shows a delay circuit using RAMI 3 as a delay element. In this case, the branching unit 5 outputs a signal whose frequency is 1/1 of the input clock frequency as a write signal. Further, as a read signal, a signal whose output timing is separated by a predetermined pulse of the input clock from the output timing of the write signal is output. counter 1
0 counts the number of pulses of a signal whose frequency is 1/i of the input clock frequency, and the adder 11 calculates a predetermined value, which is the output timing difference between the read signal and the write signal, with respect to the count value of the counter 10. Add pulses. The changeover switch 14 is configured so that the count value of the counter 10 is applied to the address of the RAM 13 when a write signal is output, and the added value of the adder 11 is applied to the address of the RAM 13 when a read signal is output. It will switch so that it is displayed. Even with this configuration, effects similar to those shown in FIG. 4 can be obtained. Note that FIG. 6 shows an example when the difference between the write signal and the read signal is "1".

Further, in each of the above embodiments, the shift registers 41 to 41, the Puarbort RAM 12, or the RAM are used as delay elements.
13, other delay elements such as delay lines or CCDs may be used.

〔Effect of the invention〕

As described above, according to the present invention, the delay circuit is configured such that a plurality of delay elements are arranged in parallel so that they do not operate simultaneously, thereby reducing power consumption and making it suitable for battery-powered devices. effective.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a delay circuit according to an embodiment of the present invention, FIG. 2 is a timing diagram showing waveforms of main parts in the delay circuit shown in FIG. 1, and FIGS. The figures are block diagrams showing delay circuits according to other embodiments of the present invention, FIG. 6 is a timing diagram showing waveforms of the main parts of the delay circuit shown in FIG. 5, and FIG. 7 is a conventional delay circuit. It is a block diagram. 41~4! is a shift register (delay element), 5 is a frequency divider, 6 is an input changeover switch (input changeover means), 7 is an output changeover switch (output selection means), 8 is a serial/parallel converter, 9
is a parallel-to-serial converter, 10 is a counter, 11 is an adder, 1
2 is dual port RAM. 13 is RAM 0. In the figure, the same reference numerals indicate the same or equivalent parts. Patent applicant Mitsubishi Electric Co., Ltd. Agent Patent attorney 1) Hiroshi Sawa (2 others) Figures 41-4ε: Shift register ('14Mt+) (±'
Fig. 8: Parallel converter 9: Parallel converter Fig. 13: RAM Fig. (b) Input signal m==...J "] Ding= ( e) Write 4 signal
・・・ −↑−Figure

Claims (1)

[Claims] a frequency divider that creates a plurality of shift clocks having different phases from an input clock; a delay element that is provided corresponding to each of the plurality of shift clocks and introduces the corresponding shift clock; and a delay element that is synchronized with the input clock. A delay circuit comprising: input switching means for sequentially supplying an input signal to each of the delay elements; and output selection means for sequentially selecting an output of each of the delay elements.