JP2000275308A - Test pattern generator for semiconductor test system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a test pattern generator in which useless consumption of memory capacity is eliminated by an arrangement wherein an n channel parallel data and an n channel parallel data read out previous time are multiplexed by n and a specified high speed test pattern is outputted in order to reduce redundancy circuit. SOLUTION: A serial.parallel converting section 40 divides the frequency of a high speed clock signal ScIk 1/n to produce a low speed sync clock. The serial.parallel converting section 40 also divides the phase of an inputted control signal 10s into n channels(ch) and an n-ch phase division control signal is subjected to retiming conversion to produce an n-ch frequency division control signal synchronized with a low speed sync clock. Furthermore, an address pointer 120 generates a common address signal for accessing an n-ch low speed memory address based on the n-ch frequency division control signal. A read control section 60 reads out an n-ch low speed memory and then an n-ch parallel read data and a retained data are multiplexed by n at an output selector section 410 and a parallel.serial converting section 420 to produce a specified highspeed pattern.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a test pattern generator for a semiconductor test device. In particular, the present invention relates to a test pattern generator of a semiconductor test apparatus that generates a high-speed test pattern using a low-speed memory.

[0002]

2. Description of the Related Art A conventional technique will be described below with reference to FIG. 5 showing a principle configuration diagram of a high-speed test pattern generation by reading RAM data by an interleaving method. In this figure, the number of interleaving phases is n. In this device, a low-speed memory is applied to an interleave configuration to generate high-speed data. Since the semiconductor test apparatus is well-known and well-known in the art, the description of the configuration of the entire system is omitted. The components in FIG. 5 include an interleave expansion unit 540, a read control unit 560,
Address pointer (AP) 570 and memory (RA)
M) 580, and an interleave restoration unit 590.

[0003] The interleave expansion section 540 divides the high-speed clock signal Sclk into 1 / n, generates n divided clocks divided at a predetermined timing, and supplies the generated clocks to the corresponding phases. Further, upon receiving the control signal 10s, the same control signal is supplied to the n-phase interleaving to each corresponding phase. Here, it is assumed that the input control signal 10s is a 1-bit control signal for controlling the count-up enable for the address counter of the AP 570. still,
The clock frequency of the high-speed clock signal Sclk is arbitrary (for example, 500 MHz to 1 MHz or less) depending on operating conditions, and the clock frequency is a clock signal that can be dynamically changed or temporarily stopped.

A read control unit 560 includes read control units # 1 to #n for n channels, and individually controls reading of a memory. Each read control unit operates at a timing synchronized with the phase separation clock, and when the phase control signal is a valid signal, counts up to the AP.
Provides an enable signal.

The AP 570 is, for example, an address counter having a width of, for example, 20 bits, which includes address pointers AP # 1 to AP # n of n channels and individually supplies an address signal for accessing a memory. Each address pointer counts up from the corresponding read control unit.
Upon receiving the enable signal, the value of the generated address signal is incremented by one.

The RAM 580 is an n-channel RAM #
1 to RAM # n. Each RAM receives an address signal from a corresponding address pointer and outputs read data obtained by reading the memory content of the address. Of course, the output timing of the read data is output at each interleave timing. The word length of the data to be read varies depending on the system configuration, but extends to several hundred bits or more.

[0007] The interleave restoration section 590 receives low-speed read data sequentially read out by n-channel interleaving, and outputs a high-speed test pattern subjected to deinterleaving conversion at a timing synchronized with the high-speed clock signal Sclk.

[0008] The conventional apparatus has the following disadvantages because it is realized by an interleaved configuration. First, since each interleaved phase is operated by a phase-divided clock of an individual timing, n
The read control units # 1 to #n of the channels need to have the same circuit configuration, and the address pointer A of the n channel
P # 1 to #n also require the same circuit configuration. Since it is necessary to provide these same circuits for n channels, there is a problem that the circuits become redundant. Second, the interleave restoration unit 590 needs to output a test pattern for each edge of the high-speed clock signal Sclk. On the other hand, because of the interleave method, the test pattern to be output is in a form in which the next phase outputs the test pattern sequentially for each edge of the high-speed clock signal Sclk. Therefore, for example, when the same data (solid pattern) continues for k clock times, it becomes necessary to store the same data for a total of k words in phases on each interleaved memory corresponding to the k clock period. . This may be a waste of several percent or more of the entire memory capacity depending on the test mode. In this regard, there is a significant disadvantage that the memory capacity is wasted.

[0009]

As described above, in the prior art, the first problem is that the circuit becomes redundant.
Has the disadvantage that the memory capacity is wasted. Therefore,
The problem to be solved by the present invention is to reduce redundant circuits,
An object of the present invention is to provide a test pattern generation device for a semiconductor test device that eliminates wasteful consumption of memory capacity.

[0010]

First, in order to solve the above-mentioned problems, in the configuration of the present invention, an n-channel low-speed memory is provided, an n-times high-speed test pattern is generated and output, and the high-speed test pattern is output. In the test pattern generator of the semiconductor test apparatus, the conditions for generating the high-speed test pattern to be output are controlled in response to the control signal 10s input in synchronization with the high-speed clock signal Sclk which is the generation cycle of the high-speed clock signal Sclk. A means for generating a low-speed synchronous clock (for example, 1 / nclk, divided clock clk2) obtained by dividing the clock signal Sclk by 1 / n is provided. The input control signal 10s is divided into n channels and divided. means for retiming conversion of the n-channel phase-dividing control signal into an n-channel parallel frequency-dividing control signal synchronized with the low-speed synchronization clock; Memory address generation control means for generating a common address signal for accessing an n-channel low-speed memory address based on the parallel frequency division control signal of the channel, and accessing the n-channel low-speed memory by the common address signal. Multiplexed output means for receiving the read n-channel parallel read data and the previously read n-channel parallel read data (hold data) and multiplexing them n times to generate and output a predetermined high-speed test pattern; A test pattern generation device for a semiconductor test device, comprising: According to the above-described invention, a test pattern generator of a semiconductor test apparatus can be realized in which redundant circuits are reduced and unnecessary consumption of memory capacity is eliminated.

The means for generating the low-speed synchronous clock and the means for retiming conversion to the parallel frequency division control signal include a test pattern generation device of the above-described semiconductor test device, which is the serial / parallel conversion unit 40.

Further, as the memory address generation control means, there is a test pattern generation device of the above-described semiconductor test device which is an address pointer (AP) 120.

As the multiplex output means, there is a test pattern generator of the above-described semiconductor test apparatus comprising a read control section 60, an output selector section 410, and a parallel / serial conversion section 420.

FIG. 2 shows a solution according to the present invention. Secondly, in order to solve the above problem, in the configuration of the present invention, an n-channel low-speed memory is provided to generate and output an n-times high-speed high-speed test pattern, and a high-speed clock signal Sclk which is a generation cycle of the high-speed test pattern In a test pattern generator of a semiconductor test apparatus in which the condition for generating the high-speed test pattern to be output is controlled in response to the control signal 10s input in synchronization with the control signal 10s
Is the address increment enable signal for enabling the address increment (address + 1) of the read address of the memory storing the test pattern. When the number of phases n = 2, the high-speed clock signal S
A low-speed synchronizing clock (for example, 1/2 clk, a frequency-divided clock clk2) that divides clk into し て and synchronizes the low-speed circuit thereafter is generated, and receives the control signal 10s to divide it into two phases. A serial-to-parallel converter 40 for generating and outputting a 2-channel 1-bit parallel frequency division control signal obtained by retiming the divided control signal with a low-speed synchronous clock; Receiving the two-channel 1-bit parallel frequency division control signal and the output signal output by the address pointer (AP) itself, the number of effective signals of the two-channel parallel frequency division control signal is compared with the previous AP output value. The result of adding the corresponding values is latched and output as an AP output value, and the number of channels n is set to 2
When expressed as an exponent of the power of m, an address pointer that outputs the lower m = 1 bit width in the AP output value as the residual value information 120b, and supplies the other upper bits as address signals 120s to the memories 201 to 202. (AP)
And m-bit width residual value information 12 from the AP.
0b and a predetermined one-channel parallel frequency division control signal output from the serial / parallel conversion unit 40, firstly, re-timing the addition result obtained by adding the two and the carry signal to a predetermined value Then, the second selector control signal 66s2 is supplied to the output selector unit 410 as the second selection control signal 66s2.
A read control unit 60 for supplying the first selection control signal 66s1 to the address 0, an address signal 120s from the AP at an address input terminal, and reading and outputting the contents of the address. The two-channel holding registers 301 to 302 receive the two-channel read data 201 s to 202 s output from the two-channel memories 201 to 202 and output the two-channel holding data 301 s to 302 s retimed by the low-speed synchronous clock. 302, receiving two-channel read data 201s-202s output from two-channel memories 201-202, receiving two-channel holding data 301s-302s output from two-channel holding registers 301-302. , The read control unit 60 Selection control signal 66s received from
An output selector unit 410 outputs two-channel parallel data 410 s selected in accordance with 1, 66 s 2, and receives two-channel parallel data 410 s from the output selector unit 410. There is provided a test pattern generator for a semiconductor test apparatus, comprising: a parallel / serial converter 420 that outputs a high-speed test pattern 420s multiplexed in a ratio of 1: 1.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the drawings together with embodiments.

FIG. 2 is a block diagram of the main part of the parallel pattern generator of FIG. 1; FIG. 2 is a specific block diagram of the two-phase parallel system; FIG. 3 is a timing chart for explaining the operation of FIG. This will be described below with reference to FIG. 6 and another specific configuration diagram of the two-phase parallel system in FIG.

First, the configuration of the present invention shown in FIG. 1 will be described. FIG. 1 shows a test pattern generator of a semiconductor test apparatus that generates an n-fold high-speed test pattern by using an n-channel low-speed memory. The test pattern generator includes a serial / parallel converter 40, a read controller 60, The address pointer (AP) 120, the memory (RAM) 200, the holding register 300, the output selector 410,
And a serial converter 420. It is assumed that the control signal 10s input in synchronization with the high-speed clock signal Sclk is an address increment enable signal for enabling the address increment (+1) of the read address of the memory storing the test pattern.

The serial / parallel converter 40 divides the high-speed clock signal Sclk by 1 / n to generate a low-speed synchronous clock 1 / nclk for operating the subsequent low-speed circuits in synchronization, and receives the control signal 10s. Into n phases,
An n-channel parallel frequency division control signal in which the phase-divided control signal is retimed (timed) by a low-speed synchronous clock is generated and output.

The address pointer (AP) 120 receives the 1-bit parallel frequency division control signal output from the serial / parallel conversion unit 40 and the output signal output by the address pointer (AP) itself when receiving the n-channel signal. A
When the AP output value obtained by adding the number of valid signals of the address increment enable signal of the n-channel of the parallel frequency division control signal to the P output value is latched, and when n is expressed by an exponent of 2 m, The lower m-bit width of the AP output value is output as the residual value information 120b, and the other upper bits are output as the address signal 120s.

The read control unit 60 stores the m-bit width residual value information 120b from the AP and the serial / parallel conversion unit 4
In response to the parallel division control signal of the (n-1) -th channel output from 0, first, the addition result obtained by adding the two and the carry signal are retimed in a predetermined manner to the output selector unit 410. The remaining value information 120b is supplied to the output selector unit 410 as the first selection control signal 66s1 at a predetermined timing.

The n-channel memories 201 to 20n include:
An address signal 120s from the AP is received at an address input terminal, and the contents of the address are read and output.

N-channel holding registers 301 to 30
n receives the n-channel read data 201s to 20ns output from the n-channel memories 201 to 20n, and outputs the n-channel held data 301s to 30ns retimed by the low-speed synchronization clock.

Output selector 410 receives n-channel read data 201s-20ns output from n-channel memories 201-20n, and receives n-channel held data 301s-301 output from n-channel holding registers 301-30n. 30 ns, and both selection control signals 66s1, 66s received from the read control unit 60
The n-channel parallel data 410s selected in advance by s2 is output.

The parallel-to-serial converter 420 receives the n-channel parallel data 410s from the output selector 410 and outputs a high-speed test pattern 420s multiplexed to n: 1 corresponding to the number of phases n.

Next, as a specific example of the configuration of FIG.
= 2 will be further described. Here, it is assumed that the bit width of the address line of the RAM is 20 bits, that is, a memory of 1M words. Further, in the time chart of FIG. 3, the generation timing of the control signal 10s as the input signal is shown in FIG.
A specific example in which valid signals 1 to 9 are generated at nine locations as shown in FIG.

The serial / parallel converter 40 can be realized by flip-flops 41, 44, 45, flip-flops 42, 43 with latch enable, and clock phase dividing means 48. The high-speed clock signal Sclk generates two low-speed divided clocks clk1 and clk2 whose frequency is divided by 2 by the clock phase dividing means 48. In this figure, the second frequency-divided clock clk2 corresponds to the low-speed synchronization clock, and is used by the internal circuit as a reference edge. Here, each cycle period of the second frequency-divided clock clk2 is given as cycles C1 to C12 as shown in FIG. 3A. Note that if n =
In the case of eight phases, eight low-speed divided clocks cl
It is needless to say that k1 to clk8 are generated and any one of the eight divided clocks is used in the internal circuit as a reference edge. On the other hand, the control signal 10s shown in FIG.
Is divided into two phases by flip flops 42 and 43, and a parallel frequency division control signal 44 is generated by a frequency division clock clk2 having both phase divided signals 42s and 43s as the same reference edge.
s, 45 s (see FIGS. 3C and 3D) and output.

The address pointer (AP) 120 includes adding means 51, 52, OR means 53, and counting means 121.
Constitute a latched adder. this is,
The two parallel frequency division control signals 44s and 45s are transmitted to the previous AP.
It is added to the overall output value (upper and lower output values) and latched. Therefore, the entire AP output value is latched and updated at any increment value of +0, +1 and +2. If n = 8 phases, the latch is updated in increments from +0 to +7.
Incidentally, the counting means 121, the adding means 51, 52 and O
The components of the R means 53 are, as shown in the principle configuration of FIG.
This is equivalent to the configuration of the bit width latch register 129, and may be realized by the configuration of FIG. 6 if desired.

FIG. 4 shows an example of the internal circuit of the counting means 121. Higher bit side is count enable signal 53s
And a 1-bit latch register 124 which receives the addition signal 52s and latches it, since the lower bit side has n = 2 phases.
And can be realized. Here, if n = 8 phases, 2
It is needless to say that a latch register whose lower bit side has a 3-bit width is necessary from the expression of the exponent of the third power of. The upper bits output from the address count register 122 are supplied to the RAMs 201 and 202 as an address signal 120s. The low-order 1-bit residual value information 120b output from the latch register 124 is supplied to the adding means 52 for the next addition, and is also supplied to the adding means 64 and the flip-flop 65 as data selection information.

Referring to the time chart of FIG.
The overall output values are the parallel frequency division control signals 44s and 45s (FIG.
C and D) are added according to the number of effective signals of FIG.
As shown in the AP total output value of E, from cycle C3,
The process proceeds to 0, 1, 2, 4, 5, 7, and 9. As shown in FIG. 3F, the upper bits of the entire AP output value are # 0, # 0, # 1, # 2, # 2, # 3, # 4 from cycle C3.
As shown in FIG. 3G, the lower bits advance from cycle C3 to 0, 1, 0, 0, 1, 1, 0, 1.

The read control unit 60 includes an output selector 41
It is to generate a selection control signal to 0. This circuit configuration example includes an adding unit 64 and flip-flops 65 and 6.
6 can be realized. The adder 64 may be an adder with a 1-bit width input since n = 2 phases. Here, if n = 8 phases, a 3-bit width input adder is required. That is, a 2-bit width signal of a result obtained by receiving and adding the first parallel frequency division control signal 44s and the residual value information 120b output from the latch register 124 and the carry signal CY via the flip-flops 65 and 66. Then, the signal is supplied to the selection control input terminal of the second selector 412 as the second selection control signal 66s2. The residual value information 120b is also supplied to the selection control input terminal of the first selector 411 as the first selection control signal 66s1 via the flip-flops 65 and 66.
The time chart of the first selection control signal 66s1 is shown in FIG.
As shown in the figure, from cycle C4, L, L, H, L,
L, H, H, and L proceed. On the other hand, the second selection control signal 6
As shown in FIG. 3L, the time chart of 6s2 shows that # 0, # 1, # 2, # 1, # 1, # 2, # 2 from cycle C4.
Proceed to # 2, # 0.

The RAM 200 has a first RAM 201, a second RAM 201,
The RAM 202 receives the address signal 120s, reads out the contents of the address, and
The signals are supplied to the output selector unit 410 as 01s and 202s (see FIG. 3H). In the time chart of FIG. 3H, the read data at address "0" is represented as # 0 (1, 2M), and thereafter, the read data at address "1" is similarly referred to as # 0.
1 (1, 2M). Here, # 0 (1M)
Of the “1M” portion of the read data 20 of the first RAM 201
1s, and the “2M” portion of # 0 (2M) is stored in the second RAM 2
02 read data 202s.

The holding register 300 supplies data delayed by one clock period to the output selector unit 410. This is composed of a first holding register 301 and a second holding register 302, and receives RAM data 201s and 202s output from the corresponding RAMs 201 and 202,
The held data 301s and 302s (see FIG. 3J) retimed by the second frequency-divided clock clk2 are supplied to the output selector 410, respectively. In the time chart of FIG. 3J, both held data 301s and 302s of the address “0” are set to # 0.
(1, 2F), and thereafter, similarly, address “1”
Is expressed as # 1 (1, 2F). Here, the “1F” part of # 0 (1F) is set as the holding data 301s output by the first holding register 301, and
The “2F” portion of F) is referred to as held data 302 s output by the second held register 302.

The output selector section 410 can be realized by a two-input one-output type first selector 411 and a four-input one-output type second selector 412. One of the first selectors 411 stores the holding data 301 s and 302 from the holding register 300.
s, and outputs the parallel data 411s selected in accordance with the first selection control signal 66s1. FIG. 3M
As shown in the time chart of FIG. 7, the output parallel data 411 s starts from cycle C5, and starts from # 0 (1F), # 0
(1F), # 0 (2F), # 1 (1F), # 2 (1F)
F), # 2 (2F) and # 3 (2F).
The other second selector 412 outputs the R from the RAM 200
In response to the AM data 201 s and 202 s and the holding data 301 s and 302 s from the holding register 300, the parallel data 412 s selected in accordance with the second selection control signal 66 s2 is output. As shown in the time chart of FIG. 3N, the output parallel data 412s starts from cycle C5, and starts from # 0 (1F), # 0 (2F), # 1 (1
M), # 1 (2F), # 2 (2F), # 3 (1M), #
4 (1M) is selectively output.

The parallel-to-serial conversion unit 420 multiplexes low-speed two-phase parallel data into one-phase high-speed data. The data selector 421 has two inputs and one output.
And the flip-flop 422 for retiming. That is, the first frequency-divided clock clk1 having a duty ratio of 50% of H / L is supplied to the selection control input terminal of the data selector 421, and the parallel data 411s and 412s are received and alternately selected and output for multiplexing. Retiming is performed by the flip-flop 422 to generate and output high-speed output data 420 s synchronized with the target high-speed clock signal Sclk. As shown in the time chart of FIG. 3P, the output data 420s to be output is # 0 (2F) in cycle C7 and # 1 (1F) in cycle C8.
M) and # 1 (1F), in cycle C9, # 1 (2F)
And # 2 (1F) in cycle C10.
However, in cycle C11, # 3 (1M) and # 3 (2F)
However, in cycle C12, # 4 (1M) is selected and output.

According to the configuration of the present invention described above, first, for example, k
When it is necessary to continuously output the same data (solid pattern) in the clock time, the control signal 10s is given an invalid signal in the k-clock period, so that the AP 12
0 is temporarily stopped, and the output data 420 s output from the parallel / serial conversion unit 420 can continuously output a solid pattern. As a result, a great advantage is obtained that wasteful consumption of memory capacity can be eliminated. Second,
In the circuit configuration, as a result of operating in synchronism with the clocks of the same reference edge that are phase-separated, the read control unit 60 and the address pointer 120, which are reduced from n systems to one system, suffice, so that the circuit scale can be greatly reduced. Can be

The configuration of the present invention is not limited to the above embodiment. That is, the desired number of phases of 2 or more can be applied to the number of phases n. At this time, the number of phases n is arbitrary, but it is preferable to apply the number of phases in an exponential relation of n = 2 to the m-th power because the control does not become complicated.

[0037]

According to the present invention, the following effects can be obtained from the above description. As described above, according to the present invention, the advantage that unnecessary consumption of memory capacity is eliminated,
The advantage that redundant circuits can be reduced can be obtained. Therefore, the technical effect of the present invention is great, and the industrial economic effect is also great.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a main part of a parallel type pattern generation unit according to the present invention.

FIG. 2 is a specific configuration diagram of a two-phase parallel system according to the present invention.

FIG. 3 is a timing chart for explaining the operation of FIG. 2;

FIG. 4 is an internal configuration diagram of an address pointer (AP).

FIG. 5 is a configuration diagram of a main part of a conventional interleaved pattern generation unit.

FIG. 6 is another specific configuration diagram of the two-phase parallel system of the present invention.

[Explanation of symbols]

40 serial / parallel converter 41,42,43,44,45,65,66,422
Flip flop 48 Clock phase dividing means 51, 52, 64 Addition means 53 OR means 60, 560 Read control unit 120, 570 Address pointer (AP) 121 Counting means 122 Address count register 124 Latch register 128 Adder 129 Latch register 200- 20n, 580 Memory (RAM) 300 to 30n Holding register 410 Output selector section 411 First selector 412 Second selector 420 Parallel / serial conversion section 421 Data selector 540 Interleave expansion section 590 Interleave restoration section

Claims (5)

[Claims] 1. An n-channel low-speed memory is provided to generate and output an n-times high-speed high-speed test pattern, and to correspond to a control signal input in synchronization with a high-speed clock signal that is a generation cycle of the high-speed test pattern. A test pattern generating apparatus for a semiconductor test apparatus in which the conditions for generating the high-speed test pattern to be output are controlled, a means for generating a low-speed synchronous clock obtained by dividing the high-speed clock signal by 1 / n; Means for dividing the control signal into n channels and retiming converting the divided n-phase control signals into n-channel parallel frequency division control signals synchronized with the low-speed synchronization clock; Memory address generation control means for generating a common address signal for accessing an n-channel low-speed memory address based on the frequency division control signal; The n-channel parallel read data read by accessing the n-channel low-speed memory by the address signal and the previously read n-channel parallel read data are received and multiplexed n times to form a predetermined high-speed test pattern. And a multiplex output means for generating and outputting. A test pattern generation apparatus for a semiconductor test apparatus, comprising: 2. The test pattern generator according to claim 1, wherein the means for generating a low-speed synchronous clock and the means for retiming conversion to a parallel frequency division control signal are serial / parallel converters. 3. The test pattern generator according to claim 1, wherein the memory address generation control means is an address pointer (AP). 4. The test pattern generator according to claim 1, wherein the multiplex output means comprises a read control section, an output selector section, and a parallel / serial conversion section. 5. An n-channel low-speed memory is provided to generate and output an n-fold high-speed high-speed test pattern, and to correspond to a control signal input in synchronization with a high-speed clock signal that is a generation cycle of the high-speed test pattern. A test pattern generator of a semiconductor test apparatus in which the conditions for generating the high-speed test pattern to be output are controlled, wherein the control signal is an address increment (address + 1) of a read address of a memory storing the test pattern.
When the number of phases is n = 2, the high-speed clock signal is frequency-divided by 1/2 to generate a low-speed synchronous clock for operating the subsequent low-speed circuits in synchronization. Receiving the control signal, dividing the control signal into two phases, and generating and outputting a 2-channel 1-bit parallel frequency division control signal in which the divided control signal is retimed (timed) by the low-speed synchronous clock. Receiving a two-channel 1-bit parallel frequency division control signal output from the serial-parallel converter and an output signal output by the address pointer (AP) itself,
When the result of adding the value corresponding to the number of effective signals of the two channels of the parallel frequency division control signal to the P output value is latched and output as an AP output value, and the number of channels n is represented by an exponent of 2 m An address pointer (AP) for outputting the lower m = 1 bit width among the AP output values as residual value information and supplying the other upper bits to the memory as an address signal; Upon receiving the value information and a predetermined one-channel parallel frequency division control signal output from the serial / parallel conversion unit, firstly, the result of addition of the two and the carry signal are retimed to a predetermined value. A read control unit which supplies the output selector unit 410 as a second selection control signal, and secondly retimed the residual value information and supplies it to the output selector unit as a first selection control signal; A two-channel memory that receives a dress signal at an address input terminal and reads and outputs the contents of the address; and a two-channel memory that receives two-channel read data output from the two-channel memory and retiming with a low-speed synchronous clock. A two-channel holding register for outputting the held data of the channel; a two-channel read data output from the two-channel memory; a two-channel held data output from the two-channel holding register; An output selector unit for outputting two-channel parallel data selected in accordance with the two selection control signals received from the read control unit; and receiving two-channel parallel data from the output selector unit to correspond to two phases. A parallel serial that outputs high-speed test patterns multiplexed 2: 1 A test pattern generation device for a semiconductor test device, comprising: an Al conversion unit;