CN115664413A - Phase adjusting circuit of frequency division clock - Google Patents
Phase adjusting circuit of frequency division clock Download PDFInfo
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- CN115664413A CN115664413A CN202211144662.7A CN202211144662A CN115664413A CN 115664413 A CN115664413 A CN 115664413A CN 202211144662 A CN202211144662 A CN 202211144662A CN 115664413 A CN115664413 A CN 115664413A
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Abstract
The invention provides a phase adjustment circuit of a frequency division clock, comprising: the phase control word generating circuit is used for generating a group of control words according to a reference clock and a frequency division clock needing to be adjusted; and the clock adjusting circuit is connected with the phase control word generating circuit and used for adjusting the phase of the frequency division clock according to the control word and acquiring the frequency division synchronous clock synchronous with the reference clock. The invention can quickly adjust the clock phase in real time by taking the half period of the system clock as the step, does not lose the sampling edge of the clock, and can be applied to integrated circuits with higher requirements on sampling precision.
Description
Technical Field
The invention belongs to the technical field of integrated circuits, and particularly relates to a phase adjustment circuit of a frequency division clock.
Background
The multi-chip synchronization technology is widely applied to systems needing time relation determination, such as communication, radar, distributed data acquisition and the like, and is used for time coordination among a plurality of chips or subsystems.
In the prior art, the method for synchronizing the local clock to the reference signal sysref is mainly realized by forcibly clearing the phase of the clock signal by using the reference signal sysref, and the method has the advantages that the realization circuit is simple, and the method can be realized only by designing a phase clearing circuit by using an analog circuit.
Disclosure of Invention
The invention provides a phase adjustment circuit of a frequency division clock, which aims to solve the problem that the sampling edge of the clock is lost when the existing clock is synchronized.
Based on the above object, an embodiment of the present invention provides a phase adjustment circuit for a frequency-divided clock, including: the phase control word generating circuit is used for generating a group of control words according to a reference clock and a frequency division clock needing to be adjusted; and the clock adjusting circuit is connected with the phase control word generating circuit and used for adjusting the phase of the frequency division clock according to the control word and acquiring the frequency division synchronous clock synchronous with the reference clock.
Optionally, the phase control word generating circuit determines a phase offset value to be adjusted according to the input divided clock and the reference clock, and generates a control word according to the phase offset value; and the clock adjusting circuit adjusts the phase of the frequency division clock according to the control word to obtain the frequency division synchronous clock corresponding to the frequency division clock.
Optionally, the frequency division clock is 2 n Frequency division clock, the number of said control words is 2 n+1 N is an integer of 0 or more.
Optionally, the clock adjusting circuit includes a fundamental frequency adjusting circuit, and the fundamental frequency adjusting circuit includes: the input ends of the first branch adjusting circuit and the second branch adjusting circuit are used for receiving the input of the control word, the output end of the first branch adjusting circuit is connected with the first input end of the first data selector, and the output end of the second branch adjusting circuit is connected with the second input end of the first data selector.
Optionally, the first branch adjusting circuit performs even-numbered half-cycle delay on the input frequency-divided clock by taking a half cycle of a system clock as a step, and generates a first adjusting clock signal in phase with the frequency-divided clock according to the control word; the second branch adjusting circuit performs odd half-period delay on the frequency division clock by taking a half period of the system clock as a step, generates a second adjusting clock signal which is opposite to the frequency division clock according to the control word, and the first data selector selects one of the first adjusting clock signal or the second adjusting clock signal to output.
Optionally, the first branch adjusting circuit includes: the first NAND gate, the second NAND gate, the third NAND gate and the first delayer; the output end of the first nand gate is connected with the first input end of the first data selector, one input end of the first nand gate is connected with the output end of the first delayer, and the other input end of the first nand gate is connected with a system clock; the first input end of the second NAND gate is used as an input end or is suspended, the second input end of the second NAND gate is connected with a first enabling signal, the first input end of the third NAND gate is connected with the output end of the second NAND gate, the second input end of the third NAND gate is connected with a first control word or a second enabling signal, and the output end of the third NAND gate is connected with the input end of the first delayer.
Optionally, the second branch adjusting circuit includes: a fourth NAND gate, a fifth NAND gate, a sixth NAND gate and a second delayer; the output end of the fourth NAND gate is connected with the second input end of the first data selector, the first input end of the fourth NAND gate is connected with the output end of the second delayer, and the second input end of the fourth NAND gate is connected with a system clock; the first input end of the fifth NAND gate is used as an input end or is suspended, the second input end of the fifth NAND gate is connected with a third enabling signal, the first input end of the sixth NAND gate is connected with the output end of the fifth NAND gate, the second input end of the sixth NAND gate is connected with a second control word or a fourth enabling signal, and the output end of the sixth NAND gate is connected with the input end of the second delayer.
Optionally, if the frequency-divided clock is a frequency-divided-by-1 clock, a first input end of the second nand gate and a first input end of the fifth nand gate are suspended, a second input end of the third nand gate is connected to the first control word, and a second input end of the sixth nand gate is connected to the second control word;
and if the frequency-divided clock is an n-frequency-divided clock larger than 1, the first input ends of the second NAND gate and the fifth NAND gate are used as input ends, the second input end of the third NAND gate is connected with a second enable signal, and the second input end of the sixth NAND gate is connected with a third enable signal.
Optionally, if the divided clock is 2 with n being greater than or equal to 1 n The clock adjusting circuit also comprises a plurality of delay control units which are arranged in n stages in series, and the ith stage comprises 2 stages connected in parallel i+1 I =1, 2, \ 8230 \ 8230;, n of the delay control unit.
Optionally, the delay control unit includes: the input end of the third delayer and the input end of the fourth delayer are connected with the control word or the output end of the second data selector at the next stage, the output end of the third delayer is connected with the first input end of the second data selector at the current stage, the output end of the fourth delayer is connected with the second input end of the second data selector at the current stage, and the output end of the second data selector at the current stage is connected with the fundamental frequency adjusting circuit or the third delayer or the fourth delayer at the previous stage.
The invention has the beneficial effects that: as can be seen from the foregoing description, an embodiment of the present invention provides a phase adjustment circuit for a divided clock, including: the phase control word generating circuit is used for generating a group of control words according to a reference clock and a frequency division clock needing to be adjusted; and the clock adjusting circuit is connected with the phase control word generating circuit and used for adjusting the phase of the frequency division clock according to the control word, acquiring the frequency division synchronous clock synchronous with the reference clock, and quickly adjusting the clock phase in real time by taking the half period of the system clock as stepping to realize the switching between any two phases without losing the sampling edge of the clock, so that the clock adjusting circuit can be applied to an integrated circuit with higher requirement on sampling precision.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a phase adjustment circuit of a frequency-divided clock according to an embodiment of the present invention;
FIG. 2 is a schematic structural diagram of a baseband adjustment circuit according to an embodiment of the present invention;
FIG. 3 is a diagram illustrating a phase adjustment relationship of a baseband adjustment circuit according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a phase adjustment circuit of a frequency division by 2 clock according to an embodiment of the present invention;
FIG. 5 is a diagram illustrating a phase adjustment relationship of a phase adjustment circuit of a frequency division by 2 clock according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of a phase adjustment circuit of a 4-way clock according to an embodiment of the present invention;
fig. 7 is a schematic diagram of a phase adjustment relationship of a phase adjustment circuit of a frequency-divided-by 4 clock according to an embodiment of the present invention.
Detailed Description
For the purpose of promoting a better understanding of the objects, aspects and advantages of the present disclosure, reference is made to the following detailed description taken in conjunction with the accompanying drawings.
It is to be noted that technical terms or scientific terms used in the embodiments of the present invention should have the ordinary meanings as understood by those having ordinary skill in the art to which the present disclosure belongs, unless otherwise defined. The use of "first," "second," and the like in the embodiments of the present invention does not denote any order, quantity, or importance, but rather the terms "first," "second," and the like are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item preceding the word comprises the element or item listed after the word and its equivalent, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used only to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.
The embodiment of the invention provides a phase adjustment circuit of a frequency division clock. As shown in fig. 1, the phase adjustment circuit of the divided clock includes: a phase control word generating circuit 1 for generating a set of control words CTRL according to a reference clock sysref and a frequency-divided clock to be adjusted; and the clock adjusting circuit 2 is connected with the phase control word generating circuit 1 and is used for adjusting the phase of the frequency division clock according to the control word CTRL to obtain the frequency division synchronous clock synchronized with the reference clock sysref. In fig. 1, clk _ div1 is a frequency division 1 clock, that is, the system clock of the embodiment of the present invention, clk _ div2 is a frequency division 2 clock, clk _ div3 is a frequency division 3 clock, clk _ div4 is a frequency division 4 clock, clk _ div1_ adjusted is a frequency division 1 synchronous clock, clk _ div2_ adjusted is a frequency division 2 synchronous clock, clk _ div3_ adjusted is a frequency division 3 synchronous clock, and clk _ div4_ adjusted is a frequency division 4 synchronous clock.
In the embodiment of the present invention, the phase control word generating circuit 1 determines a phase offset value to be adjusted according to the input divided clock and the reference clock sysref, and generates the control word CTRL according to the phase offset value; the clock adjusting circuit 2 adjusts the phase of the frequency division clock according to the control word CTRL, so that the phase of the frequency division clock is shifted to obtain the frequency division synchronous clock corresponding to the frequency division clock, thereby realizing synchronization of the frequency division clock and the reference signal sysref. The embodiment of the invention can quickly adjust the clock phase in real time according to the phase relation between the reference signal sysref and the frequency division clock, does not lose the sampling edge of the clock in the adjustment process, and can be applied to an integrated circuit with higher requirement on the sampling precision.
In the embodiment of the invention, the frequency division clock is 2 n The clock is divided, the number of control words CTRL is 2 n+1 N is an integer of 0 or more.
As shown in fig. 2, the clock adjusting circuit 2 includes a baseband frequency adjusting circuit 21, and the baseband frequency adjusting circuit 21 includes: the circuit comprises a first data selector MUX1, and a first branch adjusting circuit 211 and a second branch adjusting circuit 212 connected to the first data selector MUX1, wherein input ends of the first branch adjusting circuit 211 and the second branch adjusting circuit 212 are configured to receive an input of the control word CTRL, an output end of the first branch adjusting circuit 211 is connected to a first input end of the first data selector MUX1, and an output end of the second branch adjusting circuit 212 is connected to a second input end of the first data selector MUX 1. The first branch adjusting circuit 211 performs even-numbered half-cycle delay on the input frequency-divided clock by taking a half cycle of a system clock clk _ div1 as a step, and generates a first adjusting clock signal in phase with the frequency-divided clock according to the control word CTRL; the second branch adjusting circuit 212 performs odd half-period delay on the frequency-divided clock by taking a half period of the system clock clk _ div1 as a step, and generates a second adjusting clock signal inverted to the frequency-divided clock according to the control word CTRL, where the first data selector MUX1 selects one of the first adjusting clock signal and the second adjusting clock signal to output.
With continued reference to fig. 2, the first branch adjustment circuit 211 includes: a first nand gate 2110, a second nand gate 2111, a third nand gate 2112, and a first delay 2113; an output end of the first nand gate 2110 is connected to a first input end of the first data selector MUX1, an input end of the first nand gate 2110 is connected to an output end of the first delay 2113, and the other input end of the first nand gate 2110 is connected to a system clock clk _ div1; a first input end of the second nand gate 2111 is used as an input end or is suspended, a second input end of the second nand gate 2111 is connected with a first enable signal, a first input end of the third nand gate 2112 is connected with an output end of the second nand gate 2111, a second input end of the third nand gate 2112 is connected with a first control word or a second enable signal, and an output end of the third nand gate 2112 is connected with an input end of the first delay 2113.
The second branch adjusting circuit 212 includes: a fourth nand gate 2120, a fifth nand gate 2121, a sixth nand gate 2122, and a second delayer 2123; the output end of the fourth nand gate 2120 is connected to the second input end of the first data selector MUX1, the first input end of the fourth nand gate 2120 is connected to the output end of the second delay 2123, and the second input end of the fourth nand gate 2120 is connected to the system clock clk _ div1, specifically to the inverted system clock clk _ div1; a first input end of the fifth nand gate 2121 is used as an input end or is suspended, a second input end of the fifth nand gate 2121 is connected to a third enable signal, a first input end of the sixth nand gate 2122 is connected to an output end of the fifth nand gate 2121, a second input end of the sixth nand gate 2122 is connected to a second control word or a fourth enable signal, and an output end of the sixth nand gate 2122 is connected to an input end of the second delay unit 2123.
In an embodiment of the invention, the first delay 2113 is used for generating an odd multiple of the half-cycle delay of the system clock clk _ div 1. The second delay 2123 is used to generate an even multiple of the half-period delay of the system clock clk _ div 1. If the divided clock is a 1 divided clock, CTRL0 and CTRL2 in FIG. 2 are enable signals, and CTRL1 and CTRL3 are control words. If the divided clock is a divided-by-n clock, and n is greater than or equal to 2, CTRL0, CTRL1, CTRL2, and CTRL3 in FIG. 2 are all enable signals. Specifically, if the divided clock is a 1-divided clock, the first input of the second nand gate 2111 and the first input of the fifth nand gate 2121 are floating, the second input of the second nand gate 2111 is connected to the first enable signal CTRL0, the second input of the fifth nand gate 2121 is connected to the third enable signal CTRL2, the second input of the third nand gate 2112 is connected to the first control word CTRL1, and the second input of the sixth nand gate 2122 is connected to the second control word CTRL3. The floating gate defaults to 1, and the first input end of the second nand gate 2111 and the first input end of the fifth nand gate 2121 can also be directly connected to the high level 1. The 1-divided clock clk _ div1 and the phase relationship thereof are shown in fig. 3, where clk _ div1 phase 0 represents a first adjusted clock signal having the same phase as the 1-divided clock clk _ div1, and clk _ div1 phase 1 represents a second adjusted clock signal obtained by shifting the 1-divided clock clk _ div1 by half the phase of the system clock, that is, a clock signal having the opposite phase to the 1-divided clock clk _ div 1.
Referring to fig. 4 and 6, if the divided clock is an n-divided clock greater than 1, the first input terminal of the second nand gate 2111 and the first input terminal of the fifth nand gate 2121 serve as input terminals, the second input terminal of the third nand gate 2112 is connected to the second enable signal CTRL1, and the second input terminal of the sixth nand gate 2122 is connected to the fourth enable signal CTRL3.
With continued reference to FIGS. 4 and 6, if the divided clock is 2 with n greater than or equal to 1 n The clock adjusting circuit 2 further comprises a plurality of delay control units 22, the delay control units 22 are arranged in n stages in series, the ith stage comprises 2 stages connected in parallel i+1 I =1, 2, \ 8230 \ 8230;, n of the delay control unit. 2 in the i-th stage i+1 The delay control units 22 are arranged in parallel. The output end of the first stage delay control unit 22 is connected to the fundamental frequency adjusting circuit 21, the output ends of the other stages of delay control units 22 are connected to the input end of the previous stage delay control unit 22, and the input end of the last stage delay control unit 22 is connected to the control word CTRL.
The delay control unit 22 includes: the input end of the third delay unit 221 and the input end of the fourth delay unit 222 are connected to the control word or the output end of the second data selector MUX2 of the next stage, the output end of the third delay unit 221 is connected to the first input end of the second data selector MUX2 of the current stage, the output end of the fourth delay unit 222 is connected to the second input end of the second data selector MUX2 of the current stage, and the output end of the second data selector MUX2 of the current stage is connected to the fundamental frequency adjusting circuit 21, or is connected to the third delay unit 221 or the fourth delay unit 222 of the previous stage. The third delay 221 is used to generate an odd multiple of the half-cycle delay of the system clock clk _ div1, and the fourth delay 222 is used to generate an even multiple of the half-cycle delay of the system clock clk _ div 1.
Specifically, the first stage includes 2 delay control units 22, and an output terminal of the second data selector MUX2 in the first delay control unit 22 is connected to an input terminal of the first branch adjusting circuit 211 in the fundamental frequency adjusting circuit 21, and is specifically connected to a first input terminal of the second nand gate 2111. The output terminal of the second data selector MUX2 in the second delay control unit 22 is connected to the input terminal of the second branch adjusting circuit 212 in the baseband adjusting circuit 21, and is specifically connected to the first input terminal of the fifth nand gate 2121. The input ends of the third delayer 221 and the fourth delayer 222 in each delay control unit 22 of the last stage are respectively connected to different control words CTRL, and the output end of the second data selector MUX2 in each delay control unit 22 of the last stage is connected to the input end of the third delayer 221 of the previous stage or the input end of the fourth delayer 222. The input ends of the third delayer 221 and the fourth delayer 222 of each delay control unit 22 of the intermediate stage are respectively connected with the output end of the second data selector MUX2 in the delay control unit 22 of the subsequent stage. The output terminal of the second data selector MUX2 in each delay control unit 22 of the intermediate stage is connected to the input terminal of the third delay 221 or the input terminal of the fourth delay 222 of the previous stage.
Fig. 4 is a schematic structural diagram of a phase adjustment circuit of a frequency division 2 clock, where the phase adjustment circuit of the frequency division 2 clock includes a fundamental frequency adjustment circuit 21 and two delay control units 22 connected in parallel. The first-stage delay formed by the two delay control units 22 is connected in series with the fundamental frequency adjusting circuit 21, and outputs the 2-division synchronous clock clk _ div2_ adjusted. Where CTRL0-CTRL3 are enable signals and CTRL4-CTRL7 are control words. The phase adjustment relationship of the phase adjustment circuit of the frequency division clock of 2 is shown in fig. 5, wherein clk _ div2 phase 0, clk _ div2 phase 1, clk _ div2 phase 2, and clk _ div2 phase 3 are 4 possible phase delays of the output frequency division synchronous clock clk _ div2_ adjusted, and are sequentially different by a half cycle of the system clock. Specifically, the half period of a system clock is taken as a step, an A2 path generates N times (N is an integer) delay of A2-frequency division clock, a B2 path generates N +1/4 times delay of the 2-frequency division clock, a C2 path generates N +1/2 times delay of the 2-frequency division clock, and a D2 path generates N +3/4 times delay of the 2-frequency division clock. The control word generating circuit 1 generates control words CTRL4-CTRL7, the clock adjusting circuit 2 obtains clocks with 4 phases in total of 0, 1, 2 and 3, and one clock is selected from A2, B2, C2 and D2 to be output, so that the phase adjustment of the frequency division clock with 2 can be realized, and the clock can be switched between any two phases without losing sampling edges of the clock.
Fig. 6 is a schematic diagram of a phase adjustment circuit of a frequency-divided-by 4 clock, where the phase adjustment circuit of the frequency-divided-by 4 clock includes a baseband frequency adjustment circuit 21 and a plurality of delay control units 22. The delay control unit 22 is a two-stage delay unit, the first stage includes 2 delay control units 22 connected in parallel, and the second stage includes 4 delay control units 22 connected in parallel. The input end of the 4 delay control units 22 of the second stage is connected with the control word, the output end is connected with the input end of the 2 delay control units 22 of the first stage, the output end of the 2 delay control units 22 of the first stage is connected with the input end of the fundamental frequency adjusting circuit 21, and the 4-frequency division synchronous clock clk _ div4_ adjusted is output from the output end of the fundamental frequency adjusting circuit 21. Where CTRL0-CTRL3 are enable signals and CTRL4-CTRL11 are control words. The phase adjustment relationship of the phase adjustment circuit of the divided-by-4 clock is shown in fig. 7, where clk _ div4 phase 0, clk _ div4 phase 1, clk _ div4 phase 2, clk _ div4 phase 3, clk _ div4 phase 4, clk _ div4 phase 5, clk _ div4 phase 6, and clk _ div4 phase 7 are 8 phase delays generated by the phase adjustment circuit of the divided-by-4 clock, and sequentially differ by a half cycle of the system clock. Specifically, by taking a half period of a system clock as a step, an A4-path generates N times (N is an integer) delay of A4-frequency division clock, a B4-path clock generates N +1/8 times delay of the 4-frequency division clock, a C4-path generates N +1/4 times delay of the 4-frequency division clock, a D4-path generates N +3/8 times delay of the 4-frequency division clock, an E4-path generates N +1/2 times delay of the 4-frequency division clock, an F4-path generates N + 5/delay of the 4-frequency division clock, a G4-path generates N +3/4 times delay of the 4-frequency division clock, and an H4-path generates N +7/8 times delay of the 4-frequency division clock, wherein a control word generating circuit 1 generates control words CTRL4-CTRL11, clocks of 0, 1, 2, 3, 4, 5, 6 and 7 phases are obtained through a clock adjusting circuit 2, a clock of 0, 1, 2, 3, 4, 5, 6 and 7 phases are selected from the A4, B4, C4, D4, E4, F4, G4 and H4, a clock output phase can be switched, and any two clock output phases of the clock can be sampled without losing of the clock.
By analogy with the phase adjustment circuit of the frequency division clock of 1, 2 and 4 as reference, the phase adjustment circuit of the embodiment of the invention can perform 2 operations n Phase adjustment of frequency-divided clock (n is an integer) based on 2 n Frequency-divided clock generation 2 (n+1) Phase delay, stepped by half a period of the system clock, can produce 2 n N-fold delay of frequency-divided clock, 2 n fractional-N + 1/2 (n+1) Multiple phase delay, 2 n Divided N +2/2 (n+1) Multiple phase delay, \ 8230;, N + (2) n+1 -1)/2 (n+1) Time delay of the phase. Control word generating circuit 1 generates 2 n+1 A control word, 0-2 obtained by the clock adjusting circuit 2 (n+1) -1 Total 2 (n+1) A phase from 2 (n+1) One phase is selected from the phase outputs, namely 2 can be realized n The phase of the frequency division clock is adjusted, and the frequency division clock can be switched between any two phases without losing the sampling edge of the clock.
The phase adjustment circuit of the frequency division clock of the embodiment of the invention comprises: the clock adjusting circuit is used for adjusting the phase of the frequency division clock according to the control word to acquire the frequency division synchronous clock synchronous with the reference clock, can quickly adjust the clock phase in real time by taking the half period of the system clock as stepping, and can adjust the clock phase in pairs 1, 2, 4 and 2 n The phase of the frequency division clock is adjusted, and the frequency division clock can be switched between any two phases without losing the sampling edge of the clock, so that the frequency division clock can be applied to an integrated circuit with higher sampling precision requirement.
Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure is limited to these examples; within the context of the present application, technical features in the above embodiments or in different embodiments may also be combined, steps may be implemented in any order, and there are many other variations of the different aspects of the present application described above, which are not provided in detail for the sake of brevity.
This application is intended to embrace all such alternatives, modifications and variances that fall within the broad scope of embodiments of the present invention. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit and principles of the embodiments of the present invention are intended to be included within the scope of the present application.
Claims (10)
1. A phase adjustment circuit for a divided clock, the phase adjustment circuit comprising:
the phase control word generating circuit is used for generating a group of control words according to a reference clock and a frequency division clock needing to be adjusted;
and the clock adjusting circuit is connected with the phase control word generating circuit and used for adjusting the phase of the frequency division clock according to the control word and acquiring the frequency division synchronous clock synchronous with the reference clock.
2. The phase adjustment circuit according to claim 1, wherein the phase control word generation circuit determines a phase offset value to be adjusted based on the input divided clock and the reference clock, and generates the control word based on the phase offset value; and the clock adjusting circuit adjusts the phase of the frequency division clock according to the control word to obtain the frequency division synchronous clock corresponding to the frequency division clock.
3. The phase adjustment circuit of claim 1, wherein the divided clock is 2 n Frequency division clock, the number of said control words is 2 n+1 N is an integer of 0 or more.
4. The phase adjustment circuit of claim 1, wherein the clock adjustment circuit comprises a fundamental frequency adjustment circuit, the fundamental frequency adjustment circuit comprising: the input ends of the first branch adjusting circuit and the second branch adjusting circuit are used for receiving the input of the control word, the output end of the first branch adjusting circuit is connected with the first input end of the first data selector, and the output end of the second branch adjusting circuit is connected with the second input end of the first data selector.
5. The phase adjustment circuit of claim 4, wherein the first branch adjustment circuit delays the input divided clock by an even number times a half period in steps of a half period of a system clock and generates a first adjustment clock signal in phase with the divided clock based on the control word; the second branch adjusting circuit performs odd half-period delay on the frequency division clock by taking a half period of the system clock as a step, generates a second adjusting clock signal which is opposite to the frequency division clock according to the control word, and the first data selector selects one of the first adjusting clock signal or the second adjusting clock signal to output.
6. The phase adjustment circuit of claim 4, wherein the first branch adjustment circuit comprises: the first NAND gate, the second NAND gate, the third NAND gate and the first delayer; the output end of the first nand gate is connected with the first input end of the first data selector, one input end of the first nand gate is connected with the output end of the first delayer, and the other input end of the first nand gate is connected with a system clock; the first input end of the second NAND gate is used as the input end or is suspended, the second input end is connected with a first enabling signal, the first input end of the third NAND gate is connected with the output end of the second NAND gate, the second input end is connected with a first control word or a second enabling signal, and the output end of the third NAND gate is connected with the input end of the first delayer.
7. The phase adjustment circuit of claim 6, wherein the second branch adjustment circuit comprises: a fourth NAND gate, a fifth NAND gate, a sixth NAND gate and a second delayer; the output end of the fourth NAND gate is connected with the second input end of the first data selector, the first input end of the fourth NAND gate is connected with the output end of the second delayer, and the second input end of the fourth NAND gate is connected with a system clock; the first input end of the fifth NAND gate is used as an input end or is suspended, the second input end of the fifth NAND gate is connected with a third enabling signal, the first input end of the sixth NAND gate is connected with the output end of the fifth NAND gate, the second input end of the sixth NAND gate is connected with a second control word or a fourth enabling signal, and the output end of the sixth NAND gate is connected with the input end of the second delayer.
8. The phase adjustment circuit of claim 7, wherein if the divided clock is a divided-by-1 clock, the first input of the second nand gate and the first input of the fifth nand gate are floating, the second input of the third nand gate is connected to the first control word, and the second input of the sixth nand gate is connected to the second control word;
and if the frequency-divided clock is an n-frequency-divided clock larger than 1, the first input ends of the second NAND gate and the fifth NAND gate are used as input ends, the second input end of the third NAND gate is connected with a second enable signal, and the second input end of the sixth NAND gate is connected with a third enable signal.
9. The phase adjustment circuit according to claim 4, wherein if the divided clock is 2 where n is 1 or more n The clock adjusting circuit also comprises a plurality of delay control units which are arranged in n stages in series, and the ith stage comprises 2 stages connected in parallel i+1 I =1, 2, \8230; \ 8230;, n of the delay control units.
10. The phase adjustment circuit of claim 9, wherein the delay control unit comprises: the input ends of the third delayer and the fourth delayer are connected with the control word or the output end of the second data selector at the next stage, the output end of the third delayer is connected with the first input end of the second data selector at the current stage, the output end of the fourth delayer is connected with the second input end of the second data selector at the current stage, and the output end of the second data selector at the current stage is connected with the fundamental frequency adjusting circuit or the third delayer or the fourth delayer at the previous stage.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202211144662.7A CN115664413A (en) | 2022-09-20 | 2022-09-20 | Phase adjusting circuit of frequency division clock |
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| CN202211144662.7A CN115664413A (en) | 2022-09-20 | 2022-09-20 | Phase adjusting circuit of frequency division clock |
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2022
- 2022-09-20 CN CN202211144662.7A patent/CN115664413A/en active Pending
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