JPH08154105A - Base band signal generator for pi/4 shift qpsk quadrature modualtor - Google Patents

Abstract

PURPOSE: To reduce a storage capacity and to provide the π/4 shift QPSK modulation circuit of simple constitution. CONSTITUTION: Switching circuits 10 and 11 for constituting a digital filter switch and output address data outputted by respective two coordinate storage circuits 6 and 7 and the coordinate storage circuits 8 and 9 to a storage device 12 and the storage device 13 corresponding to switching signals T6 supplied by a timing generation circuit 5. That is, the switching circuit 10 and the switching circuit 11 supply the output of the two coordinate storage circuits to the storage device 12 and the storage device 13 in a time-division manner. A separation circuit 14 and the separation circuit 15 input data outputted by the storage device 12 and the storage device 13 in the time-division manner and separate them to the data of two systems respectively corresponding to the switching signals T6.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to a π / 4 shift QPSK.
The present invention relates to a baseband signal generator for a quadrature modulator.

[0002]

2. Description of the Related Art As a conventional technique of this type, the applicant has applied for the technique disclosed in Japanese Patent Application Laid-Open No. Hei 5-22355 (H04L727 / 20). This technique will be briefly described below with reference to FIG.

A baseband signal which is a modulated signal is serially input from an input terminal 101, serial-parallel converted by a symbol generating means 102, and converted into a 2-bit parallel signal. The generated 2-bit parallel signal is differentially encoded with the preceding symbol data by the differential encoding circuit 104 in the mapping circuit 103, and is then subjected to predetermined mapping by the mapping circuit 103. Converted to bit data.

The details of this mapping are described in the above-mentioned Japanese Patent Laid-Open No.
-22355, detailed description is omitted. The 2-bit data generated by mapping is stored in the coordinate accumulators 106, 10 at odd symbol timing.
7 is supplied to each one bit, and at the even symbol timing, one bit is supplied to each of the coordinate accumulators 108 and 109. Coordinate accumulators 106, 107, 10
8 and 109 are shift registers, which are mapping circuits 1
The data supplied from No. 03 is sequentially serial-parallel converted. The outputs of the coordinate accumulators 106, 107, 108 and 109 are storage devices 110, 111, 112 and 113, respectively.
Is supplied to.

Response waveforms of the filters are stored in the storage devices 110 and 111, and the coordinate accumulators 106 and 1 are stored.
The data supplied from 07 is the upper address of the storage device. The storage devices 112 and 113 include the storage device 11
0, compared with the response waveform stored in the storage device 111, the response waveform of ^{1/2 1/2} level is stored,
The data supplied from the coordinate accumulators 108 and 109 is the upper address of the storage device. Further, the elapsed time information of the even-odd symbol period is supplied as a lower address from the timing signal generation circuit 105 to each storage device as described below.

The timing signal generator 105 generates a timing signal for the entire modulation circuit based on a clock signal having a frequency higher than that of the baseband signal. CL1 is a clock signal having the same frequency as the baseband signal, and the symbol generation circuit 102 captures the baseband signal at the timing when CL1 is supplied.
CL2 is a clock signal having the same frequency as the symbol data, and the mapping circuit 103 fetches data from the symbol generator 2 or performs differential encoding at the timing when CL2 is supplied. CL3 is a clock signal having the same frequency as the 2-symbol data, and generates even-odd symbol timing. The timing signal generator 105 also generates elapsed time information during the even-odd symbol period, and the storage devices 110, 111, 112, 1
It is supplied to 13 as a lower address.

The storage devices 110, 111, 112, 113 supplied with the address information described above output the filter response waveform data corresponding to the address. The filter response waveform data output is subjected to predetermined addition and subtraction by a subtracter 114 and adders 115, 116, 117 to generate an I-phase signal I and a Q-phase signal Q. The generated I and Q phase signals are respectively fed to the digital / analog converter 1
Output terminal 12
It is output from 0 and 121.

[0008]

The storage devices 110 and 111 and the storage device 11 used in the above-mentioned prior art.
2 and 113 store the same filter data. Such a storage device is usually composed of a ROM,
An increase in ROM capacity causes an increase in circuits, which causes a problem in cost. In addition, it is disadvantageous when the circuit is formed into an LSI.

[0009]

[Means for Solving the Problems] In view of these problems,
According to the present invention, an input terminal to which a baseband signal is input, a symbol data generating unit that generates symbol data by serial-parallel converting the baseband signal input from the input terminal, and the symbol data generating unit are generated. Vector coordinate generation means for generating two-dimensional vector coordinates that are uniquely determined depending on the symbol data or the data obtained by differential encoding with the preceding symbol data at even and odd symbol timings, and the vector coordinate generation. Means for outputting a response waveform with the vector coordinate data at the even symbol timing generated by the means as a filter input, and a response using the vector coordinate data at the odd symbol timing generated by the vector coordinate generating means as the filter input For odd symbols that output waveforms Π / 4 shift, each of which includes digital filter means, arithmetic means for performing a predetermined arithmetic operation on the outputs of the two symbol digital filter means, and digital / analog conversion means for converting an output signal from the arithmetic means into an analog signal. In the baseband signal generator for a QPSK quadrature modulator, the two digital filters have two coordinate accumulating means for accumulating 2-bit vector coordinate data output from the vector coordinate generating means, and a frequency higher than that of the baseband signal. A time information output means for outputting midway elapsed time information over two even and odd symbols and a high-speed switching signal, and a previous period response waveform having the output of the coordinate storage means and the output of the time information output means as addresses. Faster than the stored storage device and the halfway elapsed time information output by the two coordinate storage means A switching means for switching and outputting address data supplied to the storage device according to the switching signal, and a separating means for separating the output of the storage device into the two response waveforms according to the switching signal. A baseband signal generator for π / 4 shift QPSK quadrature modulator.

[0010]

According to the present invention, the switching means constituting the digital filter switches the address data output from the two coordinate storage means to the storage device according to the switching signal supplied from the time information output means. That is, the switching means supplies the outputs of the two coordinate storage means to the storage device in a time division manner. The separation means inputs the data output from the storage device in a time division manner and separates the data into two systems according to the switching signal.

[0011]

1 is a block diagram showing an embodiment of the present invention, in which 1 is an input terminal to which a baseband signal is supplied, 2 is a symbol generator, and a serially input baseband signal is supplied to a clock T2 which will be described later. 2 at the timing when is supplied
Convert to bit parallel signal. Reference numeral 3 denotes a mapping circuit, which outputs either symbol data output from the symbol generator 2 or symbol data differentially encoded with the preceding symbol data by the differential encoding circuit 4 by a clock T3 described later. It is converted into two-dimensional coordinate data at the timing of supply.

A timing signal generation circuit 5 is driven based on a clock signal having a frequency higher than the bit rate of the baseband signal, and generates the next timing signals T1 to T7. T1 is an elapsed time information signal during the even-odd two-symbol period, T2 is a clock signal having the same frequency as the frequency of the input baseband signal, T3 is a clock signal having the same frequency as the frequency of one symbol, and T4 is the same as the two-symbol frequency. Clock signal with frequency, T5
Is a clock signal having a phase opposite to that of T4, T6 is a switching signal faster than the elapsed time information, and T7 is a separation signal having a clock speed twice that of the switching signal T6 and supplied to a separation circuit described later. .

Numerals 6 and 7 denote coordinate accumulators, which output two-dimensional coordinate data in the odd symbol timing of the mapping circuit 3 at a timing when a clock T4 having the same frequency as the two symbol periods is supplied. Serial to parallel conversion to. Reference numerals 8 and 9 denote coordinate accumulators, of the output of the mapping circuit 3, at the timing when the clock T5 having the same frequency as the two symbol period is supplied to the two-dimensional coordinate data at the even symbol vector timing.
Serial-parallel conversion is performed every two symbol periods. T4 and T5
Have the same frequency but opposite phases, so that the coordinate accumulators 6 and 7 and the coordinate accumulators 8 and 9 take in the two-dimensional coordinate data alternately.

Reference numeral 10 denotes a switching circuit, which sequentially coordinates the coordinate accumulator 6 in accordance with a switching signal T6 from the timing signal generating circuit 5.
The signal input from 7 is switched and output. Reference numeral 11 denotes a switching circuit, which sequentially outputs the signals input from the coordinate accumulators 8 and 9 in accordance with the switching signal T6 from the timing signal generating circuit 5.

Reference numeral 12 is a storage device for storing the filter response waveform, which receives the output from the switching circuit 10 and the elapsed time information T1 from the timing generation circuit 5 as an address and outputs the filter response waveform corresponding to the address information. To do. Reference ^numeral 13 is a memory device for storing 1/2 ^1/2 levels of the filter response waveform, which inputs the output from the switching circuit 11 and the elapsed time information T1 from the timing generating circuit as an address, and filters corresponding to the address information. Output the response waveform.

Reference numeral 14 denotes a separation circuit, which separates the time-division-multiplexed data output from the storage device 12 into two signals according to the switching signal T6 and the separation signal T7 from the timing generation circuit 5. Reference numeral 15 denotes a separation circuit, which separates the time-division-multiplexed data output from the storage device 13 into two signals according to the switching signal T6 and the separation signal T7 from the timing generation circuit 5.

Reference numeral 16 is a subtractor, which subtracts the two systems of data output from the separation circuit 15. Reference numeral 17 denotes an adder, which adds the two systems of data output from the separation circuit 15. 1
Reference numeral 8 denotes an adder, which adds the output of the subtractor 16 and the output of one system of the separation circuit 14, and 19 adds the output of the one system output from the adder 17 and the separation circuit 15.

Reference numeral 20 denotes a D / A converter, which converts the output of the adder 18 into digital / analog. Reference numeral 21 is a D / A converter, which converts the output from the adder 19 into digital / analog. 22 and 23 are output terminals, which are connected to the D / A converter 20 and the D / A converter 20.
The output from the A converter 21 is output.

Next, the operation will be described. Prior to that, the modulation procedure will be described. The input serial signal is converted into a symbol (Xk, Yk) by the serial-parallel converter. Then, it is further converted into quadrature signals (Ik, Qk) by the differential encoding circuit. This conversion is performed by the following formula.

[0020]

[Equation 1]

However, ΔΦ (Xk, Yk) is specified in the following table.

[0022]

[Table 1]

The Ik and Qk signals thus obtained are band-limited by a low-pass filter, and I-phase and Q-phase components supplied to the quadrature modulator are generated.

Here, focusing on the movement of the signal points of the orthogonal signals (Ik, Qk), points A to D on the orthogonal coordinate axes of FIG.
Alternatively, one of the signal points E to H is taken alternately. Then, as is clear from FIG. 3, signal points A to D
Can be represented by coordinates on a vector Iα on the I axis and a vector Qα on the Q axis, and the signal points E to H are coordinates on vectors Iβ and Qβ obtained by rotating the vector by π / 4. Can be expressed as For example, assuming that the supplied baseband signal is the information that should represent the symbol point F, 0 may be given as Iα coordinate, 0 as Qα coordinate, −1 as Iβ coordinate, and +1 as Qβ coordinate.

When the k-th symbol coordinate information using these four vectors is Iαk, Qαk, Iβk, Qβk, the k-th symbol orthogonal coordinate information Ik, Qk is expressed as follows.

[0026]

[Equation 2]

[0027]

(Equation 3)

Therefore, the I-phase signal I (t) and the Q-phase signal Q (t) supplied to the quadrature modulator are given by the following equations when the rectangular wave response function of the low pass filter is h (t). become.

[0029]

[Equation 4]

[0030]

(Equation 5)

The above equation shows that the band limiting operation for the quadrature signals Ik and Qk can be performed by the band limiting operation for each term of the expressions (2) and (3).

Among the points A to H in FIG. 3, the odd numbered symbol points are A to D and the even numbered symbol points are E to H.
Then

[0033]

(Equation 6)

[0034]

(Equation 7)

Therefore, I (t) and Q (t) are expressed by the following equations.

[0036]

(Equation 8)

[0037]

[Equation 9]

As is clear from the above equation, I (t), Q
To obtain (t), Iαk among the four vector coordinate signals Iαk, Qαk, Iβk, and Qβk shown in FIG.
For Qαk, only odd-symbol signals, Iβk, Qβk
Only the signal at the time of the even symbol should be used.

Based on the above-described modulation procedure, the circuit operation of FIG. 1 will be described below. The baseband signal serially input from the input terminal 1 is converted into 2-bit serial symbol data by the symbol generator 2. The symbol generator 2 is supplied with the clock signal T1 having the same frequency as the baseband signal from the timing generation circuit 5, and the symbol generator 2 captures the baseband signal and performs serial / serial operation at the timing when the clock signal T2 is supplied. Performing parallel conversion.

The generated symbol data is supplied to the mapping circuit 3. A clock T3 having the same frequency as the symbol data is supplied to the mapping circuit 3, and the symbol data is captured at the timing when the clock T3 is supplied. Then, after performing differential encoding as necessary, a predetermined mapping operation is performed to convert into two-dimensional coordinate data. The two-dimensional mapping data is supplied to the coordinate accumulators 6 to 9 and fetched in the coordinate accumulators 6 to 9 at the timing when the clock T4 or T5 supplied by the timing generation circuit 5 is supplied.

The coordinate accumulators 6 and 7 have a clock T.
4. The clock T5 is supplied to the coordinate accumulators 8 and 9. Therefore, the coordinate accumulators 6 and 7 take in the two-dimensional coordinate data at the odd symbol timing when T4 is supplied, and the coordinate accumulators 8 and 9 take the two-dimensional coordinate data at the even symbol timing when T5 is supplied. The coordinate accumulators 6 to 7 are composed of shift registers and accumulate data of several symbol periods.

The output of the coordinate accumulators 6 and 7 is the switching circuit 10.
The outputs of the coordinate accumulators 8 and 9 are supplied to the switching circuit 11. A switching signal T6 is supplied from the timing generation circuit 5 to the switching circuits 10 and 11. Switching signal T
6 is elapsed time information T output from the timing generation circuit 5.
A clock signal having a frequency twice as fast as 1.
The switching circuit 10 switches and outputs the data input from the coordinate accumulators 6 and 7 in accordance with this clock signal, and the storage device 1
It is supplied to 2 on a time-sharing basis. Similarly, coordinate accumulators 8 and 9
Is supplied to the switching circuit 11 and is supplied to the storage device 13 by the switching circuit 11 in a time division manner.

As described above, the storage devices 12 and 13 are supplied with the elapsed time information T1 of the two-symbol period from the timing generation circuit 5 in addition to the data from the switching circuits 10 and 11. The storage devices 12 and 13 output band limiting signals corresponding to the respective terms of the equations 8 and 9 using the coordinate accumulators 6 to 9 and the elapsed time information T1 from the timing generation circuit 5 as address information. However, as can be understood from the above description, the output from the storage devices 12 and 13 is the eighth.
Since each term in the equation and the ninth equation is a time-division multiplexed signal,
The outputs from the storage devices 12 and 13 are separated by the separation circuit 1 respectively.
4 and 15 and separates into signals corresponding to the respective terms of the eighth and ninth equations.

A switching signal T6 is supplied to the separation circuits 14 and 15,
Separation signal T7 having a frequency twice as fast as switching signal T6
, And the time-divided signals can be easily separated as described above by combining the two clock signals. Further, after the signals corresponding to the respective terms of the equations 8 and 9 are separated, the signals corresponding to the respective terms must be added to each other by the subtracter 16 and the adders 17 to 19. Therefore, the separation circuit 14,
It is necessary to match the timing of each signal separated by 15. The timing of each signal can be easily adjusted by combining the switching signal T6 and the separation signal T7 described above. In this embodiment, the separation circuits 14 and 15 are provided as a part of the function. And

The signals thus generated and output from the separation circuits 14 and 15 are added by the subtracter 16 and the adders 17 to 19 according to the eighth and ninth equations, and the I-phase signal I (t) is obtained. , Q-phase signal Q (t) is generated as a digital signal. This signal is analogized by the D / A converters 20 and 21, and the analogized I-phase signal and Q-phase signal are output from the output terminals 22 and 23.

[0046]

As is apparent from the above description, according to the present invention, the capacity of the memory device can be significantly reduced by adding a small number of circuits to the conventional modulation circuit, and the circuit configuration can be simplified. It can be measured. As a result, the cost can be reduced and the LSI can be easily implemented.

[Brief description of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a configuration diagram of a conventional π / 4 shift QPSK quadrature modulator.

FIG. 3 shows signal points and 4 in a π / 4 shift QPSK signal.
It is a figure which shows the relationship with a vector coordinate.

[Explanation of symbols]

 2 symbol generator 3 mapping circuit 4 differential encoding circuit 5 timing generation circuit 6 coordinate accumulator 7 coordinate accumulator 8 coordinate accumulator 9 coordinate accumulator 10 switching circuit 11 switching circuit 12 memory device 13 memory device 14 separation circuit 15 separation circuit

Claims (1)

[Claims] 1. An input terminal to which a baseband signal is input, symbol data generating means for generating symbol data by serial-parallel converting the baseband signal input from the input terminal, and the symbol data generating means. Vector coordinate generation means for generating two-dimensional vector coordinates that are uniquely determined depending on the generated symbol data or data obtained by differential encoding with the preceding symbol data at even and odd symbol timings, and the vector coordinates. Digital filter means for even symbols that outputs a response waveform with the vector coordinate data at the even symbol timing generated by the generating means as a filter input, and vector coordinate data at the odd symbol timing generated by the vector coordinate generating means as the filter input For odd symbols that output response waveforms Π / 4 shift, each of which includes digital filter means, arithmetic means for performing a predetermined arithmetic operation on the outputs of the two symbol digital filter means, and digital / analog conversion means for converting an output signal from the arithmetic means into an analog signal. In the baseband signal generator for a QPSK quadrature modulator, the two digital filters are driven by two coordinate accumulating means for accumulating vector coordinate data output by the vector coordinate generating means and at a frequency higher than that of the baseband signal. , A time information output means for outputting halfway elapsed time information over two even and odd symbols and a high-speed switching signal, and a storage device for storing the response waveform with the output of the coordinate accumulating means and the halfway elapsed time information as addresses. And the outputs of the two coordinate storage means, respectively, and the time information means outputs. Switching means for switching and outputting the address data to be supplied to the storage device according to the switching signal faster than the middle elapsed time information, and separation means for separating the output of the storage device into two response waveforms according to the switching signal. Π / 4 shift QPS, characterized by comprising
Baseband signal generator for K quadrature modulator.