JPH118857A - Digital color demodulator circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a circuit which is a digital color demodulator circuit that performs digital conversion of an analog carrier color signal and obtains a digital color-difference signal through digital processing, does not need an analog VCO for clock generation, a complicated arithmetic circuit of coordinate transformation, etc., and has excellent stability with high precision. SOLUTION: A phase compensating means 109 inputs outputs of two demodulating means 105 and 106, performs mean value processing of a color burst period and outputs phase deviation quantity. A phase generating means 110 configures a digital VCO in which phase progressing quantity per clock changes through an output of the means 109. A rounding means 111 performs round processing of phase information that is outputted from the means 110 and reduces the number of bits, and a sine wave generating means 112 and a cosine wave generating means 113 generate reference subcarrier (sine wave and cosine wave).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital color demodulation circuit applied to convert an analog carrier color signal into a digital signal and obtain a digital color difference signal by digital processing.

[0002]

2. Description of the Related Art Conventionally, a digital color demodulation circuit has been disclosed in
No. 42200 is known.

FIG. 4 is a block diagram showing a configuration of a conventional digital color demodulation circuit. Referring to FIG.
1 is supplied to multipliers 402 and 403, and this multiplier 40
The output of 2, 403 is a low-pass filter (LPF) 40
4 and 405, and demodulated outputs X and Y are obtained at respective outputs. The multipliers 402 and 403 are supplied with the demodulated chrominance subcarrier generated by the carrier signal source 406 and the phase shifter 407. The color subcarrier for demodulation is fixed at a predetermined phase, and in most cases, the demodulation detection axis has a phase shift from the normal detection axis. The demodulated outputs X and Y are supplied to a coordinate conversion operation circuit 408, which detects the amount of phase shift from a normal detection axis from the demodulation result during the burst period, performs coordinate conversion, and corrects the phase shift of the detection axis. An RY signal and a BY signal are output.

[0004]

However, such a digital color demodulation circuit requires a complicated arithmetic circuit for detecting a phase shift with respect to a normal detection axis from the demodulated output and performing coordinate conversion on the demodulated output. This leads to an increase in circuit scale.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a digital color demodulation circuit for demodulating a color difference signal on a regular detection axis without an arithmetic circuit for performing coordinate conversion.

[0006]

SUMMARY OF THE INVENTION In order to solve this problem, a digital color demodulation circuit according to the present invention has a clock generation circuit for generating a clock having a frequency which is an integral multiple of the data rate for outputting the first and second color difference signals. A / D conversion means for inputting a carrier color signal and performing A / D conversion for each clock;
First demodulation means for multiplying the output of the conversion means by a sine wave for each clock, removing high-frequency components and performing thinning processing to output a first color difference signal, and output and cosine of the A / D conversion means A second demodulation means for multiplying the wave for each clock and then removing high frequency components to perform a thinning process and output a second color difference signal; Phase compensating means for processing the average value and outputting the amount of phase shift; phase generating means for holding the addition result of the output of the phase compensating means and the output of the flip-flop in the flip-flop for each clock and outputting the output of the flip-flop A rounding means for rounding the output of the phase generating means and outputting the output; a sine wave generating means for inputting the output of the rounding means and outputting a sine wave for each clock; and a clock receiving the output of the rounding means as an input. Which is constituted by a cosine-wave generating means for outputting a cosine wave for each.

As a result, a digital color demodulation circuit for demodulating a color difference signal on a normal detection axis without a complicated arithmetic circuit such as coordinate conversion can be obtained.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention according to claim 1 of the present invention provides a clock generating means for generating a clock having a frequency which is an integral multiple of a data rate for outputting first and second color difference signals, and a carrier chrominance signal. And A / D conversion means for performing A / D conversion for each clock, and multiplying the output of the A / D conversion means and a sine wave for each clock, removing high-frequency components and performing thinning processing. A first demodulation unit for outputting a color difference signal, and a second unit for multiplying an output of the A / D conversion unit and a cosine wave for each clock, removing a high frequency component, performing a thinning process, and outputting a second color difference signal. 2 demodulation means, and first and second demodulation means.
And a phase compensating means for processing the average value of the color burst period by using the color difference signal as an input and outputting a phase shift amount, and holding a result of addition of an output of the phase compensating means and an output of the flip-flop in the flip-flop for each clock. Phase generating means for outputting the output of the loop, rounding means for rounding and outputting the output of the phase generating means, sine wave generating means for receiving the output of the rounding means as input and outputting a sine wave for each clock, and rounding means A digital color demodulation circuit characterized by comprising a cosine wave generation means for outputting a cosine wave for each clock with the output of the input as an input, and a color difference signal on a regular detection axis without a complicated arithmetic circuit such as coordinate transformation. It has the function of demodulating.

[0009] The invention according to claim 2 provides the NTS
C, first and second compensating means for inputting a PAL operation switching signal, wherein the phase compensating means receives the first and second color difference signals as input, processes an average value of a color burst period and outputs a phase shift amount. And the output of the first and second compensating means is N
It is characterized by switching and outputting with a TSC / PAL operation switching signal, and can cope with two systems of NTSC and PAL by almost sharing the components of the first embodiment.

Further, according to the present invention, there is provided an adding means for receiving an output of the rounding means as an input and adding a fixed value, and a second means for receiving an output of the adding means as an input and outputting a second sine wave for each clock. A sine wave generating unit, a second cosine wave generating unit that receives an output of the adding unit as an input, and outputs a second cosine wave for each clock, a third and fourth color difference signals, a second sine wave, and a second sine wave.
Balanced modulating means that receives the cosine wave of the input as an input and performs balanced modulation and outputs the output;
And a D / A converter for outputting a carrier color signal of a reference subcarrier (sine wave) that matches the input analog carrier color signal without a complicated arithmetic circuit such as coordinate conversion. And a cosine wave). Further, the operation clock of the circuit is irrelevant to the color subcarrier of the input analog carrier chrominance signal, the frequency is not an integral multiple, there is no need to lock the phase, and an analog circuit such as an analog VCO for clock generation becomes unnecessary. A highly accurate and stable circuit can be realized.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. (Embodiment 1) FIG. 1 is a block diagram showing a configuration of a digital color demodulation circuit showing an embodiment of the present invention. In FIG. 1, reference numeral 101 denotes a clock 102 having a frequency of 27 MHz.
, An input terminal 103 for an analog carrier chrominance signal, and an A / D converter 104 for sampling the analog carrier chrominance signal input from the input terminal 103 with the clock 102 and converting the analog carrier chrominance signal into 8-bit digital data. ,
105 is the output of the A / D converter 104 and the sine wave generating means 1
The output of the A / D converter 104 is multiplied by the cosine of the output of the A / D converter 104. The output of the wave generator 113 is multiplied for each clock 102, and then a high frequency component is removed to perform a decimation process to output a 6.75 MHz rate RY signal. An output terminal for signal output, 108 is an output terminal for the RY signal output of the demodulation means 106, and 109 is two demodulation means 105, 1
A phase compensating means for processing the average value of the color burst period and outputting a phase shift amount by inputting the output of the clock signal 06 as an input; a phase generating means for adding the output of the phase compensating means 109 for each clock 102 to output phase information; 111 is a rounding means for rounding the output of the phase generating means 110 and outputting 10-bit phase information. 112 and 113 are sine wave generating means and cosine wave generating means, each constituted by a ROM. The output is used as an address input to output 8-bit sine and cosine waves to the first and second demodulation means 105 and 106 for each clock 102 as described above.

The operation of the digital color demodulation circuit configured as described above will be described below.

First, the phase generating means 110 constitutes a digital VCO in which the amount of phase lead per clock changes according to the output of the phase compensating means 109. Phase generation means 1
The output of 10 is once rounded by rounding means 111 to reduce the number of bits, and sine wave generating means 112 and cosine wave generating means 113 generate reference subcarriers (sine wave and cosine wave) that match the normal detection axis. I do. As a result, the input terminal 1
03 is demodulated on the normal detection axis, and the RY signal and the B-
Obtain the Y signal. The sine wave generating means 112 and the cosine wave generating means 113 do not need to have one cycle of data in a table, and have a small capacity table (257 words) for one quarter cycle and a simple arithmetic circuit. Generate a reference subcarrier (sine wave and cosine wave) having

As described above, according to the present embodiment, a digital color demodulation circuit for demodulating a color difference signal on a normal detection axis without a complicated arithmetic circuit such as coordinate conversion can be obtained. The operation clock 102 of the digital color demodulation circuit is connected to the input terminal 10.
Irrespective of the chrominance subcarrier of the analog carrier chrominance signal input from 3, the frequency is not an integral multiple and does not need to be phase locked. Therefore, an analog circuit such as an analog VCO for clock generation is not required, and a highly accurate and stable circuit can be realized, which is suitable for LSI.

(Embodiment 2) Next, a second embodiment of the present invention will be described. FIG. 2 is a block diagram showing the configuration of the digital color demodulation circuit according to the second embodiment. In FIG. 2, parts corresponding to those in FIG. 1 are given the same numbers.

In FIG. 2, reference numeral 201 denotes NTSC, PAL
The operation switching signal 202 includes two demodulation units 105, 1
A phase compensating means for NTSC which outputs the output of the color demodulation means 106 as an input and outputs the amount of phase shift by averaging the color burst period. PAL phase compensation means for outputting a phase shift amount by using
Switching means for switching and outputting the output 202 of the phase compensating means for C and the output of the phase compensating means 203 for PAL with the NTSC / PAL operation switching signal 201. The other parts are the same as in the first embodiment.

The operation of the digital color demodulation circuit configured as described above will be described below.

In the second embodiment, in addition to the first embodiment, an NTSC / PAL operation switching signal 201 is input, and two phase compensation means 20 for NTSC and PAL are input.
2, 203. When the NTSC is operating, the NTS
Output of the phase compensating means 202 for C, PA during PAL operation
The output of the phase compensating means 203 for L is switched to the switching means 204
Is switched and output. The phase generating means 110 constitutes a digital VCO in which the amount of phase lead per clock changes according to the output of the switching means 204. The output of the phase generating means 110 is once rounded by the rounding means 111 to reduce the number of bits, and the sine wave generating means 112 and the cosine wave generating means 113 output the reference subcarrier (sine wave and cosine wave) which matches the normal detection axis. ). As a result, the analog carrier chrominance signal input from the input terminal 103 is demodulated on the normal detection axis, and the RY signal and the BY signal are obtained at the output terminals 107 and 108.

As described above, according to the present embodiment, almost all circuits are shared to constitute a digital color demodulation circuit of two systems, NTSC and PAL.

(Embodiment 3) Next, a third embodiment of the present invention will be described. FIG. 3 is a block diagram showing the configuration of the digital color demodulation circuit according to the third embodiment. 3, parts corresponding to those in FIG. 1 are denoted by the same reference numerals.

In FIG. 3, reference numeral 301 denotes an input terminal of a BY signal, reference numeral 302 denotes an input terminal of an RY signal, reference numeral 303 denotes an input which receives an output of the rounding means 111 and adds a fixed value 300, and reference numerals 304 and 305 denote input means. Each is composed of ROM,
The output of the adding means 303 is used as an address input and the clock 10
A second sine wave generating means and a second cosine wave generating means for outputting a second sine wave and a second cosine wave of 8 bits every 2 bits;
Reference numeral 306 denotes BY input from the input terminals 301 and 302.
And RY signal, the output of the sine wave generating means 304 and the output of the cosine wave generating means 305 are input, balanced modulation is performed, and the output of the balanced modulation means 306 is input. A D / A converter 308 for A-converting and outputting a second analog carrier chrominance signal is an output terminal for the second analog carrier chrominance signal. The other parts are the same as in the first embodiment.

The operation of the digital color demodulation circuit configured as described above will be described below.

In the third embodiment, in addition to the first embodiment, the output of the rounding means 111 (detection axis information of the input analog carrier chrominance signal) has a constant value (delay of the A / D converter 104 or the like). A reference subcarrier (sine wave and cosine wave) is generated by the color subcarrier to which
To generate an analog carrier color signal.

As described above, according to the present embodiment, the analog carrier balanced and modulated with the reference subcarriers (sine wave and cosine wave) that match the input analog carrier color signal without a complicated arithmetic circuit such as coordinate conversion. A color signal can be obtained.
Further, the operation clock 102 of the circuit is irrelevant to the color subcarrier of the analog carrier chrominance signal input from the input terminal 103, and the frequency is not an integral multiple and does not need to be phase locked.
For this reason, an analog circuit such as an analog VCO for clock generation is not required, and a highly accurate and stable circuit can be realized, which is suitable for LSI.

Although the present invention has been described with reference to the embodiment, the configuration of the present invention can be realized by various methods other than the above.

[0026]

As described above, according to the present invention, a digital color demodulation circuit for demodulating a color difference signal from an analog carrier color signal on a normal detection axis can be obtained without a complicated arithmetic circuit such as coordinate conversion. Further, the operation clock of the digital color demodulation circuit is irrelevant to the chrominance subcarrier of the input analog carrier chrominance signal. For this reason, an analog circuit such as an analog VCO for clock generation is not required, and a highly accurate and stable circuit can be realized, which is suitable for LSI.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a digital color demodulation circuit according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing the configuration of the second embodiment;

FIG. 3 is a block diagram showing a configuration of the third embodiment.

FIG. 4 is a block diagram showing a configuration of a conventional digital color demodulation circuit.

[Explanation of symbols]

 Reference Signs List 101 clock generator 103 analog carrier chrominance signal input terminal 104 A / D converter 105 demodulation means 106 demodulation means 107 output terminal 108 output terminal 109 phase compensation means 110 phase generation means 111 rounding means 112 sine wave generation means 113 cosine wave generation Means 201 NTSC / PAL operation switching signal 202 Phase compensation means for NTSC 203 Phase compensation means for PAL 204 Switching means 301 Input terminal of BY signal 302 Input terminal of R-Y signal 303 Addition means 304 Second sine wave Generation means 305 Second cosine wave generation means 306 Balanced modulation means 307 D / A converter 308 Output terminal

Claims (3)

[Claims] 1. A clock generation means for generating a clock having a frequency which is an integral multiple of a data rate for outputting first and second color difference signals, a carrier chrominance signal input, and a carrier chrominance signal input for each clock. A / D conversion means for performing A / D conversion;
A first demodulation means for multiplying an output of the A / D conversion means and a sine wave for each clock, removing high frequency components and performing a thinning-out process to output the first color difference signal; A second demodulation means for multiplying an output of the D conversion means and a cosine wave for each clock, removing a high frequency component and performing a thinning-out process to output the second color difference signal; and the first and second demodulation means. Phase compensation means for receiving the color difference signal as an input, processing the average value of the color burst period and outputting a phase shift amount,
Phase generating means for holding the addition result of the output of the phase compensating means and the output of the flip-flop in the flip-flop for each clock, outputting the output of the flip-flop, rounding the output of the phase generating means and outputting Rounding means, sine wave generating means for receiving the output of the rounding means as input and outputting the sine wave for each clock, and cosine wave generating for receiving the output of the rounding means as input and outputting the cosine wave for each clock And a digital color demodulation circuit. 2. An input device for inputting an NTSC / PAL operation switching signal, wherein the phase compensator receives the first and second color difference signals as input signals, averages a color burst period and outputs a phase shift amount. 2. The digital color demodulation circuit according to claim 1, further comprising a second compensator, wherein the outputs of the first and second compensators are switched by the NTSC / PAL operation switching signal and output. 3. An adding means for receiving an output of the rounding means and adding a fixed value thereto, and a second sine wave generating means for receiving an output of the adding means and outputting a second sine wave for each clock. A second cosine wave generating means for receiving an output of the adding means and outputting a second cosine wave for each clock;
, A balanced modulation means for inputting the color difference signal, the second sine wave and the second cosine wave, and performing balanced modulation to output the same; 2. A digital color demodulation circuit according to claim 1, further comprising: a D / A converter for outputting two carrier color signals.