JPH10191372A - Subcarrier generating circuit for color video signal synthesizer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To attain the circuit integration by outputting a 1st digital subcarrier from a 1st memory, and outputting a 2nd digital subcarrier having a specific phase difference from the 1st digital subcarrier from a 2nd memory so as to configure all circuits as a digital circuit. SOLUTION: Memories 12a, 12b store amplitude data at each point of time within 1/4 period of a received sine wave subcarrier 107. An address circuit 11 provides the output of an address signal 110a used to read amplitude data at each point of time for each 1/4 period of the sine wave subcarrier 107 from the memory 12a and the output of an address signal 110b that has a phase difference of 90 deg. from the address signal 110a and is used to read the amplitude data from the memory 12b. A data conversion circuit 13a provides the output of a sine wave subcarrier 108a to which data denoting positive/negative cycle of the sine wave subcarrier 107 are added. A data conversion circuit 13b provides the output of a digital subcarrier 108b with a phase difference of 90 deg. from the digital subcarrier 108a.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sub-carrier generation circuit for a color video signal synthesizing apparatus, and more particularly, to a color video signal synthesizing apparatus for converting a sub-carrier of digital data supplied to a modulator for quadrature quadrature modulating a color difference signal. Related to a circuit to generate.

[0002]

2. Description of the Related Art FIG. 4 shows the configuration of a conventional color video signal synthesizing apparatus. In FIG. 4, digital component signals of three primary colors, that is, R.R. G. FIG. B, the three types of color signals 101 to 103 are converted into a Y signal 104 of a luminance signal and two types of color difference signals I.B. Q signal 105,1
06. The I.D. Q signal 10
5 and 106 are subjected to band limitation by low-pass filters (LPF) 3a and 3b, respectively, and added to the modulators 4a and 4b.
On the other hand, the digital sub-carriers 108a and 108b having a phase difference of 90 ° generated by the sub-carrier generation circuit 8 are coupled to the modulators 4a and 4b.
b. The Q signals 105 and 106 are quadrature two-phase modulated here, and the two signals are combined by the adder 6. A synchronizing signal is added to the Y signal 104 of the luminance signal by a synchronizing signal adding circuit (SYNC) 5 and the I.V.
The Q signal and the adder 7 are combined to form a color video signal 109, which is transmitted to the transmission path.

A sub-carrier generation circuit 8 receives an analog sine-wave sub-carrier 107 generated by an oscillator (not shown), and outputs a sub-carrier having a 90 ° phase difference from the input sub-carrier in the NTSC system by a phase shifter 81. Generate and output The subcarriers having 0 ° and 90 ° phases are supplied to A / D converters 82a and 82b.
Output the digital sub-carriers 108a and 108b, respectively.

[0004]

As described above, the conventional subcarrier generation circuit has a portion in which two digital subcarriers having a phase difference of 90 ° are generated in the analog domain.
There is a problem that integration of the whole is difficult. Further, when the whole portion is performed in the digital domain, it is necessary to convert the amplitude value of the input sine wave subcarrier in the entire cycle into data and store it in the memory.

[0005]

The sub-carrier generation circuit of the color video signal synthesizing apparatus according to the present invention comprises 1 / one of the sine wave sub-carrier.
A first and a second memory storing amplitude value data at each time point within four periods, and inputting the sine wave subcarrier, and an amplitude value of an absolute value at each time point for each quarter period of the sine wave subcarrier An address generation circuit for outputting a first address signal for reading data from the first memory and a second address signal having a phase difference of 90 ° from the first address signal; and the first address signal A first data conversion circuit that outputs a first digital subcarrier obtained by adding data indicating a positive / negative cycle identified from the sine wave subcarrier to the amplitude value data read from the first memory. The first digital subcarrier and the first digital subcarrier to which the data indicating the positive / negative cycle identified from the sine wave subcarrier by adding the amplitude value data read from the second memory by the address signal of 2 are added. And a second data converting circuit for outputting a second digital sub-carriers having a phase difference.

Further, the address generation circuit inputs a phase adjustment signal from the outside, adds the adjusted address value to the address values of the first and second address signals, respectively, and adjusts the read time of the first and second memories. May be output by varying the adjustment address value to output the first and second address signals.

[0007]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of a color video signal synthesizing apparatus using a subcarrier generation circuit according to the present invention.

A digital component signal of three primary colors,
That is, the three types of color signals 101 to 103 of R, G and B are converted into a Y signal 104 of a luminance signal and two types of color difference signals I. It is converted into Q signals 105 and 106. The I.D. The Q signals 105 and 106 are band-limited by low-pass filters (LPFs) 3a and 3b and applied to modulators 4a and 4b. On the other hand, the subcarrier generation circuit 1
2 digital subcarriers 1 with a phase difference of 90 ° generated by
08a and 108b are supplied to the modulators 4a and 4b. The Q signals 105 and 106 are quadrature two-phase modulated here, and the two signals are combined by the adder 6. A synchronizing signal is added to the Y signal 104 of the luminance signal by a synchronizing signal adding circuit (SYNC) 5 and the I.V. Q signal and adder 7
Are combined into a color video signal 109 and transmitted to the transmission path.

The sub-carrier generation circuit 1 includes a sine-wave sub-carrier 10 generated and input by an oscillator (not shown) in the apparatus.
2 that stores the amplitude value data at each time point within 1/4 cycle of 7
An address signal 110a for inputting the two memories 12a and 12b and the sine wave sub-carrier 107 and reading out the amplitude value data at each time point of each 正弦 cycle of the sine wave sub-carrier 107 from the memory 12a, and the address signal 110a. 90
An address generation circuit 11 having a phase difference of ゜ and outputting an address signal 110b for reading amplitude value data from the memory 12b;
a to the amplitude value data read from the
1. A data conversion circuit 13a for outputting a digital subcarrier 108a to which data indicating the positive / negative cycle of the sine wave subcarrier 107 generated in step 1 is added, and an amplitude generation data read from the memory 12b by an address signal 110b. Digital subcarrier 1 to which data indicating the positive / negative cycle of the sine wave subcarrier 107 generated in step 11 is added
08a and a digital subcarrier 108 having a phase difference of 90 °
and a data conversion circuit 13b for outputting b.
Note that the address generation circuit 11 receives a phase adjustment signal 11 from the outside.
1 is input and added to each of the address signals 110a and 110b, and a phase adjustment circuit is provided for adjusting the phase of each of the digital subcarriers 108a and 108b by changing the read time of each of the memories 12a and 12b.

Next, the operation of the subcarrier generation circuit 1 will be described. The sub-carrier generation circuit 1 constitutes a phase shift circuit capable of adjusting the phase of the digital sub-carrier 108 output by the phase adjustment signal 111. The memories 12a and 12b previously input and store digital data indicating the 1/4 cycle of the sine wave subcarrier 107, that is, the amplitude value of each point of 0 to 90 °.

The address generation circuit 11 adds an arbitrary adjustment address value of the phase adjustment signal 111 input from the outside to the address values of the phases 0 ° and 90 ° that have been input in advance, and adds this address value to the sine wave subcarrier. Read address signals 110a and 110b alternately every 1/4 period of 107
Output as

The address signals 110a and 110b are は of the sine wave subcarrier 107 from the memories 12a and 12b.
In the case where the phase is adjusted by 30 ° by the phase adjustment signal 111 for each cycle, for example, the address signal 110a
Are the address values for sequentially reading the amplitude value data of each point in the order of 30 °, 120 °, 210 °, and 300 °.
Stores only the amplitude value data of the absolute value of 0 to 90 °, the actual address signal 110a is 30 °, 60 °
Address signals for reading the absolute value data of each point of {, 30}, 60 ° are sequentially output. Also, the address signal 110
Since b has a phase difference of 90 ° with the address signal 110a, address signals of 60 °, 30 °, 60 °, and 30 ° are sequentially output at the same time.

The amplitude data of the absolute values read from the memories 12a and 12b by the address signals 110a and 110b are input to the data converters 13a and 13b, respectively. The data converter 13 adds data indicating a positive / negative cycle to the read amplitude value data based on the positive / negative determination signal 118 input from the address generation circuit 11 and adds the data as digital subcarriers 108a and 108b to the modulators 4a and 4b, respectively. Output.

Next, the address generation circuit 11 will be described in detail. FIG. 2 is a circuit diagram of the address generation circuit, and FIG. 3 is a timing chart for explaining the operation of the address generation circuit of FIG. In FIG. 2, the adjusted address value of the phase adjustment signal 111 is directly applied to the adders 14 and 15 to which the address values of 0 ° and 90 ° have been input in advance, and the adder 15 is connected via the inverter 20 to the adder 15. They are input, added, and stored. The phase adjustment signal adjusts the phase of the output subcarrier with respect to the input subcarrier and is 0 to 90.
Arbitrary phase adjustment is possible in the range of ゜.

On the other hand, the input sine wave sub-carrier 107 is converted by the pulse conversion circuit 17 into a pulse waveform output fsc and a pulse waveform output 4 × fsc which is quadrupled. fs
c, 4xfsc are the D-FF circuit 18 and the NOR circuit 1
9 to output a selection signal 112 and a positive / negative determination signal 118. The selection signal 112 is the selector 16
, Where the address values of the adders 14 and 15 are set to 9
The read address signals 110a,
110b is output.

FIG. 3 is a timing chart showing the waveform of each signal. The address signals 110a and 110b are shown by solid lines when the phase adjustment is not performed, and by dotted lines when the phase adjustment of 30 ° is performed.

[0018]

As described above, the sub-carrier generation circuit of the color video signal synthesizing apparatus according to the present invention has an effect that it can be integrated since all parts are constituted by digital circuits. In addition, since the amplitude value data at each point of the full cycle of the sine wave subcarrier is recorded as data representing 1/4 cycle, there is an effect that the circuit scale can be reduced when integrated.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a color video signal synthesizing apparatus using a subcarrier generation circuit of the present invention.

FIG. 2 is a circuit diagram of an address generation circuit in FIG. 1;

FIG. 3 is a timing chart for explaining the operation of FIG. 2;

FIG. 4 is a block diagram showing a configuration of a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Sub-carrier generation circuit 2 Matrix circuit 3a, 3b Low-pass filter (LPF) 4a, 4b Modulator 5 Period signal addition circuit (SYNC) 6,7 Adder 11 Address generation circuit 12a, 12b Memory 13a, 13b Data converter

Claims (4)

[Claims] A first and a second memory storing amplitude value data at each time point within a quarter cycle of a sine wave subcarrier;
The sine wave sub-carrier is input and 1 /
A first address signal for reading out the amplitude value data of the absolute value at each point in time of every four cycles from the first memory and a second address signal having a phase difference of 90 ° with the first address signal are output. A first digital subcarrier obtained by adding data indicating a positive / negative cycle identified from the sine wave subcarrier to amplitude value data read from the first memory by the first address signal. A first data conversion circuit for outputting, and the first data conversion circuit in which data indicating a positive / negative cycle identified from the sine wave sub-carrier is added to amplitude value data read from the second memory by the second address signal. Digital subcarrier and 90
And a second data conversion circuit for outputting a second digital subcarrier having a phase difference of ゜. A subcarrier generation circuit of a color video signal synthesizing apparatus. 2. The address generation circuit according to claim 1, further comprising a phase adjustment signal input from outside, adding the adjusted address value to an address value of the first and second address signals, and adding the adjusted address value to the first and second memories. 2. The sub-carrier generation circuit according to claim 1, wherein the first and second address signals whose read time is varied by the adjustment address value are output. 3. The address generation circuit inputs in advance address values for reading the amplitude values of the phases 0 ° and 90 ° of the sine wave subcarrier, and adjusts the address value of the phase adjustment signal externally input to each of them. Two adders for respectively holding the added address value, a selection signal generated by pulsating the sine wave subcarrier and being generated every quarter period and cycling to the sine wave subcarrier, and a positive / negative cycle. And a signal conversion circuit for generating a positive / negative determination signal indicating that the address values held by the two adders are read alternately with a phase difference of 90 ° by the selection signal.
3. A selector for outputting the first and second address signals having a phase difference of ゜.
A sub-carrier generation circuit of the color video signal synthesizing apparatus according to any one of the preceding claims. 4. The data conversion circuit according to claim 3, wherein the data conversion circuit adds data indicating a positive / negative cycle to the amplitude value data read from the first and second memories according to the positive / negative determination signal. Sub-carrier generation circuit of color video signal synthesis device.