JPS63181027U - - Google Patents
Info
- Publication number
- JPS63181027U JPS63181027U JP1987072476U JP7247687U JPS63181027U JP S63181027 U JPS63181027 U JP S63181027U JP 1987072476 U JP1987072476 U JP 1987072476U JP 7247687 U JP7247687 U JP 7247687U JP S63181027 U JPS63181027 U JP S63181027U
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- transistor
- series
- capacitor
- connection point
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Electronic Switches (AREA)
- Monitoring And Testing Of Transmission In General (AREA)
Description
第１図は本考案のリセツト回路を示す回路図、
第２図は動作説明用の波形図、第３図はリセツト
回路の使用例を示す説明図である。
第１図でＲ１〜Ｒ４は抵抗、Ｃ１はコンデンサ
、Ｔｒ１，Ｔｒ２はトランジスタである。
FIG. 1 is a circuit diagram showing the reset circuit of the present invention.
FIG. 2 is a waveform diagram for explaining the operation, and FIG. 3 is an explanatory diagram showing an example of how the reset circuit is used. In FIG. 1, R 1 to R 4 are resistors, C 1 is a capacitor, and Tr 1 and Tr 2 are transistors.
Claims (1)
Ｃ１を直列にして電源間に接続し、 第１のトランジスタＴｒ１と第２の抵抗Ｒ２を
直列にして前記第１の抵抗Ｒ１とコンデンサＣ１
に並列に接続し、かつ該トランジスタのベースを
第１の抵抗Ｒ１とコンデンサＣ１の直列接続点Ａ
へ接続し、 第４の抵抗Ｒ４と第２のトランジスタＴｒ２を
直列にして電源間に接続し、その直列接続点Ｂを
出力端とし、該トランジスタのベースを第１のト
ランジスタＴｒ１と第２の抵抗Ｒ２の直列接続点
へ接続したことを特徴とする電源投入オートリセ
ツト回路。[Claims for Utility Model Registration] A third resistor R3 , a first resistor R1 , and a capacitor C1 are connected in series between power supplies, and a first transistor Tr1 and a second resistor R2 are connected in series. and the first resistor R 1 and the capacitor C 1
, and the base of the transistor is connected to the series connection point A of the first resistor R1 and the capacitor C1 .
The fourth resistor R4 and the second transistor Tr2 are connected in series between the power supplies, the series connection point B is used as the output terminal, and the base of the transistor is connected to the first transistor Tr1 and the second transistor Tr2 . A power-on auto-reset circuit characterized in that a resistor R2 is connected to a series connection point of the resistor R2 .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987072476U JPS63181027U (en) | 1987-05-15 | 1987-05-15 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987072476U JPS63181027U (en) | 1987-05-15 | 1987-05-15 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63181027U true JPS63181027U (en) | 1988-11-22 |
Family
ID=30915955
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987072476U Pending JPS63181027U (en) | 1987-05-15 | 1987-05-15 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63181027U (en) |
-
1987
- 1987-05-15 JP JP1987072476U patent/JPS63181027U/ja active Pending
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