JPS59180529U - Reset circuit for flip-flop - Google Patents

Reset circuit for flip-flop

Info

Publication number
JPS59180529U
JPS59180529U JP7526783U JP7526783U JPS59180529U JP S59180529 U JPS59180529 U JP S59180529U JP 7526783 U JP7526783 U JP 7526783U JP 7526783 U JP7526783 U JP 7526783U JP S59180529 U JPS59180529 U JP S59180529U
Authority
JP
Japan
Prior art keywords
flip
flop
reset circuit
output
power
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7526783U
Other languages
Japanese (ja)
Other versions
JPH024519Y2 (en
Inventor
英雄 大前
Original Assignee
ロ−ム株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ロ−ム株式会社 filed Critical ロ−ム株式会社
Priority to JP7526783U priority Critical patent/JPS59180529U/en
Publication of JPS59180529U publication Critical patent/JPS59180529U/en
Application granted granted Critical
Publication of JPH024519Y2 publication Critical patent/JPH024519Y2/ja
Granted legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図〜第３図は各従来例の回路図、第４図は本考案の
一実施例の回路図、第５図は第４図の回路の動作説明に
供する電圧波形図である。 ＴＲ１，ＴＲ２・・・出力トランジスタ、ＴＲ３，ＴＲ
４・・・第１、第２トランジスタ、Ｃ′・・・結合コン
デンサ、Ｒ３・・・電流制限抵抗。1 to 3 are circuit diagrams of each conventional example, FIG. 4 is a circuit diagram of an embodiment of the present invention, and FIG. 5 is a voltage waveform diagram for explaining the operation of the circuit of FIG. 4. TR1, TR2...output transistor, TR3, TR
4...First and second transistors, C'...Coupling capacitor, R3...Current limiting resistor.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] フリップフロップを構成する出力トランジスタの出力レ
ベルを電源投入時にリセットするフリップフロップ用リ
セット回路において、結合コンデンサと電流制限抵抗と
の直列回路を有し、この結合コンデンサには電源投入時
に電源電圧に対応した電圧を加え、直列回路の電源投入
時の過渡的な出力電圧に応答して出力トランジスタの出
力レベルを決定するフリップフロップ用リセット回路。A flip-flop reset circuit that resets the output level of the output transistor that constitutes a flip-flop when the power is turned on has a series circuit of a coupling capacitor and a current limiting resistor, and this coupling capacitor has a resistance that corresponds to the power supply voltage when the power is turned on. A flip-flop reset circuit that applies voltage and determines the output level of the output transistor in response to the transient output voltage when the series circuit is powered on.
JP7526783U 1983-05-18 1983-05-18 Reset circuit for flip-flop Granted JPS59180529U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7526783U JPS59180529U (en) 1983-05-18 1983-05-18 Reset circuit for flip-flop

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7526783U JPS59180529U (en) 1983-05-18 1983-05-18 Reset circuit for flip-flop

Publications (2)

Publication Number Publication Date
JPS59180529U true JPS59180529U (en) 1984-12-03
JPH024519Y2 JPH024519Y2 (en) 1990-02-02

Family

ID=30205340

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7526783U Granted JPS59180529U (en) 1983-05-18 1983-05-18 Reset circuit for flip-flop

Country Status (1)

Country Link
JP (1) JPS59180529U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5076749U (en) * 1973-11-15 1975-07-03

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5076749U (en) * 1973-11-15 1975-07-03

Also Published As

Publication number Publication date
JPH024519Y2 (en) 1990-02-02

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