JPS63180929U - - Google Patents

Info

Publication number
JPS63180929U
JPS63180929U JP1987071910U JP7191087U JPS63180929U JP S63180929 U JPS63180929 U JP S63180929U JP 1987071910 U JP1987071910 U JP 1987071910U JP 7191087 U JP7191087 U JP 7191087U JP S63180929 U JPS63180929 U JP S63180929U
Authority
JP
Japan
Prior art keywords
island
semiconductor chip
lead terminal
electrode
metal wire
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1987071910U
Other languages
English (en)
Japanese (ja)
Other versions
JPH0547464Y2 (enExample
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1987071910U priority Critical patent/JPH0547464Y2/ja
Publication of JPS63180929U publication Critical patent/JPS63180929U/ja
Application granted granted Critical
Publication of JPH0547464Y2 publication Critical patent/JPH0547464Y2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Wire Bonding (AREA)
JP1987071910U 1987-05-14 1987-05-14 Expired - Lifetime JPH0547464Y2 (enExample)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1987071910U JPH0547464Y2 (enExample) 1987-05-14 1987-05-14

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1987071910U JPH0547464Y2 (enExample) 1987-05-14 1987-05-14

Publications (2)

Publication Number Publication Date
JPS63180929U true JPS63180929U (enExample) 1988-11-22
JPH0547464Y2 JPH0547464Y2 (enExample) 1993-12-14

Family

ID=30914894

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987071910U Expired - Lifetime JPH0547464Y2 (enExample) 1987-05-14 1987-05-14

Country Status (1)

Country Link
JP (1) JPH0547464Y2 (enExample)

Also Published As

Publication number Publication date
JPH0547464Y2 (enExample) 1993-12-14

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