JPS63179534A - Method for screening resin sealed semiconductor integrated circuit device - Google Patents
Method for screening resin sealed semiconductor integrated circuit deviceInfo
- Publication number
- JPS63179534A JPS63179534A JP62012822A JP1282287A JPS63179534A JP S63179534 A JPS63179534 A JP S63179534A JP 62012822 A JP62012822 A JP 62012822A JP 1282287 A JP1282287 A JP 1282287A JP S63179534 A JPS63179534 A JP S63179534A
- Authority
- JP
- Japan
- Prior art keywords
- pressure
- chip
- integrated circuit
- semiconductor integrated
- filler
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229920005989 resin Polymers 0.000 title claims abstract description 16
- 239000011347 resin Substances 0.000 title claims abstract description 16
- 238000000034 method Methods 0.000 title claims description 13
- 239000004065 semiconductor Substances 0.000 title claims description 11
- 238000012216 screening Methods 0.000 title claims description 9
- 230000002950 deficient Effects 0.000 claims abstract description 14
- 230000015654 memory Effects 0.000 claims abstract description 12
- 238000007789 sealing Methods 0.000 claims description 11
- 238000003825 pressing Methods 0.000 claims description 3
- 238000011990 functional testing Methods 0.000 claims 1
- 239000000945 filler Substances 0.000 abstract description 13
- 230000007547 defect Effects 0.000 abstract description 11
- 238000002161 passivation Methods 0.000 abstract description 9
- 238000004806 packaging method and process Methods 0.000 abstract description 8
- 230000000694 effects Effects 0.000 abstract description 4
- 239000007788 liquid Substances 0.000 abstract description 2
- 230000006378 damage Effects 0.000 description 5
- 238000012360 testing method Methods 0.000 description 5
- 238000000465 moulding Methods 0.000 description 3
- 230000014759 maintenance of location Effects 0.000 description 2
- 229920003002 synthetic resin Polymers 0.000 description 2
- 239000000057 synthetic resin Substances 0.000 description 2
- 241000269821 Scombridae Species 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 235000020640 mackerel Nutrition 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000004793 poor memory Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
Landscapes
- Testing Of Individual Semiconductor Devices (AREA)
- Tests Of Electronic Circuits (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、集積回路チップを合成樹脂成形により封止
した、半導体集積回路パッケージ装置の不良品をスクリ
ーニングする方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for screening defective products of a semiconductor integrated circuit package device in which an integrated circuit chip is sealed by molding synthetic resin.
従来の紫外線消去形ｌＰＲＯＭの封止け、紫外線透過窓
付きパッケージに収納するようにしている。このパッケ
ージは、紫外線透過窓付きのため、通常セラミックパッ
ケージになっており、チップと透過室との間は空所にし
ている。The conventional UV-erasable IPROM is sealed and housed in a package with a UV-transparent window. This package is usually a ceramic package because it has an ultraviolet transmitting window, and there is a space between the chip and the transmitting chamber.
また、メモリ情報書込みは１回のみで、書込まれた情報
を消去することのない用途では、紫外線透過室を必要と
しないので、第６図に示される安価な合成樹脂封止パッ
ケージが用いられるようになった。Furthermore, in applications where memory information is written only once and the written information is not erased, an inexpensive synthetic resin sealed package shown in Figure 6 is used since an ultraviolet transmission chamber is not required. It became so.
一方、紫外線消失形ｌＰＲＯＭのメモリ保持特性、耐湿
性などの長期信頼性は、チップ（１） 表面上のパッシ
ベーション膜（２）特性とそのパッシベーション膜（２
）上に接触する封止樹脂（３）の材質と、充填剤として
封止樹脂（３）に混入されている直径数十μｍ程度のフ
ィラー（４）と呼ばれる粒子がチップ（１）上のパッシ
ベーション膜（２）を圧迫する度合−などにより影響さ
れる。紫外線透過窓付きパッケージでは実使用上問題に
ならなかった紫外線消去形ｌＰＲＯＭのメモリ特性・書
込み特性であるが、樹脂封止ｌ パッケージ装置では、
チップ（１）表面に封止樹脂（３）やフィラー（４）が
直接接触して圧迫し、次のような問題が生じていた。On the other hand, long-term reliability such as memory retention characteristics and moisture resistance of UV-disappearing lPROM depends on the characteristics of the passivation film (2) on the surface of the chip (1) and the passivation film (2) on the surface of the chip (1).
) The material of the sealing resin (3) in contact with the top of the chip (3) and the particles called filler (4) with a diameter of several tens of micrometers mixed into the sealing resin (3) as a filler form the passivation on the chip (1). It is influenced by the degree to which the membrane (2) is pressed. The memory and write characteristics of UV-erasable lPROMs did not pose a problem in practical use in packages with ultraviolet-transmitting windows, but in resin-sealed l-package equipment,
The sealing resin (3) and filler (4) directly contact and press the surface of the chip (1), causing the following problems.
すなわち、チップ（１）表面は異物の付着やパッシベー
ション膜（２）の欠陥等で凹凸がある＠封止樹脂（３）
は加熱成形後、冷却されながら収縮し、フィラー（４）
と共にチップ（１）表面を圧迫するようになる。In other words, the surface of the chip (1) is uneven due to adhesion of foreign matter or defects in the passivation film (2) @sealing resin (3)
After heating and molding, the filler (4) shrinks while being cooled.
At the same time, the surface of the chip (1) is pressed.
特にこのフィラー（４）が及ばずチップ（１）表面への
圧力が局所的に高められるような箇所（５）では、その
圧力により、メモリセルや周辺回路の押しつぶし、パッ
シベーション膜（２）の欠陥をおこし、そこから浸入し
た封止樹脂（３）による汚染などにより不良品の発生と
なっていた。Particularly in areas (5) where the filler (4) does not reach and the pressure on the chip (1) surface is locally increased, the pressure may crush the memory cells and peripheral circuits and cause defects in the passivation film (2). This caused defective products due to contamination by the sealing resin (3) that entered from there.
従来の樹脂封止紫外線消失形ＩＰＲＱＭパッケージ装置
は、以上のような原因によりメモリ保持特性不良や直流
動作不良といった不良品を生じていたが、それらの不良
品は樹脂封圧成形直後の動作試験により取り除かれる明
らかに不良をおこしているものと、その後のバーンイン
や高温保存を施しても発見しにくい軽微な不良のものと
が存在し、特に後者のような不良品のスクリーニングが
行なわれにくいという問題点があった。Conventional resin-sealed ultraviolet evaporative IPRQM package equipment has produced defective products such as poor memory retention characteristics and poor DC operation due to the reasons mentioned above, but these defective products were confirmed by operation tests immediately after resin-sealed pressure molding. The problem is that there are clearly defective products that can be removed, and minor defective products that are difficult to detect even after subsequent burn-in or high-temperature storage, and it is particularly difficult to screen for the latter type of defective products. There was a point.
この発明は、上記のような問題点を解決するためのもの
で、封止樹脂及びフィラーによる圧迫が原因であるメモ
リセル破壊、回路破壊、パッシベーション膜の欠陥等の
不良品と、それらの中でも軽微な不良品を早期にスクリ
ーニングする方法を得ることを目的とする。This invention is intended to solve the above-mentioned problems, and is aimed at preventing defective products such as memory cell destruction, circuit destruction, and passivation film defects caused by pressure caused by sealing resin and filler, as well as minor defects among them. The objective is to obtain a method for early screening for defective products.
この発明では、樹脂封止された半導体集積回路パッケー
ジ装置に対し、そのパッケージ装置外部から適度の圧力
を加えて、封止樹脂及びフィラーがチップｉ面に及ぼす
圧力を機械的に増加させる０〔作用〕
この発明における半導体集積回路パッケージ装置に加え
る外部からの圧力は、封止樹脂及びフィラーを媒介とし
て内部の半導体集積回路チップ表面まで伝達され、チッ
プ表面に存在する微小な傷や欠陥が原因となって今後引
き起こす不良に対し、その進行・発生を速める効果があ
る。In the present invention, a moderate pressure is applied from outside the package device to a semiconductor integrated circuit package device sealed with resin to mechanically increase the pressure exerted by the sealing resin and filler on the i-side of the chip. ] The external pressure applied to the semiconductor integrated circuit package device in this invention is transmitted to the internal semiconductor integrated circuit chip surface through the sealing resin and filler, and is caused by minute scratches and defects on the chip surface. This has the effect of accelerating the progress and occurrence of defects that may occur in the future.
以下、この発明の一実施例を図について説明する０第１
図において、加圧工程（８１は封止樹脂を用いてパッケ
ージ装置に加工する工程（７）と直流動作試験及び機能
試験を含む試験工程（９）との間に実施される。実際の
加圧工程は、第２図のようにパッケージ装置ｒ６）を台
ａＯ上に固定してブツシャ０で圧力を加えたり、第３図
のように気体や液体の高圧雰囲気◎により圧力を加える
といった方法、第４図のように上下のローラＤの間を通
して圧力を加える方法等が考えられる。いずれの場合も
、内部歪みによってチップ本体が破損することがないよ
うに適切な圧力を加える。Hereinafter, one embodiment of the present invention will be explained with reference to the drawings.
In the figure, the pressurization process (81 is carried out between the process (7) of processing into a package device using sealing resin and the test process (9) including a DC operation test and a function test.Actual pressurization The process involves fixing the packaging device r6) on a stand aO and applying pressure with a pusher 0 as shown in Figure 2, or applying pressure with a high-pressure atmosphere of gas or liquid ◎ as shown in Figure 3. A possible method is to apply pressure between the upper and lower rollers D as shown in Figure 4. In either case, apply appropriate pressure to prevent damage to the chip body due to internal distortion.
上記実施例に示されたような方法でパッケージ装置（６
）に加えられた圧力は、封止樹脂（３）及びフィラー（
４）がメモリセルや回路、あるいはパッシベーション膜
（２）に対して及ばず影響を増幅・加速する役割を果た
す。この結果、従来の不良品スフ１３−ニング方法では
発見するために長時間を必要としていたが、新し−スク
リーニング方法を用いることにより、不良品のスクリー
ニングを短時間に有効に行なうことができる。The packaging device (6
) The pressure applied to the sealing resin (3) and the filler (
4) does not affect the memory cells, circuits, or passivation film (2), and plays the role of amplifying and accelerating the influence. As a result, the conventional screening method required a long time to detect defective products, but by using the new screening method, defective products can be screened effectively in a short period of time.
上記実施例では、紫外線消去形ｌＰＲＯＭの場合を示し
なが、紫外線消去形ｌＰＲＯＭに限らず、他の記憶形集
積回路装置や記憶形に限らない他の半導体集積回路装置
の樹脂封止形パッケージ装置の不良品スクリーニングに
、この発明が適用できるものである◎
〔発明の効果〕
以上のように、この発明によれはメモリセル破壊や回路
破壊、パッシベーション膜欠陥などが原因となって引き
起こされる半導体集積回路装置の動作特性不良が有効に
スクリーニングでき、試験時間の短縮などの効果が得ら
れる。In the above embodiments, the case of an ultraviolet erasable IPROM is shown, but it is not limited to an ultraviolet erasable IPROM, and is applicable to other memory type integrated circuit devices and resin-sealed package devices for other semiconductor integrated circuit devices not limited to memory types. This invention can be applied to the screening of defective products. ◎ [Effects of the Invention] As described above, this invention can prevent semiconductor integration caused by memory cell destruction, circuit destruction, passivation film defects, etc. Defects in operating characteristics of circuit devices can be effectively screened, and effects such as shortening of testing time can be obtained.
第１図はこの発明の一実施例としてのフローチャート、
第２〜４図はこの発明の具体的な適用例を示した図、第
５図は従来のパッケージ装置を示す断面図である。
図において、（１）はチップ、（２）はパツシベーシミ
ン膜、１３）は封止樹脂、（４）はフィラー、（５１け
フィラーが及ぼすチップ表面への圧力が局所的に高めら
れる箇所、（６）はパッケージ装置、ａａＦｉパッケー
ジ装置を固定する台、（１１３はブツシャ、鰺はパッケ
ージ装置に圧力を加える高圧雰囲気、ａ３はローラであ
る。
なお、各図中同一符号は同一、まなは相当部分を示す。FIG. 1 is a flowchart as an embodiment of this invention.
2 to 4 are diagrams showing specific application examples of the present invention, and FIG. 5 is a sectional view showing a conventional packaging device. In the figure, (1) is the chip, (2) is the patchy base film, (13) is the sealing resin, (4) is the filler, (51) is the location where the pressure on the chip surface exerted by the filler is locally increased, (6) ) is a packaging device, a stand for fixing the aaFi packaging device, (113 is a pusher, mackerel is a high-pressure atmosphere that applies pressure to the packaging device, and a3 is a roller. In each figure, the same reference numerals are the same, and the corresponding parts are show.
Claims (3)
備えた半導体集積回路パッケージ装置に、そのパッケー
ジ上から機械的に圧力を加えた後、機能試験を行ない不
良品を取り除くことを特徴とする樹脂封止半導体集積回
路装置のスクリーニング方法。(1) A semiconductor integrated circuit package device equipped with a molded resin sealing body that seals an integrated circuit chip is characterized by mechanically applying pressure from above the package and then performing a functional test to remove defective products. A screening method for a resin-sealed semiconductor integrated circuit device.
素子（ＥＰＲＯＭ）チップからなることを特徴とする、
特許請求の範囲第１項記載の樹脂封止半導体集積回路装
置のスクリーニング方法。(2) the integrated circuit chip is characterized in that it consists of an ultraviolet erasable read-only memory (EPROM) chip;
A method for screening a resin-sealed semiconductor integrated circuit device according to claim 1.
憶素子（Ｅ＾２ＰＲＯＭ）チップからなることを特徴と
する、特許請求の範囲第１項記載の樹脂封止半導体集積
回路装置のスクリーニング方法。(3) The method for screening a resin-sealed semiconductor integrated circuit device according to claim 1, wherein the integrated circuit chip is an electrically erasable read-only memory element (E^2PROM) chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62012822A JPS63179534A (en) | 1987-01-21 | 1987-01-21 | Method for screening resin sealed semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62012822A JPS63179534A (en) | 1987-01-21 | 1987-01-21 | Method for screening resin sealed semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63179534A true JPS63179534A (en) | 1988-07-23 |
Family
ID=11816077
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62012822A Pending JPS63179534A (en) | 1987-01-21 | 1987-01-21 | Method for screening resin sealed semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63179534A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008004669A (en) * | 2006-06-21 | 2008-01-10 | Nec Electronics Corp | Manufacturing method of semiconductor device |
-
1987
- 1987-01-21 JP JP62012822A patent/JPS63179534A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008004669A (en) * | 2006-06-21 | 2008-01-10 | Nec Electronics Corp | Manufacturing method of semiconductor device |
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