JPS63178926U - - Google Patents
Info
- Publication number
- JPS63178926U JPS63178926U JP7012687U JP7012687U JPS63178926U JP S63178926 U JPS63178926 U JP S63178926U JP 7012687 U JP7012687 U JP 7012687U JP 7012687 U JP7012687 U JP 7012687U JP S63178926 U JPS63178926 U JP S63178926U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- state
- change
- circuit
- modulation circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000010355 oscillation Effects 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 6
- 230000001360 synchronised effect Effects 0.000 description 1
Landscapes
- Electronic Switches (AREA)
Description
第１図はこの考案の一実施例を示すブロツク図
、第２図は第１図に示す回路の各部波形図、第３
図は従来の一例を示すブロツク図、第４図は第３
図に示す回路の各部波形図である。
１ａ，１ｂ……発振回路、３ａ，３ｂ，４ａ，
４ｂ，２０ａ，２０ｂ……変調回路、６ａ，６ｂ
……同期回路、７ａ，７ｂ……駆動回路、８ａ，
８ｂ……発光素子、１０ａ，１０ｂ……リセツト
回路。
Figure 1 is a block diagram showing one embodiment of this invention, Figure 2 is a waveform diagram of each part of the circuit shown in Figure 1, and Figure 3 is a diagram showing waveforms of various parts of the circuit shown in Figure 1.
The figure is a block diagram showing a conventional example, and Fig. 4 is a block diagram showing a conventional example.
FIG. 3 is a waveform diagram of each part of the circuit shown in the figure. 1a, 1b...Oscillation circuit, 3a, 3b, 4a,
4b, 20a, 20b...Modulation circuit, 6a, 6b
... Synchronous circuit, 7a, 7b ... Drive circuit, 8a,
8b...Light emitting element, 10a, 10b...Reset circuit.
Claims (1)
第１の信号を分周して第２の信号とし、第１の信
号を第２の信号によつて変調することによる多重
変調を行ない、この系を２系統並列にする多重変
調回路において、第２の信号が変化したとき回路
動作を短時間リセツトする同期信号を発生する同
期回路を備え、同期信号は両系統へ共通信号とし
て供給することを特徴とする多重変調回路。 (2) 第２信号の変化は、第２信号が存在してい
る状態から存在しなくなつた状態であることを特
徴とする実用新案登録請求の範囲第１項記載の多
重変調回路。 (3) 第２信号の変化は、第２信号が存在しない
状態から存在する状態となつた状態であることを
特徴とする実用新案登録請求の範囲第１項記載の
多重変調回路。[Claims for Utility Model Registration] (1) The oscillation circuit output is divided into a first signal,
In a multiple modulation circuit that divides the frequency of a first signal to obtain a second signal, performs multiple modulation by modulating the first signal with the second signal, and connects two systems in parallel, 1. A multiplex modulation circuit comprising: a synchronization circuit that generates a synchronization signal for resetting circuit operation for a short time when a signal of two systems changes, and the synchronization signal is supplied to both systems as a common signal. (2) The multiplex modulation circuit according to claim 1, wherein the change in the second signal is from a state in which the second signal exists to a state in which it ceases to exist. (3) The multiplex modulation circuit according to claim 1, wherein the change in the second signal is a change from a state where the second signal does not exist to a state where the second signal exists.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7012687U JPH0516738Y2 (en) | 1987-05-13 | 1987-05-13 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7012687U JPH0516738Y2 (en) | 1987-05-13 | 1987-05-13 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63178926U true JPS63178926U (en) | 1988-11-18 |
| JPH0516738Y2 JPH0516738Y2 (en) | 1993-05-06 |
Family
ID=30911476
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7012687U Expired - Lifetime JPH0516738Y2 (en) | 1987-05-13 | 1987-05-13 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0516738Y2 (en) |
-
1987
- 1987-05-13 JP JP7012687U patent/JPH0516738Y2/ja not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0516738Y2 (en) | 1993-05-06 |
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