JPS63177456A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS63177456A JPS63177456A JP756487A JP756487A JPS63177456A JP S63177456 A JPS63177456 A JP S63177456A JP 756487 A JP756487 A JP 756487A JP 756487 A JP756487 A JP 756487A JP S63177456 A JPS63177456 A JP S63177456A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- type
- grooves
- buried layer
- conductivity type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 239000012535 impurity Substances 0.000 abstract description 4
- 230000010354 integration Effects 0.000 abstract description 4
- 230000000694 effects Effects 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特に抵抗を有する半導体装
置の構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to the structure of a semiconductor device having a resistor.
従来、抵抗を有する半導体装置は、第2図に示すように
、P型半導体基板1上に形成されたn型エピタキシャル
層3の絶縁分離膜10により分離された抵抗領域に、抵
抗層12及び電極7からなる抵抗を形成するのが一般的
であった。尚、第2図において11は反転防止層である
。Conventionally, a semiconductor device having a resistance has a resistance layer 12 and an electrode in a resistance region separated by an insulating separation film 10 of an n-type epitaxial layer 3 formed on a P-type semiconductor substrate 1, as shown in FIG. It was common to form a resistor consisting of 7. In FIG. 2, numeral 11 represents an anti-inversion layer.
上述した抵抗を有する従来の半導体装置では、抵抗形成
のために半導体基板表面を水平方向に用いるため、抵抗
領域、あるいは抵抗分離のための領域に大きな面積を必
要としていた。このため半導体装置の小型化、高集積化
の障害となる欠点があった。In the conventional semiconductor device having the above-mentioned resistor, the surface of the semiconductor substrate is used horizontally to form the resistor, and therefore a large area is required for the resistor region or the region for resistor isolation. For this reason, there has been a drawback that it becomes an obstacle to miniaturization and high integration of semiconductor devices.
本発明の目的は、上記欠点を除去し、抵抗の占める面積
を小さくし集積度の向上した半導体装置を提供すること
にある。SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above drawbacks, reduce the area occupied by the resistor, and provide a semiconductor device with an improved degree of integration.
本発明の半導体装置は、−導電型半導体基板上に形成さ
れた高濃度の逆導電型埋込層と、この埋込層上に形成さ
れた逆導電型エピタキシャル層と、前記エピタキシャル
層表面より前記埋込層に達して形成された一対の溝と、
溝の側面に形成された絶縁膜と、前記溝の内部に前記絶
縁膜を介して充填された逆導電型多結晶シリコン層とを
含んで構成される。The semiconductor device of the present invention includes a highly concentrated buried layer of opposite conductivity type formed on a semiconductor substrate of − conductivity type, an epitaxial layer of opposite conductivity type formed on the buried layer, and a pair of grooves formed reaching the buried layer;
The semiconductor device includes an insulating film formed on the side surface of a groove, and a reverse conductivity type polycrystalline silicon layer filled inside the groove with the insulating film interposed therebetween.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第1図は本発明の一実施例の断面図である。FIG. 1 is a sectional view of an embodiment of the present invention.
第1図において、P型半導体基板1上には層抵抗15Ω
/口のn+型埋込層2が選択的に形成され、これを覆う
ように全面に厚さ5μmのn型エピタキシャル層3が形
成されている。そして、このn型エピタキシャル層3の
表面からn+型埋込層2に達する、深さが5μmで幅が
2μm程度の2つの溝4A、4Bが形成されている。そ
してこれら2つの溝4A、4Bの側面にのみ厚さ0.2
μmの熱酸化による酸化膜5が形成されており、溝の底
面には酸化膜は形成されていない。そして、この2つの
溝4A、4Bの内部には比抵抗2にΩμmの不純物を添
加したn型多結晶シリコン6が充填され、この不純物を
添加したn型多結晶シリコン6は溝の底部でn+型埋込
層2と電気的に接続されている。尚、7A、7Bはこの
n型多結晶シリコン6に電気的に接続された電極である
。In FIG. 1, there is a layer resistance of 15Ω on the P-type semiconductor substrate 1.
An n + -type buried layer 2 with a / opening is selectively formed, and an n-type epitaxial layer 3 with a thickness of 5 μm is formed on the entire surface so as to cover this. Two grooves 4A and 4B are formed from the surface of the n-type epitaxial layer 3 to the n+-type buried layer 2, each having a depth of about 5 μm and a width of about 2 μm. And the thickness is 0.2 only on the sides of these two grooves 4A and 4B.
An oxide film 5 is formed by thermal oxidation with a thickness of μm, and no oxide film is formed on the bottom surface of the trench. The insides of these two grooves 4A and 4B are filled with n-type polycrystalline silicon 6 doped with an impurity of resistivity 2 and Ωμm, and this impurity-doped n-type polycrystalline silicon 6 is n It is electrically connected to the mold embedding layer 2. Note that 7A and 7B are electrodes electrically connected to this n-type polycrystalline silicon 6.
このように構成された本実施例においては、電極7A、
7B間のn型多結晶シリコン6とn+型埋込層2を通し
て抵抗が形成される。In this embodiment configured in this way, the electrodes 7A,
A resistor is formed through the n-type polycrystalline silicon 6 and the n+ type buried layer 2 between 7B.
例えば、溝4Aと溝4Bの間隔を10μmとし、n+型
埋込層を5μmX10μmで形成し、溝の開ロバターン
を2μm X 2μmとした場合、1つの溝による抵抗
値は2にΩμm X 5μm/(2μmX2μm)=2
.5 kΩとなり、2つの溝で5にΩとなる。一方、n
+型埋込層による抵抗値は16Ω/ロ×10μrn15
μm=32Ωであり、埋込層分の抵抗値は溝の抵抗に比
べ無視でき、溝の大きさを変えることによって所望の抵
抗値を有する抵抗を得ることができる。For example, if the distance between the grooves 4A and 4B is 10 μm, the n+ type buried layer is 5 μm x 10 μm, and the open pattern of the groove is 2 μm x 2 μm, the resistance value of one groove is 2Ωμm x 5 μm/( 2μm×2μm)=2
.. It becomes 5 kΩ, and the two grooves make it 5 Ω. On the other hand, n
The resistance value due to the + type buried layer is 16Ω/lo x 10μrn15
μm=32Ω, and the resistance value of the buried layer can be ignored compared to the resistance of the groove, and a resistor having a desired resistance value can be obtained by changing the size of the groove.
以上説明したように本発明は、溝中に不純物を含む多結
晶シリコンからなる抵抗を形成することにより、小面積
の抵抗を形成できる効果があり、従って半導体装置の集
積度は向上したものとなる。As explained above, the present invention has the effect of forming a resistor with a small area by forming a resistor made of polycrystalline silicon containing impurities in the groove, and therefore the degree of integration of a semiconductor device is improved. .
第1図は本発明の一実施例の断面図、第2図は従来の半
導体装置の一例の断面図である。
1・・・P型半導体基板、2・・・n+型埋込層、3・
・・n型エピタキシャル層、4A、4B・・・溝、5・
・・酸化膜、6・・・n型多結晶シリ゛コン、7A、7
B・・・電極、10・・・絶縁分離膜、11・・−反転
防止層、12・・・低抗層。FIG. 1 is a sectional view of an embodiment of the present invention, and FIG. 2 is a sectional view of an example of a conventional semiconductor device. DESCRIPTION OF SYMBOLS 1...P-type semiconductor substrate, 2...n+ type buried layer, 3...
...N-type epitaxial layer, 4A, 4B...groove, 5.
...Oxide film, 6...N-type polycrystalline silicon, 7A, 7
B...electrode, 10...insulating separation film, 11...-inversion prevention layer, 12...low resistance layer.
Claims (1)
込層と、該埋込層上に形成された逆導電型エピタキシャ
ル層と、前記エピタキシャル層表面より前記埋込層に達
して形成された一対の溝と、該溝の側面に形成された絶
縁膜と、前記溝の内部に前記絶縁膜を介して充填された
逆導電型多結晶シリコン層とを含むことを特徴とする半
導体装置。A highly concentrated buried layer of opposite conductivity type formed on a semiconductor substrate of one conductivity type, an epitaxial layer of opposite conductivity type formed on the buried layer, and a layer formed by reaching the buried layer from the surface of the epitaxial layer. A semiconductor device comprising: a pair of grooves formed on the substrate; an insulating film formed on the side surfaces of the groove; and an opposite conductivity type polycrystalline silicon layer filled inside the groove with the insulating film interposed therebetween. .
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP756487A JPS63177456A (en) | 1987-01-16 | 1987-01-16 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP756487A JPS63177456A (en) | 1987-01-16 | 1987-01-16 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63177456A true JPS63177456A (en) | 1988-07-21 |
Family
ID=11669297
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP756487A Pending JPS63177456A (en) | 1987-01-16 | 1987-01-16 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63177456A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04112565A (en) * | 1990-08-31 | 1992-04-14 | Nec Corp | Semiconductor resistance element and manufacture thereof |
CN112490241A (en) * | 2019-09-12 | 2021-03-12 | 株式会社东芝 | Semiconductor device with a plurality of semiconductor chips |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60140854A (en) * | 1983-12-28 | 1985-07-25 | Hitachi Ltd | High-resistant element |
-
1987
- 1987-01-16 JP JP756487A patent/JPS63177456A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60140854A (en) * | 1983-12-28 | 1985-07-25 | Hitachi Ltd | High-resistant element |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04112565A (en) * | 1990-08-31 | 1992-04-14 | Nec Corp | Semiconductor resistance element and manufacture thereof |
CN112490241A (en) * | 2019-09-12 | 2021-03-12 | 株式会社东芝 | Semiconductor device with a plurality of semiconductor chips |
JP2021044434A (en) * | 2019-09-12 | 2021-03-18 | 株式会社東芝 | Semiconductor device |
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