JPS63174460U - - Google Patents
Info
- Publication number
- JPS63174460U JPS63174460U JP1986197677U JP19767786U JPS63174460U JP S63174460 U JPS63174460 U JP S63174460U JP 1986197677 U JP1986197677 U JP 1986197677U JP 19767786 U JP19767786 U JP 19767786U JP S63174460 U JPS63174460 U JP S63174460U
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- package
- heat dissipation
- covering material
- circuit chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986197677U JPS63174460U (enExample) | 1986-12-23 | 1986-12-23 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986197677U JPS63174460U (enExample) | 1986-12-23 | 1986-12-23 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63174460U true JPS63174460U (enExample) | 1988-11-11 |
Family
ID=31157649
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1986197677U Pending JPS63174460U (enExample) | 1986-12-23 | 1986-12-23 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63174460U (enExample) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04315465A (ja) * | 1991-04-15 | 1992-11-06 | Mitsubishi Electric Corp | 表面実装型半導体装置 |
-
1986
- 1986-12-23 JP JP1986197677U patent/JPS63174460U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04315465A (ja) * | 1991-04-15 | 1992-11-06 | Mitsubishi Electric Corp | 表面実装型半導体装置 |