JPS6317338B2 - - Google Patents

Info

Publication number
JPS6317338B2
JPS6317338B2 JP57084673A JP8467382A JPS6317338B2 JP S6317338 B2 JPS6317338 B2 JP S6317338B2 JP 57084673 A JP57084673 A JP 57084673A JP 8467382 A JP8467382 A JP 8467382A JP S6317338 B2 JPS6317338 B2 JP S6317338B2
Authority
JP
Japan
Prior art keywords
adhesive
integrated circuit
membrane
width
protective film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP57084673A
Other languages
English (en)
Japanese (ja)
Other versions
JPS57201033A (en
Inventor
Edowaado Hogu Kaaru
Kuo Kuwangu Rin Guregorii
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
YUNISHISU CORP
Original Assignee
YUNISHISU CORP
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by YUNISHISU CORP filed Critical YUNISHISU CORP
Publication of JPS57201033A publication Critical patent/JPS57201033A/ja
Publication of JPS6317338B2 publication Critical patent/JPS6317338B2/ja
Granted legal-status Critical Current

Links

Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B37/00—Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding
    • B32B37/12—Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding characterised by using adhesives
    • C—CHEMISTRY; METALLURGY
    • C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09J—ADHESIVES; NON-MECHANICAL ASPECTS OF ADHESIVE PROCESSES IN GENERAL; ADHESIVE PROCESSES NOT PROVIDED FOR ELSEWHERE; USE OF MATERIALS AS ADHESIVES
    • C09J5/00—Adhesive processes in general; Adhesive processes not provided for elsewhere, e.g. relating to primers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3164—Partial encapsulation or coating the coating being a foil
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H01L23/556—Protection against radiation, e.g. light or electromagnetic waves against alpha rays
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B2379/00—Other polymers having nitrogen, with or without oxygen or carbon only, in the main chain
    • B32B2379/08—Polyimides
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B2457/00—Electrical equipment
    • B32B2457/08—PCBs, i.e. printed circuit boards
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24777—Edge feature

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Chemical & Material Sciences (AREA)
  • Health & Medical Sciences (AREA)
  • Organic Chemistry (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Laminated Bodies (AREA)
  • Formation Of Insulating Films (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
JP57084673A 1981-06-01 1982-05-18 Method of adhering protective film to integrated circuit Granted JPS57201033A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/268,813 US4388132A (en) 1981-06-01 1981-06-01 Method of attaching a protective film to an integrated circuit

Publications (2)

Publication Number Publication Date
JPS57201033A JPS57201033A (en) 1982-12-09
JPS6317338B2 true JPS6317338B2 (enExample) 1988-04-13

Family

ID=23024594

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57084673A Granted JPS57201033A (en) 1981-06-01 1982-05-18 Method of adhering protective film to integrated circuit

Country Status (2)

Country Link
US (1) US4388132A (enExample)
JP (1) JPS57201033A (enExample)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2100933B (en) * 1981-06-25 1985-04-17 Standard Telephones Cables Ltd Permanently connecting a set of conductive tracks on a substrate with a cooperating set on a printed circuit.
JPS58135A (ja) * 1981-06-25 1983-01-05 Fujitsu Ltd 半導体装置の製造方法
US4517041A (en) * 1982-09-30 1985-05-14 Magnetic Peripherals Inc. Method for attaching a workpiece to a workpiece carrier
KR920001026B1 (ko) 1984-02-09 1992-02-01 페어챠일드 카메라 앤드 인스트루먼트 코포레이션 알파입자 보호필름을 갖는 반도체 구조체 및 그 제조방법
DE3442131A1 (de) * 1984-11-17 1986-05-22 Messerschmitt-Bölkow-Blohm GmbH, 8012 Ottobrunn Verfahren zum einkapseln von mikroelektronischen halbleiter- und schichtschaltungen
US4798643A (en) * 1985-04-08 1989-01-17 Raytheon Company Self-aligning bonding technique
US4892606A (en) * 1986-08-28 1990-01-09 Canon Kabushiki Kaisha Optical recording medium having space therein and method of manufacturing the same
US4933042A (en) * 1986-09-26 1990-06-12 General Electric Company Method for packaging integrated circuit chips employing a polymer film overlay layer
US5094709A (en) * 1986-09-26 1992-03-10 General Electric Company Apparatus for packaging integrated circuit chips employing a polymer film overlay layer
KR960011853B1 (ko) * 1986-09-26 1996-09-03 제네럴 일렉트릭 컴패니 중합체막 오버레이층을 이용한 집적회로칩 패키징 방법 및 장치
DE3725269A1 (de) * 1987-07-30 1989-02-09 Messerschmitt Boelkow Blohm Verfahren zum einkapseln von mikroelektronischen halbleiter- und schichtschaltungen
US4829432A (en) * 1987-12-28 1989-05-09 Eastman Kodak Company Apparatus for shielding an electrical circuit from electromagnetic interference
JPH0615457Y2 (ja) * 1988-07-15 1994-04-20 矢崎総業株式会社 電気接続箱
JPH0286166U (enExample) * 1988-12-23 1990-07-09
US5144407A (en) * 1989-07-03 1992-09-01 General Electric Company Semiconductor chip protection layer and protected chip
US5548091A (en) * 1993-10-26 1996-08-20 Tessera, Inc. Semiconductor chip connection components with adhesives and methods for bonding to the chip
TW486238U (en) * 1996-08-18 2002-05-01 Helmut Kahl Shielding cap
US6403882B1 (en) 1997-06-30 2002-06-11 International Business Machines Corporation Protective cover plate for flip chip assembly backside
US6248614B1 (en) 1999-03-19 2001-06-19 International Business Machines Corporation Flip-chip package with optimized encapsulant adhesion and method
US6306684B1 (en) * 2000-03-16 2001-10-23 Microchip Technology Incorporated Stress reducing lead-frame for plastic encapsulation
US7547579B1 (en) * 2000-04-06 2009-06-16 Micron Technology, Inc. Underfill process
KR100629764B1 (ko) * 2002-10-25 2006-09-28 마쯔시다덴기산교 가부시키가이샤 반도체 디바이스 및 반도체 디바이스를 조립하기 위한수지 바인더
TWI285424B (en) * 2005-12-22 2007-08-11 Princo Corp Substrate including a multi-layer interconnection structure, methods of manufacturing and recycling the same, method of packaging electronic devices by using the same, and method of manufacturing an interconnection device
US8051557B2 (en) * 2006-03-31 2011-11-08 Princo Corp. Substrate with multi-layer interconnection structure and method of manufacturing the same

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3193424A (en) * 1961-10-31 1965-07-06 Olin Mathieson Process for adhesive bonding
US3852690A (en) * 1973-01-02 1974-12-03 Gen Electric Microwave transmission line to ground plane transition
US3963551A (en) * 1974-03-05 1976-06-15 Stromberg-Carlson Corporation Method for bonding semiconductor chips
FR2447066A1 (fr) * 1979-01-17 1980-08-14 Three Bond Co Ltd Procede de fabrication d'un dispositif de marquage, notamment pour robinets ou interrupteurs
JPS55138241A (en) * 1979-04-11 1980-10-28 Yamagata Nippon Denki Kk Sealing structure for semiconductor device

Also Published As

Publication number Publication date
US4388132A (en) 1983-06-14
JPS57201033A (en) 1982-12-09

Similar Documents

Publication Publication Date Title
JPS6317338B2 (enExample)
US5637536A (en) Method for interconnecting semiconductor chips in three dimensions, and component resulting therefrom
US6710437B2 (en) Semiconductor device having a chip-size package
US7883993B2 (en) Semiconductor device with semiconductor chip and rewiring layer and method for producing the same
US6107682A (en) Compliant wirebond packages having wire loop
JPH0318040A (ja) ハイブリッド半導体ストラクチャの製造法
JPH0682765B2 (ja) 液晶表示素子
JPS62173740A (ja) 半導体装置及びその製造方法
CN114284234B (zh) 一种封装结构和用于封装结构的制作方法
US20080131998A1 (en) Method of fabricating a film-on-wire bond semiconductor device
US7859108B2 (en) Flip chip package and method for manufacturing the same
US20060152615A1 (en) Image sensor chip having plate, wafer assembly and manufacturing method for the same
US4843035A (en) Method for connecting elements of a circuit device
JPH0319703B2 (enExample)
US20070045835A1 (en) Chip package structure
JPS59205747A (ja) 半導体装置の製造方法
WO2008070511A1 (en) Film-on-wire bond semiconductor device
US20120208325A1 (en) Semiconductor package and method for manufacturing the same
JPH02101753A (ja) 半導体チップの取付構造
JP3431316B2 (ja) 半導体装置の製造方法及び半導体チツプの実装方法
JPS586951B2 (ja) 電子回路装置
JPS6244851B2 (enExample)
JPS6247139A (ja) 転写バンプ基板の形成方法
JPS6214100B2 (enExample)
JP2841822B2 (ja) 混成集積回路の製造方法