JPS6317218B2 - - Google Patents

Info

Publication number
JPS6317218B2
JPS6317218B2 JP56033365A JP3336581A JPS6317218B2 JP S6317218 B2 JPS6317218 B2 JP S6317218B2 JP 56033365 A JP56033365 A JP 56033365A JP 3336581 A JP3336581 A JP 3336581A JP S6317218 B2 JPS6317218 B2 JP S6317218B2
Authority
JP
Japan
Prior art keywords
palladium
silver
external electrode
multilayer ceramic
ceramic capacitor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56033365A
Other languages
Japanese (ja)
Other versions
JPS57148333A (en
Inventor
Shigeaki Niiyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP3336581A priority Critical patent/JPS57148333A/en
Publication of JPS57148333A publication Critical patent/JPS57148333A/en
Publication of JPS6317218B2 publication Critical patent/JPS6317218B2/ja
Granted legal-status Critical Current

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  • Ceramic Capacitors (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)

Description

【発明の詳細な説明】 本発明は、積層セラミツクコンデンサおよびそ
の製造方法に関し、特に外部電極部のパラジウム
の含有状態の分布構造に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a multilayer ceramic capacitor and a method for manufacturing the same, and particularly to a distribution structure of palladium content in an external electrode portion.

一般に、この種の従来積層セラミツクコンデン
サは、第1図に示す如く誘電体グリーンシート1
の表面に、内部電極2を印刷し、これを互に逆方
向に複数枚積み重ね、熱加圧し一体化した後、焼
成して第2図の如くセラミツクチツプの両端部3
に、内部電極2の端面2aが露出した焼成セラミ
ツクチツプ4を作る。次に第3図に示す如く焼成
セラミツクチツプ4の両端部3に外部電極材料と
して、銀パラジウムペースト、または銀ペースト
を塗布し、乾燥した後、最高焼成温度830〜860℃
で10〜15分間(銀ペーストのとき750〜770℃で15
〜30分間)保持焼成した後、厚さ約100ミクロン
の外部電極5を形成していた。
Generally, this type of conventional multilayer ceramic capacitor has a dielectric green sheet 1 as shown in FIG.
The internal electrodes 2 are printed on the surface of the ceramic chip, a plurality of them are stacked in opposite directions, and after being heat-pressed and integrated, they are fired to form both ends 3 of the ceramic chip as shown in Fig. 2.
Next, a fired ceramic chip 4 in which the end surface 2a of the internal electrode 2 is exposed is made. Next, as shown in FIG. 3, silver-palladium paste or silver paste is applied as an external electrode material to both ends 3 of the fired ceramic chip 4, and after drying, the maximum firing temperature is 830-860°C.
for 10 to 15 minutes (15 minutes at 750 to 770℃ for silver paste)
After holding and firing for ~30 minutes, an external electrode 5 having a thickness of about 100 microns was formed.

このような従来の積層セラミツクコンデンサで
は外部電極5の材料に銀・パラジウムペースト
(パラジウム30重量%含有)を用いた場合には、 (イ) 価格面で、銀に比較し、パラジウムは10倍以
上と高価である。
In such conventional multilayer ceramic capacitors, when silver-palladium paste (containing 30% by weight of palladium) is used as the material for the external electrode 5, (a) palladium is more than 10 times more expensive than silver in terms of price; and expensive.

(ロ) 半田付け性が銀に比較し、銀パラジウムは1/
5以下の割合で銀に比べて悪い。
(b) Compared to silver, silver-palladium has 1/1 solderability.
It is worse than silver with a ratio of 5 or less.

(ハ) パラジウムは、温度450〜700℃で酸化し、酸
化パラジウムを生成して半田付け性を非常に悪
くする。そのために酸化パラジウムの生成量を
出来るだけ少なくするように焼成の温度と時間
をコントロールしなければならない。
(c) Palladium oxidizes at a temperature of 450 to 700°C, producing palladium oxide, which greatly impairs solderability. Therefore, the firing temperature and time must be controlled to minimize the amount of palladium oxide produced.

一方、銀ペーストのみを用いた場合には、半田
耐蝕性の割合が、銀・パラジウム:5に対して、
銀:1で、銀・パラジウムに比べて悪く内部電極
との接続がしばしば切断するという欠点を有して
いた。
On the other hand, when only silver paste is used, the ratio of solder corrosion resistance to silver/palladium: 5 is
Silver: 1, which was worse than silver/palladium, had the disadvantage that the connection with the internal electrodes was often broken.

本発明の目的は、かかる従来欠点を解決した積
層セラミツクコンデンサおよびその製造方法を提
供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a multilayer ceramic capacitor and a method for manufacturing the same which solves the above-mentioned drawbacks of the prior art.

本発明積層セラミツクコンデンサは、コンデン
サ素子両端の外部電極層に密接する下層部のパラ
ジウム(Pd)含有量10〜30重量%で、上層部に
向つてパラジウム(Pd)含有量が低く表面層の
パラジウム含有量が0重量%の銀を主成分とする
外部電極からなることを特徴とする。
The laminated ceramic capacitor of the present invention has a palladium (Pd) content of 10 to 30% by weight in the lower layer that is in close contact with the external electrode layers at both ends of the capacitor element, and a palladium (Pd) content in the surface layer that decreases toward the upper layer. It is characterized by consisting of an external electrode whose main component is silver with a content of 0% by weight.

以下、本発明を従来例(第3図)と本発明実施
例(第4図)とを参照しながら説明する。
The present invention will be explained below with reference to a conventional example (FIG. 3) and an embodiment of the present invention (FIG. 4).

第1図および第2図に示す従来方法により、誘
電体グリーンシート1の表面に、内部電極2を印
刷し、これを互に逆方向に複数枚積み重ねて、熱
加圧し一体化した後、焼成してセラミツクチツプ
の両端部3に内部電極2の端面2aが露出した焼
成セラミツクチツプ4を作る。次にこの両端部3
に、バインダー材と溶剤とガラスフリツト中にパ
ラジウム10〜30重量%含有する銀ペーストを厚さ
約50ミクロン塗布し、室温乾燥した後、この上に
溶剤とバインダー材とガラスフリツト材と、銀の
粒子径が上述の銀・パラジウムペーストと全く同
一の銀ペーストを厚さ約50ミクロン塗布して、室
温乾燥した後、最高焼成温度830〜860℃で10〜15
分間保持して焼成する。この焼成過程において、
ガラスフリツトの溶融、流れおよびパラジウム濃
度の差による拡散によつて、先きに塗布した銀・
パラジウムペースト中のパラジウムが、後から塗
布した銀ペースト中に入り込み第4図に示す外部
電極15を得ることが出来る。
By the conventional method shown in FIGS. 1 and 2, internal electrodes 2 are printed on the surface of a dielectric green sheet 1, and a plurality of sheets are stacked in opposite directions, heated and pressed to integrate, and then fired. Then, a fired ceramic chip 4 is produced in which the end surfaces 2a of the internal electrodes 2 are exposed at both ends 3 of the ceramic chip. Next, both ends 3
A silver paste containing 10 to 30% by weight of palladium in the binder material, solvent, and glass frit is applied to a thickness of about 50 microns, and after drying at room temperature, the solvent, binder material, glass frit material, and silver particle size are applied on top of the paste. A silver paste that is exactly the same as the silver/palladium paste described above was applied to a thickness of about 50 microns, dried at room temperature, and then fired at a maximum firing temperature of 830 to 860°C for 10 to 15 minutes.
Hold and bake for a minute. In this firing process,
The previously applied silver and
Palladium in the palladium paste penetrates into the silver paste applied later, and an external electrode 15 shown in FIG. 4 can be obtained.

第5図は、第4図に示す外部電極15のパラジ
ウム(Pd)の濃度勾配を示す図である。
FIG. 5 is a diagram showing the concentration gradient of palladium (Pd) in the external electrode 15 shown in FIG. 4.

以上、本発明により、外部電極の表面は半田付
け性の非常に良い銀で覆われ、内部になる程半田
耐蝕性の良いパラジウムの含有量が多くなるの
で、銀・パラジウム(パラジウム30重量%含有)
外部電極に比べて、 (i) 約36%安価になる。(下層部のパラジウム含
有量が30重量%の場合) (ii) 半田付け性が約5倍良くなる。
As described above, according to the present invention, the surface of the external electrode is covered with silver, which has very good solderability, and the content of palladium, which has good solder corrosion resistance, increases as it goes inside. )
Compared to external electrodes, (i) it is approximately 36% cheaper; (When the palladium content in the lower layer is 30% by weight) (ii) Solderability is approximately 5 times better.

(iii) 表面は銀面となるので酸化パラジウムの生成
を押えるための焼成温度等のコントロールをそ
れほど厳しく制約されることがない。
(iii) Since the surface is a silver surface, the control of firing temperature, etc. to suppress the formation of palladium oxide is not so severely restricted.

また、銀外部電極に比べて、 (i) 半田付け性は全く同じである。 Also, compared to silver external electrodes, (i) Solderability is exactly the same.

(ii) 半田耐蝕性は、内部が半田耐蝕性の大きいパ
ラジウムが多く含有しているので、良好とな
り、電極切れ等が発生しない。
(ii) The solder corrosion resistance is good because the inside contains a large amount of palladium, which has high solder corrosion resistance, and electrode breakage does not occur.

したがつて、外部電極を経済的に、かつ半田付
け性、半田耐蝕性を損なうことなく形成できるの
でその工業的価値は大である。
Therefore, it has great industrial value because external electrodes can be formed economically and without impairing solderability and solder corrosion resistance.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来例、本発明例に用いる内部電極を
印刷した誘電体グリーンシートの斜視図、第2図
は従来例、本発明例に用いる焼成セラミツクチツ
プの斜視図、第3図は従来の外部電極を形成した
積層セラミツクコンデンサの斜視図、第4図は本
発明外部電極を形成した積層セラミツクコンデン
サの斜視図、第5図は本発明の外部電極のパラジ
ウム含有量を示す勾配図。 1……誘電体グリーンシート、2……内部電
極、2a……内部電極の端面、3……焼成セラミ
ツクチツプの両端部、4……焼成セラミツクチツ
プ、5,15……外部電極。
Fig. 1 is a perspective view of a dielectric green sheet printed with internal electrodes used in a conventional example and an example of the present invention, Fig. 2 is a perspective view of a fired ceramic chip used in a conventional example and an example of the present invention, and Fig. 3 is a perspective view of a conventional example. FIG. 4 is a perspective view of a multilayer ceramic capacitor with an external electrode formed thereon, FIG. 4 is a perspective view of a multilayer ceramic capacitor with an external electrode formed thereon, and FIG. 5 is a gradient diagram showing the palladium content of the external electrode of the invention. DESCRIPTION OF SYMBOLS 1... Dielectric green sheet, 2... Internal electrode, 2a... End face of internal electrode, 3... Both ends of fired ceramic chip, 4... Fired ceramic chip, 5, 15... External electrode.

Claims (1)

【特許請求の範囲】 1 積層セラミツクコンデンサ素子両端の外部電
極層に密接する下層部のパラジウム(Pd)含有
量が10〜30重量%で上層部に向つてパラジウム
(Pd)含有量が低く表面層のパラジウム含有量が
0重量%の銀を主成分とする外部電極からなるこ
とを特徴とする積層セラミツクコンデンサ。 2 積層セラミツクコンデンサ素子両端部にパラ
ジウム(Pd)を10〜30重量%含有する第1の銀
ペーストを塗布、乾燥する工程と、前記ペースト
上に前記第1の銀ペーストからパラジウム(Pd)
分を除いた第2の銀ペーストを塗布、乾燥した後
焼成して外部電極を形成する工程からなることを
特徴とする積層セラミツクコンデンサの製造方
法。
[Claims] 1. The palladium (Pd) content of the lower layer in close contact with the external electrode layers at both ends of the multilayer ceramic capacitor element is 10 to 30% by weight, and the palladium (Pd) content is lower toward the upper layer of the surface layer. A multilayer ceramic capacitor comprising an external electrode mainly composed of silver with a palladium content of 0% by weight. 2. Applying a first silver paste containing 10 to 30% by weight of palladium (Pd) to both ends of a multilayer ceramic capacitor element and drying it, and applying palladium (Pd) from the first silver paste onto the paste.
1. A method for manufacturing a multilayer ceramic capacitor, comprising the steps of applying a second silver paste, drying and firing to form external electrodes.
JP3336581A 1981-03-09 1981-03-09 Laminated ceramic capacitor and method of prodcing same Granted JPS57148333A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3336581A JPS57148333A (en) 1981-03-09 1981-03-09 Laminated ceramic capacitor and method of prodcing same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3336581A JPS57148333A (en) 1981-03-09 1981-03-09 Laminated ceramic capacitor and method of prodcing same

Publications (2)

Publication Number Publication Date
JPS57148333A JPS57148333A (en) 1982-09-13
JPS6317218B2 true JPS6317218B2 (en) 1988-04-13

Family

ID=12384548

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3336581A Granted JPS57148333A (en) 1981-03-09 1981-03-09 Laminated ceramic capacitor and method of prodcing same

Country Status (1)

Country Link
JP (1) JPS57148333A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012231047A (en) * 2011-04-27 2012-11-22 Taiyo Yuden Co Ltd Chip shaped electronic component

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5079945U (en) * 1973-11-21 1975-07-10

Also Published As

Publication number Publication date
JPS57148333A (en) 1982-09-13

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