JPH04236412A - Electronic component of ceramic - Google Patents

Electronic component of ceramic

Info

Publication number
JPH04236412A
JPH04236412A JP3005012A JP501291A JPH04236412A JP H04236412 A JPH04236412 A JP H04236412A JP 3005012 A JP3005012 A JP 3005012A JP 501291 A JP501291 A JP 501291A JP H04236412 A JPH04236412 A JP H04236412A
Authority
JP
Japan
Prior art keywords
ceramic
main body
electrodes
capacitor
solder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3005012A
Other languages
Japanese (ja)
Inventor
Osamu Furukawa
修 古川
Yohachi Yamashita
洋八 山下
Hideyuki Kanai
金井 秀之
Naoaki Maki
真木 直明
Ichiro Suzuki
一郎 鈴木
Hiroshi Matsuo
松尾 博司
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP3005012A priority Critical patent/JPH04236412A/en
Publication of JPH04236412A publication Critical patent/JPH04236412A/en
Pending legal-status Critical Current

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  • Ceramic Capacitors (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)

Abstract

PURPOSE:To prevent the generation of cracks in an element occurring by temperature change at the time of soldering for board mounting, by constituting the outer electrode of an electronic ceramic component like a ceramic capacitor as a double-layered structure, and making the voids on the ceramic element main body side large as compared with the surface side. CONSTITUTION:A main body 1 is constituted by alternately laminating 20 layers of ceramic dielectric layers 2 and inner electrodes 3, and the end parts of the inner electrodes 3 are alternately exposed on facing side surfaces. Each side surface where the end parts are exposed, and the upper, the lower, the front and the rear surface parts in the vicinity of the side surfaces are coated with outer electrodes 9a, 9b whose voids are large. The outside thereof is coated with second outer electrodes 10a, 10b whose voids are small. By this packaging, a part of solder is wet and fixed on the surfaces of the second outer electrodes, and the solder is prevented from permeating into the first outer electrodes. As the result, the generation of cracks in the capacitor main body can be prevented, under rapid thermal change like a temperature cycle test.

Description

【発明の詳細な説明】[Detailed description of the invention]

[発明の目的] [Purpose of the invention]

【0001】0001

【産業上の利用分野】本発明は積層セラミックコンデン
サなどの、表面実装に用いられるのに好適なセラミック
電子部品に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to ceramic electronic components suitable for surface mounting, such as multilayer ceramic capacitors.

【0002】0002

【従来の技術】従来の積層セラミックコンデンサとして
は図2(A)に示す構造のものが知られている。すなわ
ち、図中の1は角型チップ形状をなす積層セラミックコ
ンデンサの素子本体であり、この本体1はセラミック誘
電体層2と内部電極層3とが交互に積層され、かつ、内
部電極3端部を対向する側面に交互に露出させた構造に
なっている。前記本体1の前記内部電極3端部が露出し
た各側面及び該側面近傍の上下面前後面部分にわたって
外部電極4a,4bがそれぞれ被覆されている。これら
の外部電極4a,4bは、例えば、セラミック誘電体層
2に対する密着性を高めるための2〜5wt%のガラス
フリットが含まれたAg系もしくはAg/Pd系の導電
材ペーストに前記本体1をその側面及びその近傍の上下
面部分にわたって浸せきし、焼き付けを行なうことによ
り形成される。
2. Description of the Related Art A conventional multilayer ceramic capacitor having a structure shown in FIG. 2(A) is known. That is, 1 in the figure is an element body of a multilayer ceramic capacitor having a square chip shape, and this body 1 has ceramic dielectric layers 2 and internal electrode layers 3 alternately laminated, and the end portions of the internal electrodes 3. The structure is such that the panels are exposed alternately on opposite sides. External electrodes 4a and 4b cover each side surface of the main body 1 where the ends of the internal electrodes 3 are exposed, as well as the front and rear surfaces of the upper and lower surfaces near the side surfaces. These external electrodes 4a and 4b are formed by, for example, applying the main body 1 to an Ag-based or Ag/Pd-based conductive material paste containing 2 to 5 wt% of glass frit to improve adhesion to the ceramic dielectric layer 2. It is formed by dipping and baking the side surfaces and upper and lower surface portions in the vicinity thereof.

【0003】この積層セラミックコンデンサを回路基板
に実装するには、図2(B)のように、はんだづけによ
りなされる。即ち、回路基板5の絶縁基材6表面に形成
された導体層7に前記構造のコンデンサをその本体1下
面のコーナー部が該導体層に当接するように仮止めした
後、フローまたはリフロー法により導体層7と本体1の
側面に位置する外部電極4a,4bとをはんだ層8によ
り接合することにより実装を行なう。この場合、通常外
部電極の厚みは約100〜200μmである。近年、大
容量の積層セラミックコンデンサの需要が高まっており
、このため、鉛ペロブスカイト化合物を主体とした高誘
電率のセラミック誘電体が用いられるようになってきて
いる。したがって、その形状も大型化しており、5.6
×5.0mmや7.5×6.3mmのような大型の積層
セラミックコンデンサも、鉛系誘電体材料を用いて製造
されはじめている。
This multilayer ceramic capacitor is mounted on a circuit board by soldering, as shown in FIG. 2(B). That is, after temporarily fixing the capacitor having the above structure to the conductor layer 7 formed on the surface of the insulating base material 6 of the circuit board 5 so that the corner portion of the lower surface of the main body 1 is in contact with the conductor layer, the capacitor is then fixed by a flow or reflow method. Mounting is performed by joining the conductor layer 7 and external electrodes 4a, 4b located on the side surfaces of the main body 1 with a solder layer 8. In this case, the thickness of the external electrode is usually about 100 to 200 μm. In recent years, demand for large-capacity multilayer ceramic capacitors has increased, and for this reason, ceramic dielectrics with high dielectric constants mainly composed of lead perovskite compounds have come to be used. Therefore, its shape has also become larger, 5.6
Large multilayer ceramic capacitors such as 5.0 mm x 7.5 x 6.3 mm are also beginning to be manufactured using lead-based dielectric materials.

【0004】しかしながら、このような、実装した積層
セラミックコンデンサは温度サイクル試験や熱衝撃試験
のような急激な熱変化を受けた場合に、セラミック誘電
体層、はんだ、導体層、絶縁基材、各々の熱膨脹係数の
差により、コンデンサ本体1に割れを発生するという問
題があった。この割れの発生は、積層セラミックコンデ
ンサ本体の寸法が大きいほど多く、特に、5.6×5.
0×1.8mmやこれ以上といった寸法の大型のチップ
積層セラミックコンデンサを実装した場合に信頼性が低
下するといった問題点があった。
However, when such a mounted multilayer ceramic capacitor is subjected to sudden thermal changes such as a temperature cycle test or a thermal shock test, the ceramic dielectric layer, solder, conductor layer, and insulating base material each break down. There was a problem in that cracks occurred in the capacitor body 1 due to the difference in thermal expansion coefficients. This cracking is more likely to occur as the size of the multilayer ceramic capacitor body becomes larger, especially for 5.6 x 5.
There is a problem in that reliability decreases when a large chip multilayer ceramic capacitor with dimensions of 0 x 1.8 mm or more is mounted.

【0005】[0005]

【発明が解決しようとする課題】本発明は、上記の問題
点を解決するためになされたもので、大型の素子を回路
基板へ実装した後の温度サイクル試験等の温度の急激な
変化に対しても割れ発生を防止したセラミック電子部品
を提供しようとするものである。 [発明の構成]
[Problems to be Solved by the Invention] The present invention has been made to solve the above-mentioned problems. The aim is to provide a ceramic electronic component that is free from cracking even when exposed to heat. [Structure of the invention]

【0006】[0006]

【発明を解決するための手段及び作用】本発明は、セラ
ミック素子本体に付与される外部電極が、素子本体に近
い領域の方が表面領域に比べ気孔率が大であることを特
徴とするセラミック電子部品である。具体的にはセラミ
ックコンデンサ等のチップ部品が挙げられる。
Means for Solving the Invention and Effects of the Invention The present invention provides an external electrode applied to a ceramic element body, which is a ceramic element characterized in that an area close to the element body has a higher porosity than a surface area. It is an electronic component. Specifically, chip components such as ceramic capacitors can be mentioned.

【0007】この様なセラミック電子部品は、例えば、
電極ペーストを塗布し焼き付けして外部電極を形成する
工程において、導電粉末40〜50wt%,無機バイン
ダ2〜5wt%,樹脂バインダ20〜30wt%,有機
溶剤残部からなる第一の電極ペーストを塗布し乾燥させ
た後、導電粉末40〜50wt%,無機バインダ0wt
%,樹脂バインダ10〜15wt%,有機溶剤残部から
なる第2の電極ペーストを塗布し乾燥させ、その後、第
1の電極ペーストおよび第2の電極ペーストを高温で焼
き付けて外部電極を形成することにより製造することが
できる。
[0007] Such ceramic electronic components are, for example,
In the step of applying and baking an electrode paste to form an external electrode, a first electrode paste consisting of 40 to 50 wt% conductive powder, 2 to 5 wt% inorganic binder, 20 to 30 wt% resin binder, and the remainder organic solvent is applied. After drying, conductive powder 40-50wt%, inorganic binder 0wt
%, a resin binder of 10 to 15 wt%, and the remainder of an organic solvent.A second electrode paste is applied and dried, and then the first electrode paste and the second electrode paste are baked at a high temperature to form an external electrode. can be manufactured.

【0008】本発明において、外部電極の多孔質の割合
を比較するためには、例えば、簡単には目視により比較
することができる。また、定量的には、形成される外部
電極の断面における気孔の全断面に対する面積比をもっ
て定義することができる。このような手法は、EIA規
格RS−198Cの60ページにピンホールもしくはボ
イドの解析用のマップとして記載されている手法と同一
である。また、多孔質の割合を変え、制御するには、第
1および第2の外部電極ペースト中の樹脂バインダの含
有量を制御することにより達成できる。
In the present invention, the porosity ratio of the external electrodes can be easily compared by visual inspection, for example. Further, quantitatively, it can be defined by the area ratio of the pores in the cross section of the formed external electrode to the total cross section. Such a method is the same as the method described on page 60 of the EIA standard RS-198C as a map for pinhole or void analysis. Furthermore, the porosity ratio can be changed and controlled by controlling the content of the resin binder in the first and second external electrode pastes.

【0009】本発明電子部品の一例としての積層セラミ
ックコンデンサは、図1(A)に示すような構造をとる
。すなわち、図中の1は角型チップ形状をなす積層セラ
ミックコンデンサ本体であり、この本体1はセラミック
誘電体層2と内部電極3とが交互に積層され、かつ、内
部電極3端部を対向する側面に交互に露出させた構造に
なっている。第1の外部電極9a,9bは前記本体1の
前記内部電極3端部が露出された各側面及び該側面近傍
の上下面前後面にわたって形成される。また、第2の外
部電極10a,10bは、この第1の外部電極9a,9
bの上に形成される。
A multilayer ceramic capacitor as an example of the electronic component of the present invention has a structure as shown in FIG. 1(A). That is, 1 in the figure is a multilayer ceramic capacitor main body in the shape of a square chip, and this main body 1 has ceramic dielectric layers 2 and internal electrodes 3 stacked alternately, and the ends of the internal electrodes 3 face each other. It has a structure in which the sides are exposed alternately. The first external electrodes 9a, 9b are formed on each side surface of the main body 1 where the ends of the internal electrodes 3 are exposed, and on the upper, lower, front and rear surfaces in the vicinity of the side surfaces. Further, the second external electrodes 10a, 10b are similar to the first external electrodes 9a, 9.
formed on b.

【0010】図3に前記第1および第2の外部電極9b
および10bの断面の拡大図を示す。図中のセラミック
本体11の上に第1の外部電極12、その上に第2の外
部電極13が形成されており、さらに実装時にははんだ
層14が形成される。第1の外部電極が第2の外部電極
よりも気孔率が大きい、すなわち多孔質であると、回路
基板等に実装後の温度サイクル試験等の急激な温度変化
において生ずる熱膨脹の差によるひずみを、第1の外部
電極が緩衝部材となってやわらげる作用をする。第1の
外部電極の厚みは、積層セラミックコンデンサの形状寸
法により異なるが、すくなくとも30μm以上、好まし
くは100〜150μm程度であると、上述の効果が発
揮できる。一方、第2の外部電極は、回路基板の実装時
に生ずるはんだのしみ込みを防止する必要があるため、
気孔率はすくないことが必要である。また、第2の外部
電極の厚みはこのはんだしみ込み防止のためと、はんだ
付けの際のぬれ性をよくするため、必要な厚み、通常3
0μm以上必要であるが、あまり厚すぎると前述の第1
の外部電極の緩衝効果を妨げるので、100μm以下で
あることが好ましい。
FIG. 3 shows the first and second external electrodes 9b.
and 10b are shown enlarged cross-sectional views. A first external electrode 12 is formed on the ceramic body 11 in the figure, a second external electrode 13 is formed thereon, and a solder layer 14 is further formed upon mounting. If the first external electrode has a higher porosity than the second external electrode, that is, it is porous, the strain due to the difference in thermal expansion that occurs during rapid temperature changes such as temperature cycle tests after being mounted on a circuit board etc. The first external electrode serves as a buffer member and has a softening effect. Although the thickness of the first external electrode varies depending on the shape and dimensions of the multilayer ceramic capacitor, the above-mentioned effects can be achieved if the thickness is at least 30 μm or more, preferably about 100 to 150 μm. On the other hand, the second external electrode needs to prevent solder from seeping in when mounting the circuit board.
It is necessary that the porosity be low. In addition, the thickness of the second external electrode is set to the necessary thickness, usually 3.5 mm, in order to prevent this solder from seeping in and to improve wettability during soldering.
It is necessary to have a thickness of 0 μm or more, but if it is too thick, the above-mentioned first problem will occur.
The thickness is preferably 100 μm or less because it hinders the buffering effect of the external electrode.

【0011】なお、本発明において、外部電極が2層の
場合について例をあげて説明したが、3層もしくはそれ
以上の場合でも、外部電極のセラミック側が気孔率大で
あり、表面側が気孔率小の条件を満たせば良い。本発明
によれば、大型の素子を回路基板に実装した後の温度サ
イクル試験等の急激な熱変化による割れ発生防止効果を
著しく高めることが可能になる。
[0011] In the present invention, the case where the external electrode has two layers has been described as an example, but even in the case of three or more layers, the ceramic side of the external electrode has a high porosity and the surface side has a low porosity. It is sufficient if the following conditions are met. According to the present invention, it is possible to significantly enhance the effect of preventing cracks from occurring due to sudden thermal changes such as during a temperature cycle test after a large element is mounted on a circuit board.

【0012】0012

【実施例】以下、本発明の実施例を図面を参照して詳細
に説明する。
Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

【0013】図1(A)は本実施例の積層セラミックコ
ンデンサの断面図である。図中の1は、例えば、寸法7
.5×6.3×2.0mmの角型チップ形状をなす積層
セラミックコンデンサ本体であり、この本体1はセラミ
ック誘電体層2と内部電極とが交互に20層積層され、
かつ、内部電極3端部を対向する側面に交互に露出させ
た構造になっている。前記本体1の前記内部電極3端部
が露出した各側面および該側面近傍の上下面前後面部分
にわたって、気孔率が大きい第1の外部電極9a,9b
が各々被覆されている。これらの第1の外部電極は、例
えば、Ag粉末45wt%,ガラスフリット4wt%,
エチルセルロース25wt%,2ブチルカルビトール残
部からなる第1の電極ペーストを塗布、乾燥させた後、
700℃前後焼き付けすることにより、形成される。も
しくは、後述の第2の電極ペーストを塗布、乾燥させた
後に、同時に焼き付けを行なってもよい。
FIG. 1A is a sectional view of the multilayer ceramic capacitor of this example. 1 in the figure is, for example, the dimension 7
.. This is a multilayer ceramic capacitor body having a square chip shape of 5 x 6.3 x 2.0 mm, and this body 1 has 20 layers of ceramic dielectric layers 2 and internal electrodes stacked alternately.
Moreover, the structure is such that the ends of the internal electrodes 3 are exposed alternately on the opposing side surfaces. First external electrodes 9a, 9b having a high porosity are provided over each side surface of the main body 1 where the end portions of the internal electrodes 3 are exposed and the front and rear surfaces of the upper and lower surfaces near the side surfaces.
are each coated. These first external electrodes are made of, for example, 45 wt% Ag powder, 4 wt% glass frit,
After applying and drying a first electrode paste consisting of 25 wt% ethyl cellulose and the remainder 2-butyl carbitol,
It is formed by baking at around 700°C. Alternatively, baking may be performed simultaneously after applying and drying a second electrode paste to be described later.

【0014】また、前記外部電極9a,9bの外側には
、気孔率の小さい第2の外部電極10a,10bがそれ
ぞれ被覆されている。これらの第2の外部電極は、例え
ば、Ag粉末45wt%,エチルセルロース10wt%
,ブチルカルビトール残部からなり、ガラスフリットを
含まない第2の電極ペーストを前記第1の外部電極の上
に塗布、乾燥させた後、700℃前後で焼き付けするこ
とにより形成される。このような構成の積層セラミック
コンデンサを回路基板に実装するには、図1(B)に示
すように、回路基板5の絶縁基材6表面に形成された導
体層7に前記構造コンデンサをその本体1下面のコーナ
ー部が該導体層7に当接するように仮止めした後、フロ
ー法もしくはリフロー法により、導体層7と本体1の側
面に位置する第2の外部電極10a,10bとをはんだ
層8により接合することにより行なわれる。
Further, the outer sides of the external electrodes 9a and 9b are coated with second external electrodes 10a and 10b having a small porosity, respectively. These second external electrodes are made of, for example, 45 wt% Ag powder and 10 wt% ethyl cellulose.
, the remainder of butyl carbitol, and does not contain glass frit, is applied onto the first external electrode, dried, and then baked at around 700°C. In order to mount a multilayer ceramic capacitor having such a configuration on a circuit board, as shown in FIG. After temporarily fixing the corner portion of the lower surface of the main body 1 so that it is in contact with the conductor layer 7, the conductor layer 7 and the second external electrodes 10a and 10b located on the side surface of the main body 1 are soldered using a flow method or a reflow method. This is done by joining by 8.

【0015】このような実装を行なうことにより第2の
外部電極表面にはんだが一部ぬれて固着され、なおかつ
、第1の外部電極中へのはんだのしみ込みが防止され、
その結果、温度サイクル試験のような急激な熱変化をう
けても、第1の外部電極が緩衝層として有効に機能する
ため、各部材の熱膨脹係数の差によるコンデンサ本体の
割れ発生を防止でき、高信頼性の積層セラミックコンデ
ンサを得ることができる。
By carrying out such mounting, the solder is partially wetted and fixed on the surface of the second external electrode, and the solder is prevented from seeping into the first external electrode.
As a result, even when subjected to sudden thermal changes such as during a temperature cycle test, the first external electrode effectively functions as a buffer layer, which prevents the capacitor body from cracking due to differences in the coefficient of thermal expansion of each member. A highly reliable multilayer ceramic capacitor can be obtained.

【0016】(Pb0.875 Ba0.125 )(
Zn1/3 Nb2/3 )0.3 (Mg1/3 N
b2/3)0.5 Ti0.2 O3 のセラミック誘
電体組成からなり、寸法7.5×6.3×2.0mmの
積層セラミックコンデンサを、前述の要領で作成し、図
1(B)のように回路基板に実装した20個のサンプル
を用意し、125℃で30分間、−55℃で30分間の
冷熱サイクル試験を行ない、50サイクルの故障数を測
定した。なお、容量が初期値よりも10%を越えて低下
したコンデンサを故障と判定した。その結果、従来のサ
ンプルでは割れによる故障が15個も認められたが、本
実施例では20個すべてが良好で、故障発生が皆無であ
った。
(Pb0.875 Ba0.125) (
Zn1/3 Nb2/3 )0.3 (Mg1/3 N
b2/3) A multilayer ceramic capacitor with a ceramic dielectric composition of 0.5 Ti0.2 O3 and dimensions of 7.5 x 6.3 x 2.0 mm was fabricated as described above, and the capacitor shown in Fig. 1(B) was prepared. Twenty samples mounted on circuit boards as described above were prepared, and a thermal cycle test was conducted at 125°C for 30 minutes and at -55°C for 30 minutes, and the number of failures over 50 cycles was measured. Note that a capacitor whose capacity decreased by more than 10% from the initial value was determined to be a failure. As a result, as many as 15 failures due to cracks were observed in the conventional samples, but in this example, all 20 were in good condition, with no failures occurring.

【0017】[0017]

【発明の効果】以上、詳述したように、本発明によれば
、回路基板等への実装後の温度サイクル試験等の急激な
熱変化に対しても、割れ発生を防止した高信頼性のセラ
ミック電子部品を提供できる。また、鉛を含むペロブス
カイト化合物からなり、形状が5.6×5.0×1.8
mm以上の積層セラミックコンデンサに対して特に効果
を発揮する。
Effects of the Invention As described in detail above, according to the present invention, a highly reliable product that prevents cracking even under sudden thermal changes such as temperature cycle tests after being mounted on a circuit board, etc. We can provide ceramic electronic components. It is also made of a perovskite compound containing lead, and has a shape of 5.6 x 5.0 x 1.8
It is particularly effective for multilayer ceramic capacitors with a diameter of mm or more.

【図面の簡単な説明】[Brief explanation of the drawing]

【図1】  本発明セラミック電子部品の断面図。FIG. 1 is a cross-sectional view of the ceramic electronic component of the present invention.

【図2】  従来のセラミック電子部品の断面図。[Fig. 2] Cross-sectional view of a conventional ceramic electronic component.

【図3】  本発明セラミック電子部品の拡大断面図。FIG. 3 is an enlarged cross-sectional view of the ceramic electronic component of the present invention.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】セラミック素子本体に付与される外部電極
が、素子本体に近い領域の方が、表面領域に比べ気孔率
が大であることを特徴とするセラミック電子部品。
1. A ceramic electronic component characterized in that an external electrode applied to a ceramic element body has a higher porosity in a region closer to the element body than in a surface region.
JP3005012A 1991-01-21 1991-01-21 Electronic component of ceramic Pending JPH04236412A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3005012A JPH04236412A (en) 1991-01-21 1991-01-21 Electronic component of ceramic

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3005012A JPH04236412A (en) 1991-01-21 1991-01-21 Electronic component of ceramic

Publications (1)

Publication Number Publication Date
JPH04236412A true JPH04236412A (en) 1992-08-25

Family

ID=11599629

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3005012A Pending JPH04236412A (en) 1991-01-21 1991-01-21 Electronic component of ceramic

Country Status (1)

Country Link
JP (1) JPH04236412A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006344820A (en) * 2005-06-09 2006-12-21 Tdk Corp Method of manufacturing ceramic electronic component
JP2011139021A (en) * 2009-12-30 2011-07-14 Samsung Electro-Mechanics Co Ltd Multilayer ceramic capacitor
JP2015023120A (en) * 2013-07-18 2015-02-02 Tdk株式会社 Laminated capacitor
WO2016133090A1 (en) * 2015-02-16 2016-08-25 京セラ株式会社 Chip electronic component and module
JP2018157183A (en) * 2016-09-28 2018-10-04 株式会社村田製作所 Electronic component
WO2024161946A1 (en) * 2023-01-30 2024-08-08 太陽誘電株式会社 Multilayer ceramic capacitor

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006344820A (en) * 2005-06-09 2006-12-21 Tdk Corp Method of manufacturing ceramic electronic component
JP4618010B2 (en) * 2005-06-09 2011-01-26 Tdk株式会社 Manufacturing method of ceramic electronic component
JP2011139021A (en) * 2009-12-30 2011-07-14 Samsung Electro-Mechanics Co Ltd Multilayer ceramic capacitor
US8248752B2 (en) 2009-12-30 2012-08-21 Samsung Electro-Mechanics Co., Ltd. Multilayer ceramic capacitor
JP2015023120A (en) * 2013-07-18 2015-02-02 Tdk株式会社 Laminated capacitor
WO2016133090A1 (en) * 2015-02-16 2016-08-25 京セラ株式会社 Chip electronic component and module
JPWO2016133090A1 (en) * 2015-02-16 2017-12-07 京セラ株式会社 Chip-type electronic components and modules
JP2018157183A (en) * 2016-09-28 2018-10-04 株式会社村田製作所 Electronic component
WO2024161946A1 (en) * 2023-01-30 2024-08-08 太陽誘電株式会社 Multilayer ceramic capacitor

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