JP2015023120A - Laminated capacitor - Google Patents

Laminated capacitor Download PDF

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JP2015023120A
JP2015023120A JP2013149361A JP2013149361A JP2015023120A JP 2015023120 A JP2015023120 A JP 2015023120A JP 2013149361 A JP2013149361 A JP 2013149361A JP 2013149361 A JP2013149361 A JP 2013149361A JP 2015023120 A JP2015023120 A JP 2015023120A
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plating layer
plating
electrode
multilayer capacitor
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JP6201474B2 (en
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通 尾上
Tooru Ogami
通 尾上
智紀 杉山
Tomonori Sugiyama
智紀 杉山
岳史 大沼
Takeshi Onuma
岳史 大沼
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Tdk株式会社
Tdk Corp
Tdk株式会社
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Abstract

PROBLEM TO BE SOLVED: To provide a laminated capacitor in which cracking of an element can be suppressed.SOLUTION: A laminated capacitor 1 includes an element 10, terminal electrodes 14A, 14B arranged at both ends of the element 10, and internal electrodes 12A, 12B arranged in the element 10 and connected with the terminal electrodes 14A, 14B, respectively. The terminal electrodes 14A, 14B have outside plating layers 14A, 14Bconstituting the outermost surface thereof, respectively, and inside plating layers 14A, 14Blocated between the elements 10. The outside plating layers 14A, 14Bcontain Cu, Ag, Au, Ni, Pd or Sn as a main component. The inside plating layers 14A, 14Bhave a density smaller than that of the outside plating layers 14A, 14B.

Description

本発明は、積層コンデンサに関する。   The present invention relates to a multilayer capacitor.
特許文献1は、セラミック素体と、セラミック素体の表面に形成された端子電極とを備えるセラミック電子部品を開示している。端子電極は、セラミック素体の表面に配置された下地電極層と、下地電極層上に配置された第1のCuめっき層と、第1のCuめっき層上に配置された第2のCuめっき層とを有する。第2のCuめっき層は、第1のCuめっき層及び下地電極層の熱処理後に形成される。   Patent document 1 is disclosing the ceramic electronic component provided with a ceramic element | base_body and the terminal electrode formed in the surface of the ceramic element | base_body. The terminal electrode includes a base electrode layer disposed on the surface of the ceramic body, a first Cu plating layer disposed on the base electrode layer, and a second Cu plating disposed on the first Cu plating layer. And having a layer. The second Cu plating layer is formed after the heat treatment of the first Cu plating layer and the base electrode layer.
特開2012−009813号公報JP 2012-009813 A
本発明の目的は、素体へのクラック発生を抑制することが可能な積層コンデンサを提供することにある。   An object of the present invention is to provide a multilayer capacitor capable of suppressing the occurrence of cracks in an element body.
素体へのクラック発生を抑制することが可能な積層コンデンサを得るために、本発明者が鋭意研究したところ、端子電極を構成するめっき層の密度がクラック発生の一つの要因であるという新たな知見を見出だした。すなわち、めっき層の密度に応じてめっき層に含まれる空孔の多寡が左右されるので、めっき層に含まれる空孔が少ないほどめっき層に生じた応力が緩和され難くなる結果、当該応力が素体に伝達してクラックが生じうる、ということが判明した。   In order to obtain a multilayer capacitor capable of suppressing the occurrence of cracks in the element body, the present inventors have intensively studied and found that the density of the plating layer constituting the terminal electrode is a factor in the occurrence of cracks. I have found out. That is, since the number of holes included in the plating layer depends on the density of the plating layer, the less the holes included in the plating layer, the more difficult the stress generated in the plating layer is relaxed. It was found that cracks could occur when transmitted to the element body.
例えば、特許文献1に係るセラミック電子部品の端子電極においては、第1のCuめっき層は熱処理により緻密になるので、第1のCuめっき層の密度は第2のCuめっき層の密度よりも大きいと推定される。つまり、密度の高い第1のCuめっき層が下地電極層上に配置されている。従って、本発明者が見出だした新たな知見によれば、第1のCuめっき層の形成過程で第1のCuめっき層自身に内部応力が生じたり、セラミック電子部品に外部から力が加わるなどにより第1のCuめっき層に応力が作用した場合に、それらの応力は、第1のCuめっき層において緩和されず、セラミック素体にも作用する。その結果、セラミック素体にクラック(欠けや割れなど)が生ずる場合がある。   For example, in the terminal electrode of the ceramic electronic component according to Patent Document 1, since the first Cu plating layer becomes dense by heat treatment, the density of the first Cu plating layer is larger than the density of the second Cu plating layer. It is estimated to be. That is, the high-density first Cu plating layer is disposed on the base electrode layer. Therefore, according to the new knowledge discovered by the present inventor, internal stress is generated in the first Cu plating layer itself in the process of forming the first Cu plating layer, or external force is applied to the ceramic electronic component. Therefore, when stress acts on the first Cu plating layer, those stresses are not relaxed in the first Cu plating layer and also act on the ceramic body. As a result, cracks (chips, cracks, etc.) may occur in the ceramic body.
これに対して、本発明の一つの観点に係る積層コンデンサは、互いに対向する一対の端面と、一対の端面同士を連結するように延びると共に互いに対向する一対の主面と、一対の端面同士及び一対の主面同士を連結するように延びると共に互いに対向する一対の側面とを有し、一対の主面の間の寸法が、一対の端面の間の寸法及び一対の側面の間の寸法よりも小さい素体と、素体のうち一方の端面側に位置すると共に、主面と、端面及び側面の少なくとも一方とにわたって連続して延びるように素体の表面に配置された第1の端子電極と、素体のうち他方の端面側に位置すると共に、主面と、端面及び側面の少なくとも一方とにわたって連続して延びるように素体の表面に配置された第2の端子電極と、素体内に位置すると共に、第1の端子電極に接続された第1の内部電極と、素体内に位置すると共に、第2の端子電極に接続された第2の内部電極とを備え、第1及び第2の内部電極は、一対の主面の対向方向において隣り合って配置されていると共に、対向方向から見たときに互いに一部が重なり合っており、第1及び第2の端子電極はそれぞれ、その最外表面を構成する第1のめっき層と、第1のめっき層及び素体の間に位置する第2のめっき層とを有し、第1のめっき層は、Cu、Ag、Au、Ni、Pd又はSnを主成分として含み、第2のめっき層の密度は、第1のめっき層の密度よりも小さい。   On the other hand, the multilayer capacitor according to one aspect of the present invention includes a pair of end faces facing each other, a pair of main faces extending to connect the pair of end faces and facing each other, a pair of end faces, and A pair of side surfaces extending to connect the pair of main surfaces and facing each other, and the dimension between the pair of main surfaces is larger than the dimension between the pair of end surfaces and the dimension between the pair of side surfaces. A small element body, and a first terminal electrode disposed on the surface of the element body so as to continuously extend over at least one of the main surface and the end surface and the side surface while being positioned on one end face side of the element body A second terminal electrode disposed on the surface of the element body so as to be located on the other end face side of the element body and continuously extending over at least one of the end surface and the side surface; And a first terminal A first internal electrode connected to the electrode and a second internal electrode located in the element body and connected to the second terminal electrode, wherein the first and second internal electrodes are a pair of main electrodes. The first terminal electrode and the second terminal electrode are arranged adjacent to each other in the opposing direction of the surfaces, and partially overlap each other when viewed from the opposing direction. A plating layer and a second plating layer located between the first plating layer and the element body, the first plating layer containing Cu, Ag, Au, Ni, Pd or Sn as a main component; The density of the second plating layer is smaller than the density of the first plating layer.
本発明の一つの観点に係る積層コンデンサでは、第1及び第2の端子電極がそれぞれ第1及び第2のめっき層とを有し、第2のめっき層の密度が第1のめっき層の密度よりも小さい。第2のめっき層には第1のめっき層よりも多くの空孔が含まれているので、第2のめっき層に作用する応力は空孔の存在によって緩和される。そのため、第1のめっき層の形成過程で第1のめっき層自身に内部応力が生じたり、積層コンデンサに外部から力が加わるなどにより第1のめっき層に応力が作用すると、それらの応力は、第2のめっき層において緩和され、素体に作用し難くなる。その結果、素体にクラック(欠けや割れなど)が発生することを抑制できる。   In the multilayer capacitor according to one aspect of the present invention, the first and second terminal electrodes respectively have the first and second plating layers, and the density of the second plating layer is the density of the first plating layer. Smaller than. Since the second plating layer contains more holes than the first plating layer, the stress acting on the second plating layer is relieved by the presence of the holes. Therefore, when stress is applied to the first plating layer due to an internal stress generated in the first plating layer itself in the process of forming the first plating layer or a force is applied to the multilayer capacitor from the outside, these stresses are: It is relaxed in the second plating layer and hardly acts on the element body. As a result, it is possible to suppress the occurrence of cracks (chips, cracks, etc.) in the element body.
本発明の一つの観点に係る積層コンデンサでは、第1のめっき層がCu、Ag、Au、Ni、Pd又はSnを主成分として含んでいる。そのため、本発明の一つの観点に係る積層コンデンサを基板等に実装する際に、当該積層コンデンサの端子電極と、基板等のビア導体との接続が良好に行える。しかも、第1のめっき層は、第2のめっき層よりも密度が高く表面がより緻密であるので、当該積層コンデンサの基板等への実装時に、当該積層コンデンサの端子電極と基板等のビア導体とがより強固に固着しやすい。従って、当該積層コンデンサをより確実に基板等に実装することが可能となる。   In the multilayer capacitor according to one aspect of the present invention, the first plating layer contains Cu, Ag, Au, Ni, Pd, or Sn as a main component. Therefore, when the multilayer capacitor according to one aspect of the present invention is mounted on a substrate or the like, the terminal electrode of the multilayer capacitor and a via conductor such as the substrate can be connected well. In addition, since the first plating layer has a higher density and a denser surface than the second plating layer, the terminal electrode of the multilayer capacitor and the via conductor such as the substrate when the multilayer capacitor is mounted on the substrate or the like. And are more likely to be firmly fixed. Therefore, the multilayer capacitor can be more reliably mounted on a substrate or the like.
本発明の一つの観点に係る積層コンデンサでは、一対の主面の間の寸法が、一対の端面の間の寸法及び一対の側面の間の寸法よりも小さい。そのため、本発明の一つの観点に係る積層コンデンサは、いわゆる低背型の積層コンデンサとして構成される。加えて、第1及び第2の端子電極が少なくとも主面に配置されているので、当該積層コンデンサを回路基板に内蔵したり、LSI(Large Scale Integration)に埋め込んで実装することが可能となる。ところで、積層コンデンサを回路基板等に埋め込む実装構造においては、積層コンデンサの端子電極が露出するようにレーザビーム等を用いて回路基板等に貫通孔(ビアホール)を形成し、当該貫通孔内にビア導体を埋め込むことにより、ビア導体と積層コンデンサの端子電極とが接続される。このような実装構造では、端子電極の電流ループ距離が短くなるため、等価直列インダクタンス(ESL)を低くできる。   In the multilayer capacitor according to one aspect of the present invention, the dimension between the pair of main surfaces is smaller than the dimension between the pair of end surfaces and the dimension between the pair of side surfaces. Therefore, the multilayer capacitor according to one aspect of the present invention is configured as a so-called low profile multilayer capacitor. In addition, since the first and second terminal electrodes are disposed on at least the main surface, the multilayer capacitor can be built in a circuit board or embedded in an LSI (Large Scale Integration). By the way, in a mounting structure in which a multilayer capacitor is embedded in a circuit board or the like, a through hole (via hole) is formed in the circuit board or the like using a laser beam or the like so that the terminal electrode of the multilayer capacitor is exposed, and a via is formed in the through hole. By burying the conductor, the via conductor and the terminal electrode of the multilayer capacitor are connected. In such a mounting structure, since the current loop distance of the terminal electrode is shortened, the equivalent series inductance (ESL) can be lowered.
第1及び第2のめっき層は共にCuを主成分として含んでいてもよい。この場合、第1及び第2のめっき層が共に同じ材料を主成分として含んでいるので、両者の界面における固着性を高めることができる。   Both the first and second plating layers may contain Cu as a main component. In this case, since both the first and second plating layers contain the same material as the main component, the adhesion at the interface between them can be improved.
第1及び第2の端子電極はそれぞれ、素体の表面に位置する焼付電極層と、焼付電極層を覆う第2のめっき層と、第2のめっき層を覆う第1のめっき層とを有し、焼付電極層はCuを主成分として含んでいてもよい。この場合、素体の表面に位置する焼付電極層に内部電極が接続されるので、端子電極と内部電極とをより確実に接続することができる。またこの場合、焼付電極層、第1のめっき層及び第2のめっき層がいずれも同じ材料を主成分として含んでいるので、焼付電極層と第2のめっき層との界面、及び第2のめっき層と第1のめっき層との界面における固着性を高めることができる。   Each of the first and second terminal electrodes has a baked electrode layer located on the surface of the element body, a second plated layer covering the baked electrode layer, and a first plated layer covering the second plated layer. The baked electrode layer may contain Cu as a main component. In this case, since the internal electrode is connected to the baked electrode layer located on the surface of the element body, the terminal electrode and the internal electrode can be more reliably connected. Further, in this case, since the baking electrode layer, the first plating layer, and the second plating layer all contain the same material as the main component, the interface between the baking electrode layer and the second plating layer, and the second Adhesiveness at the interface between the plating layer and the first plating layer can be enhanced.
第1及び第2の端子電極はそれぞれ、素体の表面に位置する焼付電極層と、焼付電極層を覆う第2のめっき層と、第2のめっき層を覆う第1のめっき層とを有し、第2のめっき層はNiを主成分として含んでおり、第1のめっき層はCuを主成分として含んでいてもよい。この場合、NiはCuよりも熱伝導率が低いので、積層コンデンサに熱が加わった場合でも、第1のめっき層から素体への熱伝達が第2のめっき層によって妨げられる。そのため、積層コンデンサの回路基板等への実装に際して積層コンデンサに熱が加わった場合でも、当該熱によって素体の内部に生じうる損傷(ダメージ)を低減することができる。特に、積層コンデンサを回路基板等に埋め込む実装構造においては、回路基板等に貫通孔(ビアホール)を形成する際に、レーザビームが積層コンデンサの端子電極に照射される。そのため、積層コンデンサの端子電極に大きな熱が作用する傾向にある。しかしながら、第2のめっき層がNiを主成分として含んでおり、第1のめっき層がCuを主成分として含んでいる場合には、レーザビームによって素体の内部に生じうる損傷(ダメージ)も低減することができる。   Each of the first and second terminal electrodes has a baked electrode layer located on the surface of the element body, a second plated layer covering the baked electrode layer, and a first plated layer covering the second plated layer. The second plating layer may contain Ni as a main component, and the first plating layer may contain Cu as a main component. In this case, since Ni has a lower thermal conductivity than Cu, even when heat is applied to the multilayer capacitor, heat transfer from the first plating layer to the element body is hindered by the second plating layer. Therefore, even when heat is applied to the multilayer capacitor when the multilayer capacitor is mounted on a circuit board or the like, damage (damage) that can occur inside the element body due to the heat can be reduced. In particular, in a mounting structure in which a multilayer capacitor is embedded in a circuit board or the like, a laser beam is applied to the terminal electrode of the multilayer capacitor when a through hole (via hole) is formed in the circuit board or the like. For this reason, large heat tends to act on the terminal electrode of the multilayer capacitor. However, when the second plating layer contains Ni as a main component and the first plating layer contains Cu as a main component, damage (damage) that may occur inside the element body due to the laser beam is also caused. Can be reduced.
第1のめっき層の厚さは、第2のめっき層の厚さよりも大きくてもよい。積層コンデンサを回路基板等に埋め込む実装構造においては、回路基板等に貫通孔(ビアホール)を形成する際に、レーザビームが積層コンデンサの端子電極に照射される。そのため、端子電極のうちレーザビームが照射された部分が、レーザビームにより除去される場合がある。しかしながら、第1のめっき層の厚さが第2のめっき層の厚さよりも大きい場合には、第1のめっき層の厚さを十分に確保できる。そのため、レーザビームによって第1のめっき層が部分的に除去されるのに止まるので、素体の内部に損傷が生ずる虞を低減することができる。なお、第1のめっき層が厚いほど、第1のめっき層自身に生ずる内部応力が高くなる傾向にある。しかしながら、本発明の一つの観点に係る積層コンデンサでは、第1のめっき層よりも密度が小さい第2のめっき層が存在しているため、第1のめっき層自身に生ずる内部応力を第2のめっき層において緩和することが可能である。   The thickness of the first plating layer may be larger than the thickness of the second plating layer. In a mounting structure in which a multilayer capacitor is embedded in a circuit board or the like, a laser beam is applied to the terminal electrode of the multilayer capacitor when a through hole (via hole) is formed in the circuit board or the like. Therefore, the portion of the terminal electrode that has been irradiated with the laser beam may be removed by the laser beam. However, when the thickness of the first plating layer is larger than the thickness of the second plating layer, the thickness of the first plating layer can be sufficiently ensured. Therefore, since the first plating layer is only partially removed by the laser beam, it is possible to reduce the possibility of damage inside the element body. Note that the thicker the first plating layer, the higher the internal stress generated in the first plating layer itself. However, in the multilayer capacitor according to one aspect of the present invention, since the second plating layer having a density lower than that of the first plating layer is present, internal stress generated in the first plating layer itself is reduced to the second level. It is possible to relax in the plating layer.
第2のめっき層の厚さは、第1のめっき層の厚さよりも大きくてもよい。この場合、応力を緩和する機能を有する第2のめっき層の厚さを十分に確保できる。そのため、素体に応力がより作用し難くなるので、素体にクラック(欠けや割れなど)が発生することをいっそう抑制できる。   The thickness of the second plating layer may be larger than the thickness of the first plating layer. In this case, it is possible to sufficiently secure the thickness of the second plating layer having a function of relaxing stress. For this reason, stress is less likely to act on the element body, so that it is possible to further suppress the occurrence of cracks (chips, cracks, etc.) in the element body.
本発明によれば、素体へのクラック発生を抑制することが可能な積層コンデンサを提供できる。   ADVANTAGE OF THE INVENTION According to this invention, the multilayer capacitor which can suppress generation | occurrence | production of the crack to an element body can be provided.
図1は、本実施形態に係る積層コンデンサを示す斜視図である。FIG. 1 is a perspective view showing the multilayer capacitor in accordance with this embodiment. 図2は、図1のII−II線断面図である。2 is a cross-sectional view taken along line II-II in FIG. 図3は、図1のIII−III線断面図である。3 is a cross-sectional view taken along line III-III in FIG. 図4は、素体を示す分解斜視図である。FIG. 4 is an exploded perspective view showing the element body. 図5は、本実施形態に係る積層コンデンサが基板に実装された実装構造を示す断面図である。FIG. 5 is a cross-sectional view showing a mounting structure in which the multilayer capacitor according to the present embodiment is mounted on a substrate.
本発明の実施形態について図面を参照して説明するが、以下の本実施形態は、本発明を説明するための例示であり、本発明を以下の内容に限定する趣旨ではない。説明において、同一要素又は同一機能を有する要素には同一符号を用いることとし、重複する説明は省略する。   Embodiments of the present invention will be described with reference to the drawings. However, the following embodiments are exemplifications for explaining the present invention and are not intended to limit the present invention to the following contents. In the description, the same reference numerals are used for the same elements or elements having the same function, and redundant description is omitted.
積層コンデンサ1は、図1〜図3に示されるように、略直方体形状の素体10と、素体10内に配置された内部電極12A,12Bと、素体10の両端部側に配置された端子電極14A,14Bとを備える。積層コンデンサ1の長さLは例えば0.4mm〜1.6mm程度に設定でき、積層コンデンサ1の幅Wは例えば0.2mm〜0.8mm程度に設定でき、積層コンデンサ1の高さHは例えば0.10mm〜0.35mm程度に設定できる。   As shown in FIGS. 1 to 3, the multilayer capacitor 1 is arranged on a substantially rectangular parallelepiped element body 10, internal electrodes 12 </ b> A and 12 </ b> B arranged in the element body 10, and both end portions of the element body 10. Terminal electrodes 14A and 14B. The length L of the multilayer capacitor 1 can be set to, for example, about 0.4 mm to 1.6 mm, the width W of the multilayer capacitor 1 can be set to, for example, about 0.2 mm to 0.8 mm, and the height H of the multilayer capacitor 1 is, for example, It can be set to about 0.10 mm to 0.35 mm.
素体10は、互いに対向して略平行に延びると共に素体10の長手方向に対して略直交する一対の端面10a,10bと、互いに対向して略平行に延びると共に素体10の高さ方向に対して略直交する一対の主面10c,10dと、互いに対向して略平行に延びると共に素体10の幅方向に対して略直交する一対の側面10e,10fとを有する。   The element body 10 is opposed to each other and extends substantially in parallel with each other, and a pair of end faces 10a and 10b that are substantially orthogonal to the longitudinal direction of the element body 10, and is opposed to each other and extends substantially in parallel with each other. And a pair of side surfaces 10e and 10f extending substantially parallel to each other and substantially orthogonal to the width direction of the element body 10.
一対の主面10c,10dの短辺はそれぞれ、一対の端面10a,10bの長辺と接続されている。そのため、一対の主面10c,10dは、一対の端面10a,10b同士を連結している。一対の側面10e,10fの長辺はそれぞれ、一対の主面10c,10dの長辺と接続されている。そのため、一対の側面10e,10fは、一対の主面10c,10d同士を連結している。一対の側面10e,10fの短辺はそれぞれ、一対の端面10a,10bの短辺と接続されている。そのため、一対の側面10e,10fは、一対の端面10a,10b同士を連結している。   The short sides of the pair of main surfaces 10c and 10d are connected to the long sides of the pair of end surfaces 10a and 10b, respectively. Therefore, the pair of main surfaces 10c and 10d connects the pair of end surfaces 10a and 10b. The long sides of the pair of side surfaces 10e and 10f are connected to the long sides of the pair of main surfaces 10c and 10d, respectively. Therefore, the pair of side surfaces 10e and 10f connects the pair of main surfaces 10c and 10d to each other. The short sides of the pair of side surfaces 10e and 10f are connected to the short sides of the pair of end surfaces 10a and 10b, respectively. Therefore, the pair of side surfaces 10e and 10f connects the pair of end surfaces 10a and 10b to each other.
積層コンデンサ1は、いわゆる低背型コンデンサとして構成されている。すなわち、素体10において、主面10c,10dの間の寸法(素体10の高さ)h(図2参照)は、端面10a,10bの間の寸法(素体10の長さ)l(図2参照)、及び側面10e,10fの間の寸法(素体10の幅)w(図3参照)よりも小さい。   The multilayer capacitor 1 is configured as a so-called low profile capacitor. That is, in the element body 10, the dimension between the main surfaces 10c and 10d (height of the element body 10) h (see FIG. 2) is the dimension between the end faces 10a and 10b (the length of the element body 10) l ( 2) and the dimension between the side surfaces 10e and 10f (the width of the element body 10) w (see FIG. 3).
素体10は、図4に示されるように、複数の長方形板状の誘電体層16と、複数の(本実施形態では3つの)内部電極12Aと、複数の(本実施形態では3つの)内部電極12Bとが所定の順序に従って積層された積層体である。内部電極12Aと内部電極12Bとは、誘電体層16の積層方向(主面10c,10dの対向方向)(以下、「積層方向」という。)において、交互に並ぶように素体10内に配置されている。内部電極12Aと内部電極12Bとは、少なくとも一層の誘電体層16を挟むように対向配置されている。実際の積層コンデンサ1では、複数の誘電体層16は、互いの間の境界が視認できない程度に一体化されている。   As shown in FIG. 4, the element body 10 includes a plurality of rectangular plate-like dielectric layers 16, a plurality of (three in this embodiment) internal electrodes 12 </ b> A, and a plurality (three in this embodiment). The internal electrode 12B is a stacked body that is stacked in a predetermined order. The internal electrodes 12A and the internal electrodes 12B are arranged in the element body 10 so as to be alternately arranged in the stacking direction of the dielectric layers 16 (opposite directions of the main surfaces 10c and 10d) (hereinafter referred to as “stacking direction”). Has been. The internal electrode 12A and the internal electrode 12B are disposed so as to face each other with at least one dielectric layer 16 interposed therebetween. In the actual multilayer capacitor 1, the plurality of dielectric layers 16 are integrated to such an extent that the boundary between them cannot be visually recognized.
内部電極12Aは、矩形状を呈しており、主電極部12Aと、引き出し部12Aとを有している。内部電極12Bは、矩形状を呈しており、主電極部12Bと、引き出し部12Bとを有している。主電極部12A,12A同士は、積層方向から見て重なり合っている。 Internal electrodes 12A is a rectangular shape, has a main electrode portion 12A 1, and lead portions 12A 2. Internal electrode 12B is a rectangular shape, has a main electrode portion 12B 1, and lead portions 12B 2. The main electrode portions 12A 1 and 12A 1 overlap each other when viewed from the stacking direction.
引き出し部12Aは、主電極部12Aのうち端面10a側の端部から端面10aにかけて延びている。引出部12Aの端面10a側の端部は、端面10aに露出しており、端子電極14A(後述する焼付電極層14A)と接続されている。そのため、内部電極12Aと端子電極14Aとは、電気的に接続されている。 Drawer unit 12A 2 extends toward the end surface 10a from the end portion of the end surface 10a side of the main electrode portion 12A 1. End of the end face 10a side of the lead-out portion 12A 2 is exposed to the end surface 10a, and is connected to the terminal electrode 14A (baked electrode layer 14A 1 to be described later). Therefore, the internal electrode 12A and the terminal electrode 14A are electrically connected.
引き出し部12Bは、主電極部12Bのうち端面10b側の端部から端面10bにかけて延びている。引出部12Bの端面10b側の端部は、端面10bに露出しており、端子電極14B(後述する焼付電極層14B)と接続されている。そのため、内部電極12Bと端子電極14Bとは、電気的に接続されている。 Drawer unit 12B 2 extends toward the end face 10b from the end portion of the end surface 10b side of the main electrode portion 12B 1. End of the end face 10b side of the lead portion 12B 2 is exposed to the end face 10b, and is connected to the terminal electrode 14B (baked electrode layer 14B 1 to be described later). Therefore, the internal electrode 12B and the terminal electrode 14B are electrically connected.
図2に示されるように、素体10の最上部(主面10cに最も近い位置)に配置された内部電極12Aと、素体10の最下部(主面10dに最も近い位置)に配置された内部電極12Bとの間の内層寸法を「D1」とする。素体10の主面10cを構成する誘電体層16の最上層(保護層)と、素体10の最上部に配置された内部電極12Aとの間の外層寸法を「D2」とする。素体10における外層寸法D2の部分は、複数の誘電体層16が積層されて構成されている。素体10の主面10dを構成する誘電体層16の最下層と、素体10の最下部に配置された内部電極12Bとの間の外層寸法を「D3」とする。素体10における外層寸法D3の部分は、複数の誘電体層16が積層されて構成されている。   As shown in FIG. 2, the internal electrode 12A is disposed at the uppermost portion (position closest to the main surface 10c) of the element body 10, and is disposed at the lowermost portion (position closest to the main surface 10d) of the element body 10. The inner layer dimension between the internal electrodes 12B is “D1”. The outer layer dimension between the uppermost layer (protective layer) of the dielectric layer 16 constituting the main surface 10c of the element body 10 and the internal electrode 12A disposed on the uppermost part of the element body 10 is defined as “D2”. A portion having the outer layer dimension D <b> 2 in the element body 10 is configured by laminating a plurality of dielectric layers 16. The outer layer dimension between the lowermost layer of the dielectric layer 16 constituting the main surface 10d of the element body 10 and the internal electrode 12B disposed at the lowermost part of the element body 10 is “D3”. A portion having the outer layer dimension D3 in the element body 10 is configured by laminating a plurality of dielectric layers 16.
素体10においては、内層寸法D1と外層寸法D2とが略等しく、内層寸法D1と外層寸法D3とが略等しい。すなわち、内層の厚みと、それを挟む一対の外層の厚みとは略等しい。ここでいう「略等しい」とは、例えば5μm程度の誤差を含む。   In the element body 10, the inner layer dimension D1 and the outer layer dimension D2 are substantially equal, and the inner layer dimension D1 and the outer layer dimension D3 are approximately equal. That is, the thickness of the inner layer is approximately equal to the thickness of the pair of outer layers sandwiching it. Here, “substantially equal” includes an error of about 5 μm, for example.
端子電極14Aは、図1〜図3に示されるように、端面10aの全体と、主面10c,10d及び側面10e,10fのうち端面10a側の領域とを覆っている。端子電極14Aは、素体10の表面上に配置されており、端面10aから主面10c,10d及び側面10e,10fにわたって素体10の稜部を回り込むように連続して延びている。端子電極14Aは、焼付電極層14Aと、内側めっき層14Aと、外側めっき層14Aとを有する。 As shown in FIGS. 1 to 3, the terminal electrode 14 </ b> A covers the entire end surface 10 a and a region on the end surface 10 a side of the main surfaces 10 c and 10 d and the side surfaces 10 e and 10 f. The terminal electrode 14A is disposed on the surface of the element body 10, and continuously extends from the end face 10a to the main surfaces 10c and 10d and the side faces 10e and 10f so as to go around the ridges of the element body 10. Terminal electrodes 14A includes a baked electrode layer 14A 1, and inner plating layer 14A 2, and an outer plating layer 14A 3.
端子電極14Bは、図1〜図3に示されるように、端面10bの全体と、主面10c,10d及び側面10e,10fのうち端面10b側の領域とを覆っている。端子電極14Bは、素体10の表面上に配置されており、端面10bから主面10c,10d及び側面10e,10fにわたって素体10の稜部を回り込むように連続して延びている。端子電極14Bは、焼付電極層14Bと、内側めっき層14Bと、外側めっき層14Bとを有する。 The terminal electrode 14B covers the entire end surface 10b and the region on the end surface 10b side of the main surfaces 10c and 10d and the side surfaces 10e and 10f, as shown in FIGS. The terminal electrode 14B is disposed on the surface of the element body 10, and continuously extends so as to wrap around the ridges of the element body 10 from the end face 10b to the main surfaces 10c, 10d and the side faces 10e, 10f. Terminal electrodes 14B includes a baked electrode layer 14B 1, the inner plating layer 14B 2, and an outer plating layer 14B 3.
本実施形態において、図2に示されるように、端面10a,10bの対向方向における端子電極14Aの長さX1は、端面10a,10bの対向方向における端子電極14A,14Bの離間距離Yよりも大きくてもよい。本実施形態において、図2に示されるように、端面10a,10bの対向方向における端子電極14Bの長さX2は、端面10a,10bの対向方向における端子電極14A,14Bの離間距離Yよりも大きくてもよい。   In the present embodiment, as shown in FIG. 2, the length X1 of the terminal electrode 14A in the facing direction of the end faces 10a, 10b is larger than the separation distance Y of the terminal electrodes 14A, 14B in the facing direction of the end faces 10a, 10b. May be. In the present embodiment, as shown in FIG. 2, the length X2 of the terminal electrode 14B in the facing direction of the end faces 10a and 10b is larger than the separation distance Y of the terminal electrodes 14A and 14B in the facing direction of the end faces 10a and 10b. May be.
焼付電極層14A,14Bは、素体10の表面に直接接するように素体10の表面上に配置されている。焼付電極層14A,14Bは、金属(例えば、Cu、Ni、Ag、Pd、Au、又はPtなど)と、ガラス成分(例えば、ホウケイ酸ガラスなど)とを含有する導電性ペーストを、例えばディップ工法により素体10に付与し、その導電性ペーストを所定の温度で焼き付けることで形成される。焼付電極層14A,14Bのガラス成分の含有比率は、例えば5〜10%である。すなわち、焼付電極層14A,14Bは、Cu、Ni、Ag、Pd、Au又はPtを主成分として含んでいる。焼付電極層14A,14Bの厚さは、例えば1μm以上である。 The baked electrode layers 14 </ b> A 1 and 14 </ b> B 1 are disposed on the surface of the element body 10 so as to be in direct contact with the surface of the element body 10. The baked electrode layers 14A 1 and 14B 1 are made of a conductive paste containing a metal (for example, Cu, Ni, Ag, Pd, Au, or Pt) and a glass component (for example, borosilicate glass), for example. It is formed by applying to the element body 10 by a dip method and baking the conductive paste at a predetermined temperature. The content ratio of the glass components of the baked electrode layers 14A 1 and 14B 1 is, for example, 5 to 10%. That is, the baked electrode layers 14A 1 and 14B 1 contain Cu, Ni, Ag, Pd, Au, or Pt as a main component. The thickness of the baked electrode layers 14A 1 and 14B 1 is, for example, 1 μm or more.
内側めっき層14Aは、焼付電極層14Aの表面全体を覆うように焼付電極層14Aの表面上に配置されている。内側めっき層14Bは、焼付電極層14Bの表面全体を覆うように焼付電極層14Bの表面上に配置されている。内側めっき層14A,14Bは、Cu、Ag、Au、Ni、Pd又はSnを主成分として含んでいる。内側めっき層14A,14Bの厚さは、例えば1μm以上である。 Inner plating layer 14A 2 is disposed on the surface of the sintered electrode layers 14A 1 so as to cover the entire surface of the sintered electrode layers 14A 1. Inner plating layer 14B 2 is disposed on the surface of the sintered electrode layers 14B 1 so as to cover the entire surface of the sintered electrode layers 14B 1. The inner plating layers 14A 2 and 14B 2 contain Cu, Ag, Au, Ni, Pd, or Sn as a main component. The thickness of the inner plating layers 14A 2 and 14B 2 is, for example, 1 μm or more.
外側めっき層14Aは、内側めっき層14Aの表面全体を覆うように内側めっき層14Aの表面上に配置されている。外側めっき層14Bは、内側めっき層14Bの表面全体を覆うように内側めっき層14Bの表面上に配置されている。外側めっき層14A,14Bはそれぞれ、本実施形態において端子電極14A,14Bの最外表面を構成している。外側めっき層14A,14Bは、Cu、Ag、Au、Ni、Pd又はSnを主成分として含んでいる。外側めっき層14A,14Bの厚さは、例えば5μm以上である。 Outer plating layer 14A 3 is disposed on the surface of the inner plating layer 14A 2 so as to cover the entire surface of the inner plating layer 14A 2. Outer plating layer 14B 3 is disposed on the surface of the inner plating layer 14B 2 so as to cover the entire surface of the inner plating layer 14B 2. The outer plating layers 14A 3 and 14B 3 form the outermost surfaces of the terminal electrodes 14A and 14B, respectively, in the present embodiment. The outer plating layers 14A 3 and 14B 3 contain Cu, Ag, Au, Ni, Pd, or Sn as a main component. The thickness of the outer plating layers 14A 3 and 14B 3 is, for example, 5 μm or more.
内側めっき層14A,14Bの密度は、外側めっき層14A,14Bの密度よりも小さい。内側めっき層14A,14B及び外側めっき層14A,14Bの密度は、めっき層を構成する金属粒子の粒径を製造条件によって変化させることで制御可能である。具体的には、めっき層を構成する金属粒子の粒径が小さいほど、めっき層内に空孔ができやすく、めっき層の密度が低くなる傾向にあり、めっき層を構成する金属材料の粒径が大きいほど、めっき層内に空孔ができにくく、めっき層の密度が高くなる傾向にある。例えば、外側めっき層14A,14Bを構成する金属粒子の粒径が、内側めっき層14A,14Bを構成する金属粒子の粒径の5倍以上の大きさとなるように、各めっき層の製造条件を設定してもよい。その結果、内側めっき層14A,14Bの空孔率が10%以上となると共に、外側めっき層14A,14Bの空孔率が10%未満となっていてもよい。ここで、「空孔率」とは、各めっき層14A,14B,14A,14Bの任意断面において、各めっき層14A,14B,14A,14Bの断面積に対する空孔の面積の割合を意味する。 The density of the inner plating layers 14A 2 and 14B 2 is smaller than the density of the outer plating layers 14A 3 and 14B 3 . The densities of the inner plating layers 14A 2 and 14B 2 and the outer plating layers 14A 3 and 14B 3 can be controlled by changing the particle diameter of the metal particles constituting the plating layer according to the manufacturing conditions. Specifically, the smaller the particle size of the metal particles constituting the plating layer, the easier the formation of pores in the plating layer and the lower the density of the plating layer. The particle size of the metal material constituting the plating layer The larger the is, the more difficult it is to form pores in the plating layer, and the density of the plating layer tends to increase. For example, each plating layer is formed such that the particle size of the metal particles constituting the outer plating layers 14A 3 and 14B 3 is not less than five times the particle size of the metal particles constituting the inner plating layers 14A 2 and 14B 2. The manufacturing conditions may be set. As a result, the porosity of the inner plating layers 14A 2 and 14B 2 may be 10% or more, and the porosity of the outer plating layers 14A 3 and 14B 3 may be less than 10%. Here, the “porosity” means a void with respect to a cross-sectional area of each plating layer 14A 2 , 14B 2 , 14A 3 , 14B 3 in an arbitrary cross section of each plating layer 14A 2 , 14B 2 , 14A 3 , 14B 3. Means the percentage of the area.
続いて、図5を参照して、積層コンデンサ1の実装構造について説明する。図5に示されるように、積層コンデンサ1は、基板(回路基板)100に埋め込まれて実装される。基板100は、絶縁性の複数の樹脂シート102が積層されて構成されている。基板100は、基板100の表面に形成された電極104A,104Bと、ビア導体106A,106Bとを備える。ビア導体106A,106Bはそれぞれ、基板100に形成された各貫通孔(ビアホール)108A,108B内に充填されている。   Next, the mounting structure of the multilayer capacitor 1 will be described with reference to FIG. As shown in FIG. 5, the multilayer capacitor 1 is embedded and mounted in a substrate (circuit board) 100. The substrate 100 is configured by laminating a plurality of insulating resin sheets 102. The substrate 100 includes electrodes 104A and 104B formed on the surface of the substrate 100 and via conductors 106A and 106B. The via conductors 106A and 106B are filled in the through holes (via holes) 108A and 108B formed in the substrate 100, respectively.
ビア導体106Aのうち基板100の内部側の端部は、端子電極14Aのうち主面10c,10d上に配置されている部分と接続されている。ビア導体106Aのうち基板100の外部側の端部は、電極104Aと接続されている。ビア導体106Bのうち基板100の内部側の端部は、端子電極14Bのうち主面10c,10d上に配置されている部分と接続されている。ビア導体106Bのうち基板100の外部側の端部は、電極104Bと接続されている。   An end of the via conductor 106A on the inner side of the substrate 100 is connected to a portion of the terminal electrode 14A disposed on the main surfaces 10c and 10d. An end of the via conductor 106A on the outer side of the substrate 100 is connected to the electrode 104A. An end of the via conductor 106B on the inner side of the substrate 100 is connected to a portion of the terminal electrode 14B disposed on the main surfaces 10c and 10d. An end of the via conductor 106B on the outer side of the substrate 100 is connected to the electrode 104B.
続いて、積層コンデンサ1を基板100に埋め込む方法について説明する。まず、積層コンデンサ1を内部に配置した状態で複数の樹脂シート102を積層して、積層コンデンサ1を基板100の内部に埋め込む。次に、レーザビームを用いて基板100に貫通孔108A,108Bを形成する。このとき、レーザビームは、端子電極14A,14Bのうち主面10c,10d上に配置されている部分に向けて照射される。その結果、貫通孔108A,108Bを介して、端子電極14A,14Bが外部に露出する。   Next, a method for embedding the multilayer capacitor 1 in the substrate 100 will be described. First, a plurality of resin sheets 102 are laminated with the multilayer capacitor 1 disposed therein, and the multilayer capacitor 1 is embedded in the substrate 100. Next, through holes 108A and 108B are formed in the substrate 100 using a laser beam. At this time, the laser beam is emitted toward the portions of the terminal electrodes 14A and 14B that are disposed on the main surfaces 10c and 10d. As a result, the terminal electrodes 14A and 14B are exposed to the outside through the through holes 108A and 108B.
次に、無電解めっきにより、貫通孔108A,108B内にそれぞれビア導体106A,106Bを形成する。次に、ビア導体106Aと接続されるように、基板100上に電極104Aを形成すると共に、ビア導体106Bと接続されるように、基板100上に電極104Bを形成する。こうして、積層コンデンサ1の内部電極12A,12Bがそれぞれ、端子電極14A,14B及びビア導体106A,106Bを介して、電極104A,104Bと電気的に接続される。   Next, via conductors 106A and 106B are formed in the through holes 108A and 108B, respectively, by electroless plating. Next, an electrode 104A is formed on the substrate 100 so as to be connected to the via conductor 106A, and an electrode 104B is formed on the substrate 100 so as to be connected to the via conductor 106B. Thus, the internal electrodes 12A and 12B of the multilayer capacitor 1 are electrically connected to the electrodes 104A and 104B through the terminal electrodes 14A and 14B and the via conductors 106A and 106B, respectively.
以上のような本実施形態では、端子電極14A,14Bがそれぞれ外側めっき層14A,14Bと内側めっき層14A,14Bとを有し、内側めっき層14A,14Bの密度が外側めっき層14A,14Bの密度よりも小さい。内側めっき層14A,14Bには外側めっき層14A,14Bよりも多くの空孔が含まれているので、内側めっき層14A,14Bに作用する応力は空孔の存在によって緩和される。そのため、外側めっき層14A,14Bの形成過程で外側めっき層14A,14B自身に内部応力が生じたり、積層コンデンサ1に外部から力が加わるなどにより外側めっき層14A,14Bに応力が作用すると、それらの応力は、内側めっき層14A,14Bにおいて緩和され、素体10に作用し難くなる。その結果、素体10にクラック(欠けや割れなど)が発生することを抑制できる。 In the present embodiment as described above, the terminal electrodes 14A and 14B have the outer plating layers 14A 3 and 14B 3 and the inner plating layers 14A 2 and 14B 2 , respectively, and the inner plating layers 14A 2 and 14B 2 have a density of the outer side. It is smaller than the density of the plating layers 14A 3 and 14B 3 . Since the inner plating layers 14A 2 and 14B 2 contain more holes than the outer plating layers 14A 3 and 14B 3 , the stress acting on the inner plating layers 14A 2 and 14B 2 is relieved by the presence of the holes. Is done. Therefore, internal stress or occur outside the plating layer 14A 3, 14B 3 itself during formation of the outer plating layer 14A 3, 14B 3, the outer plated layer 14A 3, 14B 3 due external force is applied to the multilayer capacitor 1 When stress acts, these stresses are relaxed in the inner plating layers 14A 2 and 14B 2 , and it becomes difficult to act on the element body 10. As a result, it is possible to suppress the occurrence of cracks (chips, cracks, etc.) in the element body 10.
本実施形態では、外側めっき層14A,14BがCu、Ag、Au、Ni、Pd又はSnを主成分として含んでいる。そのため、積層コンデンサ1を基板100に実装する際に、積層コンデンサ1の端子電極14A,14Bと、基板100のビア導体106A,106Bとの接続が良好に行える。しかも、外側めっき層14A,14Bは、内側めっき層14A,14Bよりも密度が高く表面がより緻密であるので、積層コンデンサ1の基板100への実装時に、積層コンデンサ1の端子電極14A,14Bと基板100のビア導体106A,106Bとがより強固に固着しやすい。従って、積層コンデンサ1をより確実に基板100に実装することが可能となる。 In the present embodiment, the outer plating layers 14A 3 and 14B 3 contain Cu, Ag, Au, Ni, Pd, or Sn as a main component. Therefore, when the multilayer capacitor 1 is mounted on the substrate 100, the terminal electrodes 14A and 14B of the multilayer capacitor 1 and the via conductors 106A and 106B of the substrate 100 can be satisfactorily connected. Moreover, since the outer plating layers 14A 3 and 14B 3 have a higher density and a denser surface than the inner plating layers 14A 2 and 14B 2 , the terminal electrodes of the multilayer capacitor 1 are mounted when the multilayer capacitor 1 is mounted on the substrate 100. 14A and 14B and the via conductors 106A and 106B of the substrate 100 can be more firmly fixed. Therefore, the multilayer capacitor 1 can be more reliably mounted on the substrate 100.
本実施形態では、主面10c,10dの間の寸法(素体10の高さ)hが、端面10a,10bの間の寸法(素体10の長さ)l、及び側面10e,10fの間の寸法(素体10の幅)wよりも小さい。そのため、積層コンデンサ1は、いわゆる低背型の積層コンデンサとして構成される。加えて、端子電極14A,14Bが主面10c,10dに配置されているので、積層コンデンサ1を基板100に内蔵した状態で実装することが可能となる。ところで、積層コンデンサ1を基板100に埋め込む実装構造においては、積層コンデンサ1の端子電極14A,14Bが露出するようにレーザビームを用いて基板100に貫通孔(ビアホール)108A,108Bを形成し、貫通孔108A,108B内にそれぞれビア導体106A,106Bを埋め込むことにより、ビア導体106A,106Bと積層コンデンサ1の端子電極14A,14Bとが接続される。このような実装構造では、端子電極14A,14Bの電流ループ距離が短くなるため、等価直列インダクタンス(ESL)を低くできる。   In the present embodiment, the dimension (height of the element body 10) h between the main surfaces 10c and 10d is the dimension between the end faces 10a and 10b (the length of the element body 10) l and the side surfaces 10e and 10f. Is smaller than the dimension (the width of the element body 10) w. Therefore, the multilayer capacitor 1 is configured as a so-called low profile multilayer capacitor. In addition, since the terminal electrodes 14A and 14B are disposed on the main surfaces 10c and 10d, the multilayer capacitor 1 can be mounted in a state of being built in the substrate 100. By the way, in the mounting structure in which the multilayer capacitor 1 is embedded in the substrate 100, through holes (via holes) 108A and 108B are formed in the substrate 100 using a laser beam so that the terminal electrodes 14A and 14B of the multilayer capacitor 1 are exposed, and the through holes are formed. The via conductors 106A and 106B are connected to the terminal electrodes 14A and 14B of the multilayer capacitor 1 by embedding the via conductors 106A and 106B in the holes 108A and 108B, respectively. In such a mounting structure, since the current loop distance between the terminal electrodes 14A and 14B is shortened, the equivalent series inductance (ESL) can be lowered.
本実施形態では、長さX1,X2が離間距離Yよりも大きい。この場合、主面10c,10d上において端子電極14A,14Bの面積が十分に確保される。そのため、積層コンデンサ1を基板100に実装する際に、端子電極14A,14Bとビア導体106A,106Bとの接触領域を大きくできる。その結果、端子電極14A,14Bとビア導体106A,106Bとの接続をより確実に行うことができる。   In the present embodiment, the lengths X1 and X2 are larger than the separation distance Y. In this case, the areas of the terminal electrodes 14A and 14B are sufficiently ensured on the main surfaces 10c and 10d. Therefore, when the multilayer capacitor 1 is mounted on the substrate 100, the contact area between the terminal electrodes 14A and 14B and the via conductors 106A and 106B can be increased. As a result, the terminal electrodes 14A and 14B and the via conductors 106A and 106B can be more reliably connected.
本実施形態では、素体10において、内層寸法D1と外層寸法D2とが略等しく、内層寸法D1と外層寸法D3とが略等しい。この場合、外層寸法D2,D3が比較的大きくなるので、外層部分が保護層として機能する。従って、積層コンデンサ1において構造欠陥の発生を抑制できる。加えて、このような積層コンデンサ1では、静電容量を確保できる。   In the present embodiment, in the element body 10, the inner layer dimension D1 and the outer layer dimension D2 are substantially equal, and the inner layer dimension D1 and the outer layer dimension D3 are approximately equal. In this case, since the outer layer dimensions D2 and D3 are relatively large, the outer layer portion functions as a protective layer. Therefore, occurrence of structural defects in the multilayer capacitor 1 can be suppressed. In addition, such a multilayer capacitor 1 can ensure electrostatic capacity.
本実施形態では、端子電極14A,14Bがそれぞれ、素体10の表面に配置された焼付電極層14A,14Bを有している。そのため、素体10の表面に位置する焼付電極層14A,14Bに内部電極12A,12Bが接続されるので、端子電極14A,14Bと内部電極12A,12Bとをより確実に接続することができる。 In the present embodiment, the terminal electrodes 14A and 14B have the baked electrode layers 14A 1 and 14B 1 disposed on the surface of the element body 10, respectively. Therefore, since the internal electrodes 12A and 12B are connected to the baked electrode layers 14A 1 and 14B 1 located on the surface of the element body 10, the terminal electrodes 14A and 14B and the internal electrodes 12A and 12B can be more reliably connected. it can.
以上、本発明の実施形態について詳細に説明したが、本発明は上記した実施形態に限定されるものではない。例えば、外側めっき層14A,14B及び内側めっき層14A,14Bは共にCuを主成分として含んでいてもよい。この場合、外側めっき層14A,14B及び内側めっき層14A,14Bが共に同じ材料を主成分として含んでいるので、両者の界面における固着性を高めることができる。 As mentioned above, although embodiment of this invention was described in detail, this invention is not limited to above-described embodiment. For example, the outer plating layers 14A 3 and 14B 3 and the inner plating layers 14A 2 and 14B 2 may both contain Cu as a main component. In this case, since the outer plating layers 14A 3 and 14B 3 and the inner plating layers 14A 2 and 14B 2 both contain the same material as a main component, the adhesion at the interface between them can be improved.
焼付電極層14A,14B、内側めっき層14A,14B、及び外側めっき層14A,14Bがいずれも、Cuを主成分として含んでいてもよい。この場合、焼付電極層14A,14B、外側めっき層14A,14B及び内側めっき層14A,14Bがいずれも同じ材料を主成分として含んでいるので、焼付電極層14A,14Bと内側めっき層14A,14Bとの界面、及び内側めっき層14A,14Bと外側めっき層14A,14Bとの界面における固着性を高めることができる。 The baking electrode layers 14A 1 and 14B 1 , the inner plating layers 14A 2 and 14B 2 , and the outer plating layers 14A 3 and 14B 3 may all contain Cu as a main component. In this case, the baking electrode layers 14A 1 and 14B 1 , the outer plating layers 14A 3 and 14B 3 and the inner plating layers 14A 2 and 14B 2 all contain the same material as the main component, and therefore the baking electrode layers 14A 1 and 14B. the interface between the 1 and the inner plating layer 14A 2, 14B 2, and can increase the adherence at the interface between the inner coating layer 14A 2, 14B 2 and the outer plating layer 14A 1, 14B 1.
内側めっき層14A,14BはNiを主成分として含んでおり、外側めっき層14A,14BはCuを主成分として含んでいてもよい。この場合、300K雰囲気におけるCuの熱伝導率は401W/(m・K)程度であり、300K雰囲気におけるNiの熱伝導率は90.9W/(m・K)程度である。つまりNiはCuよりも熱伝導率が低いので、積層コンデンサ1に熱が加わった場合でも、外側めっき層14A,14Bから素体への熱伝達が内側めっき層14A,14Bによって妨げられる。そのため、積層コンデンサ1の基板100への実装に際して積層コンデンサ1に熱が加わった場合でも、当該熱によって素体10の内部に生じうる損傷(ダメージ)を低減することができる。特に、積層コンデンサ1を基板100に埋め込む実装構造においては、基板100に貫通孔(ビアホール)108A,108Bを形成する際に、レーザビームが積層コンデンサ1の端子電極14A,14Bに照射される。そのため、積層コンデンサ1の端子電極14A,14Bに大きな熱が作用する傾向にある。しかしながら、内側めっき層14A,14BがNiを主成分として含んでおり、外側めっき層14A,14BがCuを主成分として含んでいる場合には、レーザビームによって素体10の内部に生じうる損傷(ダメージ)も低減することができる。なお、Niの他にCuよりも熱伝導率が低い金属としては、PdやSnが挙げられる。300K雰囲気におけるPdの熱伝導率は71.8W/(m・K)程度であり、300K雰囲気におけるSnの熱伝導率は66.8W/(m・K)程度である。 The inner plating layers 14A 2 and 14B 2 may contain Ni as a main component, and the outer plating layers 14A 3 and 14B 3 may contain Cu as a main component. In this case, the thermal conductivity of Cu in the 300K atmosphere is about 401 W / (m · K), and the thermal conductivity of Ni in the 300K atmosphere is about 90.9 W / (m · K). That is, since Ni has a lower thermal conductivity than Cu, even when heat is applied to the multilayer capacitor 1, heat transfer from the outer plating layers 14A 3 and 14B 3 to the element body is hindered by the inner plating layers 14A 2 and 14B 2 . It is done. Therefore, even when heat is applied to the multilayer capacitor 1 when the multilayer capacitor 1 is mounted on the substrate 100, damage (damage) that can occur inside the element body 10 due to the heat can be reduced. In particular, in a mounting structure in which the multilayer capacitor 1 is embedded in the substrate 100, when the through holes (via holes) 108 </ b> A and 108 </ b> B are formed in the substrate 100, the laser beam is applied to the terminal electrodes 14 </ b> A and 14 </ b> B of the multilayer capacitor 1. Therefore, large heat tends to act on the terminal electrodes 14 </ b> A and 14 </ b> B of the multilayer capacitor 1. However, when the inner plating layers 14A 2 and 14B 2 contain Ni as a main component and the outer plating layers 14A 3 and 14B 3 contain Cu as a main component, the inside of the element body 10 is irradiated by a laser beam. Possible damage (damage) can also be reduced. In addition to Ni, examples of the metal having a lower thermal conductivity than Cu include Pd and Sn. The thermal conductivity of Pd in the 300K atmosphere is about 71.8 W / (m · K), and the thermal conductivity of Sn in the 300K atmosphere is about 66.8 W / (m · K).
外側めっき層14A,14Bの厚さは、内側めっき層14A,14Bの厚さよりも大きくてもよい。積層コンデンサ1を基板100に埋め込む実装構造においては、基板100に貫通孔(ビアホール)108A,108Bを形成する際に、レーザビームが積層コンデンサ1の端子電極14A,14Bに照射される。そのため、端子電極14A,14Bのうちレーザビームが照射された部分が、レーザビームにより除去される場合がある。しかしながら、外側めっき層14A,14Bの厚さが内側めっき層14A,14Bの厚さよりも大きい場合には、外側めっき層14A,14Bの厚さを十分に確保できる。そのため、レーザビームによって外側めっき層14A,14Bが部分的に除去されるのに止まるので、素体10の内部に損傷が生ずる虞を低減することができる。なお、外側めっき層14A,14Bが厚いほど、外側めっき層14A,14B自身に生ずる内部応力が高くなる傾向にある。しかしながら、本実施形態に係る積層コンデンサ1では、外側めっき層14A,14Bよりも密度が小さい内側めっき層14A,14Bが存在しているため、外側めっき層14A,14B自身に生ずる内部応力を内側めっき層14A,14Bにおいて緩和することが可能である。 The thicknesses of the outer plating layers 14A 3 and 14B 3 may be larger than the thicknesses of the inner plating layers 14A 2 and 14B 2 . In the mounting structure in which the multilayer capacitor 1 is embedded in the substrate 100, when the through holes (via holes) 108 </ b> A and 108 </ b> B are formed in the substrate 100, the laser beam is applied to the terminal electrodes 14 </ b> A and 14 </ b> B of the multilayer capacitor 1. For this reason, portions of the terminal electrodes 14A and 14B irradiated with the laser beam may be removed by the laser beam. However, when the thickness of the outer plating layers 14A 3 and 14B 3 is larger than the thickness of the inner plating layers 14A 2 and 14B 2 , the thickness of the outer plating layers 14A 3 and 14B 3 can be sufficiently secured. Therefore, since the outer plating layers 14A 3 and 14B 3 are only partially removed by the laser beam, it is possible to reduce the possibility of damage inside the element body 10. Note that the thicker the outer plating layer 14A 3, 14B 3, there is a tendency that the internal stress generated in the outer plating layer 14A 3, 14B 3 itself increases. However, in the multilayer capacitor 1 according to the present embodiment, the inner plating layers 14A 2 and 14B 2 having a density lower than that of the outer plating layers 14A 3 and 14B 3 exist, and therefore the outer plating layers 14A 3 and 14B 3 themselves are provided. The generated internal stress can be relaxed in the inner plating layers 14A 2 and 14B 2 .
内側めっき層14A,14Bの厚さは、外側めっき層14A,14Bの厚さよりも大きくてもよい。この場合、応力を緩和する機能を有する内側めっき層14A,14Bの厚さを十分に確保できる。そのため、素体10に応力がより作用し難くなるので、素体10にクラック(欠けや割れなど)が発生することをいっそう抑制できる。 The thicknesses of the inner plating layers 14A 2 and 14B 2 may be larger than the thicknesses of the outer plating layers 14A 3 and 14B 3 . In this case, it is possible to sufficiently secure the thickness of the inner plating layers 14A 2 and 14B 2 having a function of relaxing stress. For this reason, stress is less likely to act on the element body 10, so that the occurrence of cracks (chips, cracks, etc.) in the element body 10 can be further suppressed.
端子電極14Aは、主面10c,10dの一方と、端面10a及び側面10e,10fのうち内部電極12Aの引き出し部12Aが引き出されたいずれか一つの面とに、少なくとも配置されていればよい。端子電極14Bは、主面10c,10dの一方と、端面10b及び側面10e,10fのうち内部電極12Bの引き出し部12Bが引き出されたいずれか一つの面とに、少なくとも配置されていればよい。この場合、端子電極14A,14Bは、断面L字形状を呈する。 Terminal electrodes 14A are the major surface 10c, the one of the 10d, the end face 10a and the side surface 10e, to the one of the surface on which the lead portions 12A 2 of the internal electrodes 12A is drawn out of 10f, need only be disposed at least . Terminal electrodes 14B are main surfaces 10c, one of a 10d, the end face 10b and side 10e, to the one of the surface on which the lead portions 12B 2 of the internal electrode 12B is drawn out of 10f, need only be disposed at least . In this case, the terminal electrodes 14A and 14B have an L-shaped cross section.
本実施形態では、外側めっき層14A,14Bがそれぞれ端子電極14A,14Bの最外表面を構成していた。しかしながら、内側めっき層14A,14Bにおいて応力緩和の効果を得る目的の場合には、外側めっき層14A,14Bが端子電極14A,14Bの最外表面を構成しておらず、端子電極14A,14Bにおいて内側めっき層14A,14Bと外側めっき層14A,14Bとが素体10から近い側からこの順で並んでいればよい。 In the present embodiment, the outer plating layers 14A 3 and 14B 3 constitute the outermost surfaces of the terminal electrodes 14A and 14B, respectively. However, for the purpose of obtaining a stress relaxation effect in the inner plating layers 14A 2 and 14B 2 , the outer plating layers 14A 3 and 14B 3 do not constitute the outermost surfaces of the terminal electrodes 14A and 14B, and the terminal electrodes In 14A and 14B, the inner plating layers 14A 2 and 14B 2 and the outer plating layers 14A 3 and 14B 3 may be arranged in this order from the side closer to the element body 10.
1…積層コンデンサ、10…素体、10a,10b…端面、10c,10d…主面、10e,10f…側面、12A,12B…内部電極、14A,14B…端子電極、14A,14B…焼付電極層、14A,14B…内側めっき層、14A,14B…外側めっき層。 1 ... multilayer capacitor, 10 ... body, 10a, 10b ... end surface, 10c, 10d ... the main surface, 10e, 10f ... side, 12A, 12B ... internal electrode, 14A, 14B ... terminal electrodes, 14A 1, 14B 1 ... baking Electrode layer, 14A 2 , 14B 2 ... inner plating layer, 14A 3 , 14B 3 ... outer plating layer.

Claims (6)

  1. 互いに対向する一対の端面と、前記一対の端面同士を連結するように延びると共に互いに対向する一対の主面と、前記一対の端面同士及び前記一対の主面同士を連結するように延びると共に互いに対向する一対の側面とを有し、前記一対の主面の間の寸法が、前記一対の端面の間の寸法及び前記一対の側面の間の寸法よりも小さい素体と、
    前記素体のうち一方の前記端面側に位置すると共に、前記主面と、前記端面及び前記側面の少なくとも一方とにわたって連続して延びるように前記素体の表面に配置された第1の端子電極と、
    前記素体のうち他方の前記端面側に位置すると共に、前記主面と、前記端面及び前記側面の少なくとも一方とにわたって連続して延びるように前記素体の表面に配置された第2の端子電極と、
    前記素体内に位置すると共に、前記第1の端子電極に接続された第1の内部電極と、
    前記素体内に位置すると共に、前記第2の端子電極に接続された第2の内部電極とを備え、
    前記第1及び第2の内部電極は、前記一対の主面の対向方向において隣り合って配置されていると共に、前記対向方向から見たときに互いに一部が重なり合っており、
    前記第1及び第2の端子電極はそれぞれ、その最外表面を構成する第1のめっき層と、前記第1のめっき層及び前記素体の間に位置する第2のめっき層とを有し、
    前記第1のめっき層は、Cu、Ag、Au、Ni、Pd又はSnを主成分として含み、
    前記第2のめっき層の密度は、前記第1のめっき層の密度よりも小さい、積層コンデンサ。
    A pair of opposing end surfaces, a pair of main surfaces that extend to connect the pair of end surfaces, and a pair of opposing main surfaces, and a pair of end surfaces and the pair of main surfaces that extend to face each other. A body having a dimension between the pair of main surfaces smaller than a dimension between the pair of end surfaces and a dimension between the pair of side surfaces;
    The first terminal electrode disposed on the surface of the element body so as to be located on one end face side of the element body and continuously extend over the main surface and at least one of the end face and the side surface. When,
    A second terminal electrode which is located on the other end face side of the element body and is arranged on the surface of the element body so as to continuously extend over the main surface and at least one of the end surface and the side surface. When,
    A first internal electrode located in the element body and connected to the first terminal electrode;
    A second internal electrode located in the element body and connected to the second terminal electrode;
    The first and second internal electrodes are arranged adjacent to each other in the opposing direction of the pair of main surfaces, and partially overlap each other when viewed from the opposing direction,
    Each of the first and second terminal electrodes has a first plating layer constituting the outermost surface thereof, and a second plating layer located between the first plating layer and the element body. ,
    The first plating layer contains Cu, Ag, Au, Ni, Pd or Sn as a main component,
    The multilayer capacitor wherein the density of the second plating layer is smaller than the density of the first plating layer.
  2. 前記第1及び第2のめっき層は共にCuを主成分として含む、請求項1に記載の積層コンデンサ。   The multilayer capacitor according to claim 1, wherein each of the first and second plating layers contains Cu as a main component.
  3. 前記第1及び第2の端子電極はそれぞれ、前記素体の表面に位置する焼付電極層と、前記焼付電極層を覆う前記第2のめっき層と、前記第2のめっき層を覆う前記第1のめっき層とを有し、
    前記焼付電極層はCuを主成分として含む、請求項2に記載の積層コンデンサ。
    Each of the first and second terminal electrodes includes a baked electrode layer located on the surface of the element body, the second plated layer covering the baked electrode layer, and the first plated layer covering the second plated layer. And having a plating layer of
    The multilayer capacitor according to claim 2, wherein the baked electrode layer contains Cu as a main component.
  4. 前記第1及び第2の端子電極はそれぞれ、前記素体の表面に位置する焼付電極層と、前記焼付電極層を覆う前記第2のめっき層と、前記第2のめっき層を覆う前記第1のめっき層とを有し、
    前記第2のめっき層はNiを主成分として含んでおり、前記第1のめっき層はCuを主成分として含んでいる、請求項1に記載の積層コンデンサ。
    Each of the first and second terminal electrodes includes a baked electrode layer located on the surface of the element body, the second plated layer covering the baked electrode layer, and the first plated layer covering the second plated layer. And having a plating layer of
    The multilayer capacitor according to claim 1, wherein the second plating layer includes Ni as a main component, and the first plating layer includes Cu as a main component.
  5. 前記第1のめっき層の厚さは、前記第2のめっき層の厚さよりも大きい、請求項1〜4のいずれか一項に記載の積層コンデンサ。   The multilayer capacitor according to claim 1, wherein a thickness of the first plating layer is larger than a thickness of the second plating layer.
  6. 前記第2のめっき層の厚さは、前記第1のめっき層の厚さよりも大きい、請求項1〜4のいずれか一項に記載の積層コンデンサ。   5. The multilayer capacitor according to claim 1, wherein a thickness of the second plating layer is larger than a thickness of the first plating layer.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016149484A (en) * 2015-02-13 2016-08-18 Tdk株式会社 Multilayer capacitor

Citations (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04236412A (en) * 1991-01-21 1992-08-25 Toshiba Corp Electronic component of ceramic
JPH0790675A (en) * 1993-09-21 1995-04-04 Murata Mfg Co Ltd Production of electronic parts
JPH08162359A (en) * 1994-12-08 1996-06-21 Murata Mfg Co Ltd Chip type ceramic electronic part
JPH11297565A (en) * 1998-04-07 1999-10-29 Murata Mfg Co Ltd Ceramic electronic component and its manufacture
JP2000049034A (en) * 1998-07-28 2000-02-18 Murata Mfg Co Ltd Ceramic electronic component and manufacture of the same
JP2000357627A (en) * 1999-06-15 2000-12-26 Mitsubishi Materials Corp Chip type electronic component
JP2001110666A (en) * 1999-10-08 2001-04-20 Murata Mfg Co Ltd Electronic component, and manufacturing method thereof
JP2002203735A (en) * 2000-12-27 2002-07-19 Ibiden Co Ltd Capacitor, multilayered printed wiring board, and method of manufacturing the same
JP2006342390A (en) * 2005-06-08 2006-12-21 Tdk Corp Barrel plating method and method for manufacturing electronic parts
JP2008166645A (en) * 2007-01-04 2008-07-17 Toyota Motor Corp Plating member, and its manufacturing method
JP2009158662A (en) * 2007-12-26 2009-07-16 Tdk Corp Electronic component and method of producing the same
JP2010123865A (en) * 2008-11-21 2010-06-03 Murata Mfg Co Ltd Ceramic electronic component and component built-in substrate
JP2011014564A (en) * 2009-06-30 2011-01-20 Murata Mfg Co Ltd Laminated ceramic electronic component and manufacturing method therefor
JP2011124257A (en) * 2009-12-08 2011-06-23 Ngk Spark Plug Co Ltd Component built in wiring board, method of manufacturing the same, and the wiring board
JP2012009813A (en) * 2010-05-27 2012-01-12 Murata Mfg Co Ltd Ceramic electronic component and manufacturing method for the same
JP2012253292A (en) * 2011-06-07 2012-12-20 Murata Mfg Co Ltd Electronic component

Patent Citations (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04236412A (en) * 1991-01-21 1992-08-25 Toshiba Corp Electronic component of ceramic
JPH0790675A (en) * 1993-09-21 1995-04-04 Murata Mfg Co Ltd Production of electronic parts
JPH08162359A (en) * 1994-12-08 1996-06-21 Murata Mfg Co Ltd Chip type ceramic electronic part
JPH11297565A (en) * 1998-04-07 1999-10-29 Murata Mfg Co Ltd Ceramic electronic component and its manufacture
JP2000049034A (en) * 1998-07-28 2000-02-18 Murata Mfg Co Ltd Ceramic electronic component and manufacture of the same
JP2000357627A (en) * 1999-06-15 2000-12-26 Mitsubishi Materials Corp Chip type electronic component
JP2001110666A (en) * 1999-10-08 2001-04-20 Murata Mfg Co Ltd Electronic component, and manufacturing method thereof
JP2002203735A (en) * 2000-12-27 2002-07-19 Ibiden Co Ltd Capacitor, multilayered printed wiring board, and method of manufacturing the same
JP2006342390A (en) * 2005-06-08 2006-12-21 Tdk Corp Barrel plating method and method for manufacturing electronic parts
JP2008166645A (en) * 2007-01-04 2008-07-17 Toyota Motor Corp Plating member, and its manufacturing method
JP2009158662A (en) * 2007-12-26 2009-07-16 Tdk Corp Electronic component and method of producing the same
JP2010123865A (en) * 2008-11-21 2010-06-03 Murata Mfg Co Ltd Ceramic electronic component and component built-in substrate
JP2011014564A (en) * 2009-06-30 2011-01-20 Murata Mfg Co Ltd Laminated ceramic electronic component and manufacturing method therefor
JP2011124257A (en) * 2009-12-08 2011-06-23 Ngk Spark Plug Co Ltd Component built in wiring board, method of manufacturing the same, and the wiring board
JP2012009813A (en) * 2010-05-27 2012-01-12 Murata Mfg Co Ltd Ceramic electronic component and manufacturing method for the same
JP2012253292A (en) * 2011-06-07 2012-12-20 Murata Mfg Co Ltd Electronic component

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016149484A (en) * 2015-02-13 2016-08-18 Tdk株式会社 Multilayer capacitor

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