JPS6316713A - Signal switching circuit - Google Patents

Abstract

PURPOSE:To reduce the delay time and the power consumption by providing the 2nd and 3rd transistors (TRs) constituting a current mirror to a load of the 1st TR of emitter follower constitution and connecting the 1st and 2nd diodes to the 2nd and 3rd TRs respectively. CONSTITUTION:Each terminal of the 1st and 2nd diodes 7, 8 is connected in common to the load of the 1st TR 4 of emitter follower constitution and the other terminal of the 1st diode is connected to the collector, base of the 2nd TR 9 and the base of the 3rd TR 10. Further, the emitter of the 2nd and 3rd TRs is connected respectively to ground, the collector of the 3rd TR is connected to the other terminal of the 2nd diode so as to give the constitution where the common connecting point of the 1st and 2nd diodes is used as an input terminal and the collector of the 3rd TR is used as an output terminal. Thus, in selecting the Miller ratio properly and giving a minimum current only to the input terminal, the power consumption is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a high-speed operation, low power consumption signal switching circuit.

BACKGROUND ART Saturation signal switching circuits using bipolar transistors can be constructed easily and at low cost, and are therefore widely used in switching circuits that do not require high performance.The conventional signal switching circuits are explained below.

FIG. 2 shows a conventional signal switching circuit, which is an example constructed from a composite semiconductor integrated circuit including bipolar transistors and CMOS transistors. 12 is input terminal, 13 is CMO
S inverter, 14 is a power supply terminal, 15 is an emitter follower operation transistor, 16, 17 is a resistor, 18 is a switching transistor for taking out an output signal, and 19 is an output terminal.

The operation of the signal switching circuit configured as described above will be described below.

First, a logic signal enters the input terminal 12, the CMOS inverter 13 operates, and its output drives the light-load emitter follower transistor 15. A logic signal of low impedance is taken out from the emitter of the transistor 15, converted into a current by the resistor 16, 17, drives the output transistor 18, and takes out an output signal from its collector terminal 19. Note that the resistor 17 is provided to reduce the delay time when the output transistor 18 changes from an on state to an off state.

Problems to be Solved by the Invention However, in the conventional configuration described above, the base current required to turn on the output transistor 18 increases as the current amplification factor varies and as the output transistor 18 approaches the saturation region. Considering the sudden decrease in amplification factor, etc., it is necessary to design with sufficient margin for the base current required to operate in the active region, and for this reason, the power supply current has to increase considerably. I didn't get it. In addition, the collector of the output transistor 18 becomes saturated more than necessary due to the excessive base current, and charge is accumulated in the base. Therefore, even if the base current disappears, the output transistor 18 continues to operate until the charge accumulated in the base is discharged. The on state continues and there is a delay time until the off state is reached. Although it is possible to reduce the delay time by reducing the resistance value of the resistor 17, in that case, the power supply current will further increase. In other words, the conventional configuration has the disadvantage that if an attempt is made to reduce the delay time, power consumption increases, and if an attempt is made to reduce the power consumption, the delay time becomes longer.

The present invention solves the above conventional problems and aims to simultaneously reduce the delay time and power consumption of a signal switching circuit.

Means for Solving the Problems To achieve this objective, the signal switching circuit of the present invention comprises:
Emitter follower configuration One terminal of each of the first and second diodes is commonly connected to the load section of the first transistor, and the other terminal of the first diode is connected to the collector, base, and third transistor of the second transistor. the emitters of the second and third transistors are respectively grounded, and the collector of the third transistor is connected to the second transistor.
The third transistor is connected to the other terminal of the first diode, the common connection point of the first and second diodes is used as an input terminal, and the collector of the third transistor is used as an output terminal.

Effect With this configuration, even when the current signal converted by the first transistor in the emitter follower configuration is input from the input terminal and the third transistor is turned on, the forward voltage of the first diode and the third Base of transistor
Since the collector-emitter voltage of the third transistor, which is determined by subtracting the forward voltage of the second diode from the sum of the emitter voltages, is greater than the saturation voltage of the collector of the third transistor, the third transistor The transistor can be kept in a non-saturated state, and the delay time until the third transistor turns off can be reduced. Also second. Since each third transistor constitutes a current mirror circuit, by appropriately selecting the mirror ratio and passing only the minimum necessary current to the input terminal,
It becomes possible to reduce power consumption.

EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the signal switching circuit of the present invention, which is constructed from a composite semiconductor integrated circuit of bipolar transistors and CMO transistors. In Figure 1,
1 is an input terminal, 2 is a CMOS inverter, 3 is a power supply terminal, 4 is a transistor with emitter follower operation, 5 and 6 are resistors, 7.8 is a diode, 9 and 10 are transistors, and the emitter current flowing through transistor 9 is A current mirror circuit doubles the current and returns it to the transistor 10, and 11 is an output terminal. The current amplification factor of the transistor is infinite, and the voltage between the base and emitter and the forward voltage of the diode are 0.7.
When approximated by V, the output voltage V appearing at the output terminal 11 is
OL is the resistance value R1, R of the power supply voltage VCC1 resistors 5, 6.
2. When the drawing current at the output terminal 11 is IQL, VOL=0.7-1+3 Here, by appropriately selecting the resistance values RI, R2+ and the mirror ratio K, the delay time can be reduced without saturating transistor 0. Can be done. Furthermore, since a margin in the base current of the current resistor 10 of the power supply is not required, the value R1 of the resistor 5 can be increased to several tens of times that of the conventional one, and power consumption is reduced to several tenths of that of the conventional one.

Effects of the Invention As described above, the present invention provides a second transistor forming a current mirror in the load section of the first transistor having an emitter follower structure.
．． In addition, in order to prevent saturation of the collector of the third transistor as an output transistor, the first and second diodes are respectively connected to the second transistor.
．． By connecting to the third transistor, delay time and power consumption can be reduced, which has great practical effects.

[Brief explanation of the drawing]

Ru. 1...Input terminal, 2...CMOS inverter, 3...Power terminal, 4,9.10...
...transistor, 5.6...resistance, 7,8
...Diode, 11...Output terminal. Name of agent: Patent attorney Toshio Nakao et al.18 Figure 1

Claims (1)

[Claims] A signal switching circuit in which a load section of a first transistor having an emitter follower configuration is branched by first and second diodes to couple respective electric paths of second and third transistors of a current mirror pair.