JPH04227316A - Switching circuit - Google Patents

Abstract

PURPOSE:To drive a heavy load with low power consumption at a high speed by using a MOS transistor(TR) so as to form an output stage and employing a bipolar MOS composite logic circuit operated in the unsaturation mode so as to form a drive stage. CONSTITUTION:An inverter circuit 141 consists of a bipolar MOS composite logic circuit, and a load 143 such as a resistor, a relay or a lamp is connected between a drain electrode of an NMOS TR 142 and a power supply terminal equipment 144 whose voltage is V. The buffer circuit acts like an inverting load switch, and when an input V1 is switched to a high level, an output VM of an inverter circuit 141 goes to a low level, an NMOS 142 is turned off to interrupt a current flowing to the load 143. When the input V1 is switched to a low level, the output VM of the inverter circuit 141 goes to a high level, the NMOS 142 is turned on to supply a current from the power supply terminal 144 to the load 143.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switching circuit, and more particularly to a switching circuit suitable for driving a high current load.

0002

2. Description of the Related Art As a circuit capable of relatively large load switching, a TTL (transistor) circuit as shown in FIG.
transistor logic) circuits are well known. In FIG. 1, 11, 12, and 13 are Schottky NPN transistors with clamps, 14 is a level shift diode, and 15, 16, and 17 are resistors.

When the potential VI of the input terminal 10 switches to a high level, the NPN transistors 11 and 13 turn on,
NPN transistor 12 is turned off. Therefore, the charge accumulated in the load CL is discharged to the ground potential GND through the NPN transistor 13, and the potential V of the output terminal 18 is
0 switches to low level. Next, when the potential V1 of the input terminal 10 is switched to a low level, the NPN transistors 11 and 13 are turned off, and the NPN transistor 12 is turned on. Therefore, from the power supply terminal 19 to the resistor 17, the NPN
Load CL through transistor 12 and diode 14
A charging current flows, and the potential V0 of the output terminal 18 switches to a high level. This circuit has the advantage of being able to switch a heavy load at a relatively high speed, but on the other hand, it requires the formation of Schottky diodes to prevent saturation of the NPN transistors 11, 12, and 13, which increases manufacturing costs. In addition, in an output buffer circuit such as a TTL circuit whose output stage is composed of bipolar transistors, when the output is at a low level, a specified DC current IOL is generated at a specified output voltage VOL.
Must be able to SINK. For example, a typical TT
In the L circuit, VOL=0.4 V and IOL=16 mA. Therefore, when the voltage VI at the input terminal 10 is at a high level, the voltage VCC at the power supply terminal 19, the resistor 15, and the NPN
I to the NPN transistor 13 through the transistor 11
There is a problem in that the base current required to flow OL=16 mA must be kept flowing at all times, which increases power consumption.

Furthermore, since a bipolar transistor having a charge storage effect is used in the output stage, the time it takes for the bipolar transistor to turn off due to the charge stored in the base of the bipolar transistor becomes longer.

As another conventional example capable of driving a relatively large load, a CMOS circuit as shown in FIG. 2 is widely known. In FIG. 2, 21 and 23 are PMOS transistors, 22
, 24 are NMOS transistors, PMOS 21 and NMOS 22 constitute a drive stage inverter, and PMOS 2
3. Configure an output stage inverter with NMOS24.

When the potential VI of the input terminal 20 is switched to a high level, the PMOS 21 is turned off, the NMOS 22 is turned on, then the PMOS 23 is turned on, and the NMOS 24 is turned off. Therefore, a charging current flows from the power supply terminal 26 of the voltage VCC through the PMOS 23 to the load CL, and the potential V0 of the output terminal 25 switches to a high level. Next, when the voltage V2 at the input terminal is switched to a low level, PMOS21 is turned on and NMOS22 is turned off, then PMOS23 is turned off and NMOS24 is turned on. Therefore, the charge stored in the load CL is transferred to the NMOS24
The potential V0 of the output terminal 25 is switched to a low level.

The greatest advantage of this circuit is that it consumes almost zero power in a steady state when the input potential VI is at a high or low level, making it possible to reduce power consumption. However, on the other hand, it is difficult to increase the speed, and There is a problem in that the power consumption depends on the rise and fall characteristics of the switching waveform of the drive stage and tends to increase.

In the circuit of FIG. 2, in order to increase the load driving capability of the output stage, PMOS 23 and NMOS 2 of the output stage are
It is necessary to design the channel width W of 4 to be large. In FIG. 3, the channel widths of PMOS21 and NMOS22 in the drive stage in FIG. 2 are constant, and the PMOS23 and NMOS in the output stage are
This figure shows the delay time characteristics with respect to the load capacity when the channel width of 24 is changed to W1 and 2W1. Figure 3
As is clear, even though the drive capacity of the output stage is doubled, the delay time becomes large below the load capacitance C1. The cause of this is PMOS2 in the output stage.
This is because by doubling the channel widths of NMOS 24 and NMOS 24, the gate input capacitance was doubled, resulting in insufficient drive stage performance and increased delay time. If the driving capacity of the drive stage is insufficient, another problem will occur. That is,
If the driving capacity of the drive stage is insufficient, the input waveform of the output stage will change more slowly. Therefore, during the transition period of switching of the output stage, the time during which both the PMOS 23 and NMOS 24 of the output stage are ON becomes longer, and the power consumption during switching increases.

[0009]

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the drawbacks of the prior art described above and to provide a switching circuit that can drive a high load at high speed with low power consumption.

0010

[Means for Solving the Problems] In a switching circuit comprising an output stage connected to a predetermined load and acting as a switch for the load, and a drive stage driving the output stage, the output stage has a control gate. the first terminal being a control gate is connected to the output terminal of the drive stage;
The second terminal is connected to the first potential section via the load, the third terminal is configured with a transistor connected to the second potential section, and the drive stage includes a bipolar transistor that drives the transistor. and a MOS transistor that drives the bipolar transistor in response to an input signal.

[0011]

[Operation] In order to drive a high load with low power consumption and high speed, the output stage is configured with a transistor such as a bipolar transistor that does not have a charge storage effect, such as a MOS transistor.
By configuring the drive stage with a non-saturated bipolar/MOS composite logic circuit in which the input part is a MOS transistor and the output part is a bipolar transistor, the gate capacitance of the MOS transistor in the output stage is charged and discharged at high speed.

In a preferred embodiment of the present invention, the gate input capacitance of the MOS transistor in the output stage is larger than the gate input capacitance of the MOS transistor in the drive stage.

[0013]

Embodiment FIG. 4 is a diagram showing a first embodiment of the present invention. In the figure, 141 is an inverter circuit;
It is composed of a bipolar/MOS complex logic circuit as shown in FIG. 7, etc. 142 is an NMOS transistor, and a load 143 such as a resistor, relay, lamp, etc. is connected between its drain electrode and a power supply terminal 144 at a potential V. This buffer circuit acts as an inverting load switch, and when the input VI switches to a high level, the output VM of the inverter circuit 141 goes to a low level and the NMOS 142
is turned off. Therefore, the current flowing through load 143 is interrupted. Next, when the input VI is switched to a low level, the output VM of the inverter circuit 141 becomes a high level and the NMOS 142 is turned on. Therefore, power terminal 1
44 supplies current to the load 143. FIG. 5 is a diagram showing another embodiment of the present invention. In the figure, 151
is composed of a bipolar/MOS complex logic circuit as shown in FIGS. 6, 7, etc. 152 is a PMOS transistor whose source S is connected to a power supply terminal 154 at potential V, and between its drain D and ground potential GND a load 153 such as a resistor, relay, lamp, etc. is connected. This buffer circuit acts as a non-inverting load switch, and when the input signal VI switches to a high level, the output VM of the inverter circuit 151 goes to a low level, turning on the PMOS 152. therefore,
The load 15 is connected from the power supply terminal 154 through the PMOS 152.
3 is supplied with current. Next, when the input signal VI switches to low level, the output VM of the inverter circuit 151 becomes high level, and the PMOS
152 turns off. Therefore, the current flowing through load 153 is interrupted. An example of a desirable circuit of the bipolar/MOS composite inverter circuits 141 and 151 is shown in FIG.

In FIG. 6, 71 indicates that the collector C is the first
A first NPN whose emitter E is connected to the output terminal 77 (potential VM) is connected to the power supply terminal 78 which has a fixed potential VCC of
A bipolar transistor (hereinafter simply referred to as a first NPN) 72 has a collector C connected to an output terminal 77 and an emitter E connected to the output terminal 77.
is a second NPN bipolar transistor (hereinafter simply referred to as the second NPN bipolar transistor) connected to the ground potential GND, which is a second fixed potential.
73 is a PMOS whose gate G is connected to the input terminal 70, and whose source S and drain D are respectively connected to the collector C and base B of the first NPN 71;
An NMOS whose gate G is connected to the input terminal 70 and whose drain D and source S are connected to the collector C and base B of the second NPN 72, and 75 are the drain D of the PMOS 73 and the NMOS
Diffusion resistor or MOS connected to drain D of S76
A base charge extraction element 76 formed of a resistor or the like is a base charge extraction element formed of a diffused resistor or a MOS resistor that connects the base B and emitter E of the second NPN 72.

Table 1 shows the logical operation of this embodiment.

[0016]

[Table 1]

When input VI is at “0” (low) level, P
MOS 73 is turned on and NMOS 74 is turned off. Therefore, the base potential of the first NPN 71 rises, and the first
NPN71 is turned on. At this time, since the NMOS 74 is turned off, the supply of current to the second NPN 72 is stopped, and the accumulated charge accumulated in the base B of the second NPN 72 is extracted, so the second NPN 72 is rapidly turned off. .

[0018] When VI70 is at “1” level, PMOS
73 is turned off and NMOS 74 is turned on. At this time, since the PMOS 73 is turned off, the supply of current to the first NPN 71 is stopped, and the accumulated charge accumulated in the base B of the first NPN 71 is extracted, so that the first NPN
PN71 turns off quickly. Also, since the NMOS 74 is turned on and the drain D and source S are short-circuited, the base B of the second NPN 72 receives current from the gate capacitance of the PMOS 62 and NMOS 63 in the output stage connected to the output VM. The current of the accumulated charge accumulated in the base B of the first NPN 71 as described above is also supplied, and the second NPN 72 is rapidly turned on. Therefore, the output VM quickly becomes the "0" level.

In the above operation process, the base and collector junctions of the NPNs 71 and 72 are not biased in sequence, so the charge accumulation effect due to saturation peculiar to bipolar transistors does not occur, and high-speed switching is performed.

Here, the function of the base charge extracting element 75 will be further described. As mentioned above, the base charge extraction element 7
5, when the PMOS 73 and the first NPN 71 are switched from on to off, the accumulated charge accumulated in the base B of the first NPN 71 is extracted, and the first NPN 71 is rapidly turned off. NMO with charge turned on
It has the function of supplying it to the base B of the second NPN 72 via S74 and rapidly turning on the second NPN 72.

Furthermore, the base charge extraction element 75 is a PMO
Since it is provided between the drain D of S73 and the drain D of NMOS74, the power supply potential VCC and the ground potential GN
No conductive path is created between it and D, and low power consumption can be achieved. In other words, if the base charge extraction element 75 is P
When the drain of MOS73 is connected to the ground potential GND, when the input VI is at "0" level,
A conductive path is created between the power supply potential VCC and the ground potential GND, and current always flows, increasing power consumption, but in this embodiment, no conductive path is created.

Furthermore, in this embodiment, since the base potential extraction element 75 is also connected to the output VM, when the input VI is at the "0" level, the base potential extraction element 75 is connected to the PMOS 73 and the base electric charge extraction element 75. Thus, the potential of the output VM can be raised to the potential VCC of the power supply terminal 78.

Next, the function of the base charge extracting element 76 will be further described. As mentioned above, the base charge extraction element 76
has the function of extracting the accumulated charge accumulated in the base B of the second NPN 72 and rapidly turning off the second NPN 72 when the NMOS 74 and the second NPN 72 are switched from on to off. Furthermore, in this embodiment, when the input VI is at the "1" level, the base charge extracting element 76 and the NMOS
74, the output VM can be lowered to the "0" level.

FIG. 7 shows another example of the bipolar/MOS composite inverter circuits 141 and 151.

In the figure, 43 is a PMOS which is a MOS transistor of the other conductivity type, 44, 45 and 46 are NMOS which are MOS transistors of one conductivity type, and 47 and 48 are NMOS transistors.
It is a PN bipolar transistor. PMOS43 and N
The MOS 44 constitutes a CMOS inverter, and each gate G is connected to the common input terminal 40, and each drain D is connected to the base B of the first NPN 47 and also to the gate G of the NMOS 46. PMOS
Sources S of the NMOS 43 and NMOS 44 are respectively connected to the power supply terminal 42 which is a first potential and the ground potential GND which is a second potential. The drain D of the NMOS 45 is connected to the output terminal 41 of potential VM, the gate G is connected to the input terminal 40, and the source S is connected to N
Drain D of MOS46 and base B of second NPN48
connected to. Source S of NMOS46 is ground potential GN
Connected to D. Also, the collector C of the first NPN47
is the power supply 42, base B is PMOS43 and NMOS44
The emitter E connects the drain D of the NMOS45, the collector C of the second NPN48 and the output VM to the common drain connection point of the
Commonly connected to. The base B of the second NPN48 is N
It is commonly connected to the source S of the MOS 45 and the drain D of the NMOS 46, and the emitter E is connected to the ground potential GND.

Next, the operation of the inverter circuit of this embodiment will be explained. Now, when the input VI switches from a low level to a high level, the PMOS 43 is turned off, the NMOS 44 is turned on, and the base of the first NPN 47 is at a low level, so the first NPN 47 and NMOS 46 are turned off. On the other hand, since NMOS45 is turned on, the second NPN48
is turned on, and the output VM switches from high level to low level.

Next, the NMOS 45 and the second NPN 48 whose input VI switches from high level to low level are turned off. On the other hand, since the PMOS 43 is turned on and the NMOS 44 is also turned off, the base of the first NPN 47 is switched to a high level, and the first NPN 47 and NMOS 46 are turned on. Therefore, the output VM switches from a low level to a high level. Here, the function of NMOS 46 is important for high-speed switching. NMOS 46 acts as a dynamic discharge circuit. That is, when the input VI switches from a low level to a high level, the gate of the NMOS 46 switches from a high level to a low level, so that the NMOS 46 is turned off. Therefore, the base B of the second NPN 48 and the ground potential GND
Since there is no current bus, all the current flowing from the output VM through the NMOS45 is transferred to the base B of the second NPN48.
The second NPN 48 can be turned on at high speed. Next, when the input VI switches from high to low, the gate G of NMOS 46 switches from low to high, so NMOS 46 is turned on. Therefore, the base B of the second NPN 48 is grounded with low impedance, and the accumulated charges in the base region are quickly discharged. Therefore, the second NPN 48 is quickly turned off.

Now, when the input VI is at a high level, PM
OS43 and first NPN47 are off, input VI
When is at a low level, NMOS 45 and second NPN 48 are off. Therefore, the inverter circuit of this example is CMO
Like the S circuit, no power is consumed in steady state.

[0029]

As is clear from the above description, the switching circuit according to the present invention has a driving stage composed of a bipolar/MOS composite logic circuit with MOS input and bipolar output and non-saturated operation, and a MOS transistor with no charge storage effect. This can be realized with a two-stage configuration of the output stage consisting of
It is possible to perform switching at higher speed and with lower power consumption than conventional methods, and is suitable for switching circuits such as thermal head drivers, IED drivers, lamp drivers, and relay drivers.

[Brief explanation of the drawing]

FIG. 1 is a diagram of a conventional TTL buffer circuit.

FIG. 2 is a conventional CMOS buffer circuit diagram.

FIG. 3 is a diagram showing delay time characteristics of the CMOS buffer circuit of FIG. 2;

FIG. 4 is a switching circuit diagram showing one embodiment of the present invention.

FIG. 5 is a switching circuit diagram showing another embodiment of the present invention.

FIG. 6 is a diagram showing a configuration example of a bipolar/MOS composite inverter circuit used in the present invention.

FIG. 7 is a diagram showing another configuration example of a bipolar/MOS composite inverter circuit used in the present invention.

[Explanation of symbols]

141, 151...Bipolar/MOS composite logic circuit, 1
42,152...MOS transistor.

Claims (1)

[Claims] 1. In a switching circuit comprising an output stage that is connected to a predetermined load and acts as a current switch for the load, and a drive stage that drives the output stage, the output stage has three terminals including a control gate, and the output stage has three terminals including a control gate. A first terminal, which is a gate, is connected to the output terminal of the drive stage, a second terminal is connected to the first potential section via the load, and a third terminal is connected to the second potential section. The drive stage is composed of a non-saturated bipolar/MOS composite logic circuit including a bipolar transistor that drives the transistor and a MOS transistor that drives the bipolar transistor in response to an input signal. switching circuit.