JPS6120426A - Logical gate circuit - Google Patents

Logical gate circuit

Info

Publication number
JPS6120426A
JPS6120426A JP59140536A JP14053684A JPS6120426A JP S6120426 A JPS6120426 A JP S6120426A JP 59140536 A JP59140536 A JP 59140536A JP 14053684 A JP14053684 A JP 14053684A JP S6120426 A JPS6120426 A JP S6120426A
Authority
JP
Japan
Prior art keywords
npn
base
output
potential
field effect
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59140536A
Other languages
Japanese (ja)
Other versions
JPH0622326B2 (en
Inventor
Ikuro Masuda
郁朗 増田
Masahiro Iwamura
将弘 岩村
Yoji Nishio
洋二 西尾
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP59140536A priority Critical patent/JPH0622326B2/en
Publication of JPS6120426A publication Critical patent/JPS6120426A/en
Publication of JPH0622326B2 publication Critical patent/JPH0622326B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/09448—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET in combination with bipolar transistors [BIMOS]

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To obtain a logical gate circuit at a high speed with low power consumption, which consists of a field effect transistor and a bipolar transistor, by providing a p type field effect transistor as a discharge bus of a storage charge between the base of the first npn transistor and an output terminal. CONSTITUTION:As for NMOSs 21, 22, the respective drains are connected in common to an output, the respective sources are connected in common to the base of the second npn, and the respective gates are connected to the first input A and the second input B. In case both inputs A, B are switched to a low level from a high level, NMOSs 21, 22 are turned off, and an npn 32 also off. On the other hand, both PMOSs 11, 12 are turned on, a base current is supplied to an npn 31 from power source +V, the npn 31 is turned on, and an output is switched to a high level from a low level. Accordingly, when the base potential of the npn 31 is below a threshold voltage of a PMOS51, the PMOS51 is remained to off state, currents flowing through the PMOSs 11, 12 are all used for charging of a base area of the npn 31, and the npn 31 is turned on quickly.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は論理ゲート回路に係り、特に、電界効果トラン
ジスタとバイポーラトランジスタを組合せた論理回路に
関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to logic gate circuits, and particularly to logic circuits that combine field effect transistors and bipolar transistors.

〔発明の背景〕[Background of the invention]

電界効果トランジスタとバイポーラトランジスタを組合
せた論理ゲート回路には、例えば、第２図に示す二入力
ＮＯＲゲート回路が公知である。As a logic gate circuit that combines a field effect transistor and a bipolar transistor, for example, a two-input NOR gate circuit shown in FIG. 2 is well known.

この回路はＰＭＯ３１１と１２、ＮＭＯ８２１と２２で
二入力ＮＯＨの論理動作を行ない、ＮＰＮトランジスタ
、３１と３２で出力の高負荷を高速に駆動できるように
したものである。この回路ではＮＰＮ３１と３２は前段
のＭＯ８論理により相補動作を行なうが、それぞれがオ
ンからオフにスイッチするとき、図示のように夫々のベ
ース端子に形成される寄与容ＭＣ５Ｉ、Ｃ１ｌ、に蓄積
された電荷の放電パスが無いため、ＮＰＮ３１と３２が
オフにスイッチする時間が長くなる。このため、ＮＰＮ
３１と３２がともにオンになっている状態が長く続き、
スイッチング時間が遅くなるだけでなく、消費電力も大
きくなる。This circuit performs a two-input NOH logic operation using PMOs 311 and 12 and NMOs 821 and 22, and is capable of driving a high output load at high speed using NPN transistors 31 and 32. In this circuit, the NPNs 31 and 32 perform complementary operations based on the MO8 logic in the previous stage, but when each switches from on to off, as shown in the figure, the contribution capacitors MC5I and C1l formed at their respective base terminals accumulate Since there is no charge discharge path, the time that NPNs 31 and 32 are switched off becomes longer. For this reason, NPN
Both 31 and 32 remain on for a long time,
Not only does switching time become slower, but power consumption also increases.

これらの問題を解決するものとして、発明者等は先に特
願昭５７−１１９８１５号として、第３図に示す論理回
路を提案している。この回路は二入力ＮＯＲ回路の例で
あるが、第３図で、ＮＰＮ３１とＮＰＮ３２がオフにス
イッチするとき、ベース領域の寄生容量に蓄積された電
荷を放電させる手段としてＮＰＮ３１とＮＰＮ３２の夫
々のベースとエミッタ間に設けられる抵抗４１．４２と
、相補動作を行なうＰＭＯＳＩＩ、１２とＮＭＯ８２１
，２２と組合わせることにより、入力に応じていずれか
一方のＮＰＮが動作し、他方のＮＰＮはベース電荷の放
電が速やかに行なわれ、オフになる。従って、スイッチ
ングの過渡期のごく短い時間以外は余分な電源電流が流
れないというＣＭＯ３の特徴がそのまま維持され、出力
はバイポーラトランジスタによって高負荷駆動能力を備
え、負荷によらず高速動作を実現できる。In order to solve these problems, the inventors previously proposed a logic circuit shown in FIG. 3 in Japanese Patent Application No. 119815/1983. Although this circuit is an example of a two-input NOR circuit, in FIG. 3, when NPN31 and NPN32 switch off, the respective bases of NPN31 and NPN32 are Resistors 41 and 42 provided between the
, 22, one of the NPNs operates according to the input, and the base charge of the other NPN is quickly discharged and turned off. Therefore, the feature of the CMO3 that no extra power supply current flows except for a very short time during the switching transition period is maintained, and the output is provided with a high load drive capability using a bipolar transistor, and high-speed operation can be realized regardless of the load.

しかし、第３図の回路では次のように問題がある。すな
わち、ＮＰＮ３　ｉがオフとなり、ＮＰＮ３２がオンと
なって出力が高レベルから低レベルにスイッチするとき
、ＮＰＮ３１のベース領域の蓄積電荷は抵抗４１を通し
て放電されるため、抵抗４１が小さいほど放電は速やか
に行なわれる。However, the circuit shown in FIG. 3 has the following problems. That is, when NPN3 i is turned off and NPN32 is turned on to switch the output from high level to low level, the accumulated charge in the base region of NPN31 is discharged through resistor 41, so the smaller the resistor 41 is, the faster the discharge is. It will be held in

一方、ＮＰＮ３１がＯＮ、ＮＰＮ３２がオフになり、出
力が低レベルから高レベルにスイッチするとき、ＰＭＯ
ＳＩＩ、１．２を流れる電流はＮＰＮ３１のベースに流
れ、抵抗４１にも分流する。従って、この場合、抵抗４
１が大きいほどＮＰＮ３１のターンオンは速くなる。従
って、ＮＰＮ３１のターン・オンとターン・オフ特性を
両立させるには、ターン・オフを速めるために抵抗４１
を小さくしておき、ターン・オンの時は、抵抗４１に分
流する電流を見込んで、ＰＭＯＳＩＩ、１２から大きな
電流を供給してやらなければならない。このため、ＰＭ
ＯＳＩＩ、１２のサイズが大きくなり、消費電力が増大
する欠点がある。On the other hand, when NPN31 turns on and NPN32 turns off, and the output switches from low level to high level, PMO
The current flowing through SII, 1.2 flows to the base of NPN 31 and is also shunted to resistor 41. Therefore, in this case, the resistance 4
The larger 1 is, the faster the NPN 31 turns on. Therefore, in order to achieve both turn-on and turn-off characteristics of NPN31, resistor 41 is required to speed up turn-off.
is kept small, and when turning on, a large current must be supplied from the PMOS II, 12, taking into account the current that will be shunted to the resistor 41. For this reason, PM
This has the disadvantage that the size of OSII 12 increases and power consumption increases.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、電界効トランジスタおよびバイポーラ
トランジスタからなる高速、低消費電力の論理ゲート回
路を提供するにある。An object of the present invention is to provide a high-speed, low-power consumption logic gate circuit comprising field effect transistors and bipolar transistors.

〔発明の概要〕[Summary of the invention]

本発明の論理ゲート回路の特徴は、コレクタが第一の電
位に、エミッタが出力にそれぞれ接続された第一のＮＰ
Ｎトランジスタと、コレクタが出力に、エミッタが第二
の電位に接続された第二のＮＰＮ）−ランジスタと、第
一の電位と第−ＮＰＮのベース間に夫々のソースとドレ
インが直列、または、並列接続され、ゲートが夫々異な
る入力に接続されたＰ型電界効果トランジスタと、第二
のＮＰＮトランジスタのコレクタとベース間に並列、ま
たは、直列接続され、ゲートが夫々異なる入力に接続さ
れたＮ型電界効果トランジスタからなる論理ゲート回路
において、第一のＮＰＮ）−ランジスタのベースと出力
端子の間に蓄積電荷の放電バスとしてＰ型電界効果トラ
ンジスタを設けたことにある。The logic gate circuit of the present invention is characterized by a first NP whose collector is connected to a first potential and whose emitter is connected to an output.
a second NPN transistor whose collector is connected to the output and whose emitter is connected to a second potential) and whose respective sources and drains are in series between the first potential and the base of the second NPN; A P-type field effect transistor connected in parallel with its gates connected to different inputs, and an N-type field effect transistor connected in parallel or in series between the collector and base of a second NPN transistor, with its gates connected to different inputs. In a logic gate circuit composed of field effect transistors, a P-type field effect transistor is provided as a discharge bus for accumulated charges between the base of the first NPN transistor and the output terminal.

〔発明の実施例〕[Embodiments of the invention]

第１図は本発明による二入力ＮＯＲゲートの実施例を示
す。図において１１．１２はＰＭＯ３でＰＭＯＳＩＩの
ソースは第一の電位子Ｖに接続され、ドレインはＰＭＯ
８１２のソースと接続され、ゲートは第一の入力Ａに接
続されている。ＰＭＯ５１２のソースはＰＭＯ８１１の
ドレインに接続され、ドレインは第一のＮＰＮ３１のベ
ースに接続され、ゲートは第二の入力Ｂに接続されてい
る。２１と２２はＮＭＯ３で夫々のドレインは出力に共
通接続され、夫々のソースは第二のＮＰＮのベースに共
通接続され、夫々のゲートは、第一の入力Ａと第二の入
力Ｂに接続される。また、第一のＮＰＮのコレクタは第
一の電位に、エミッタは出力に、ベースはＰＭＯ８ｌ　
２のドレインに接続され、第二のＮＰＮのコレクタは出
力に、エミッタは第二の電位（接地）に、ベースはＮＭ
Ｏ３２１，２１のドレインに接続され、抵抗４２は第二
のＮＰＮのベースと第二の電位間に接続される。FIG. 1 shows an embodiment of a two-input NOR gate according to the invention. In the figure, 11.12 is PMO3, the source of PMOSII is connected to the first potential V, and the drain is PMO3.
812, and its gate is connected to the first input A. The source of PMO 512 is connected to the drain of PMO 811, the drain is connected to the base of first NPN 31, and the gate is connected to second input B. 21 and 22 are NMO3, their respective drains are commonly connected to the output, their respective sources are commonly connected to the base of the second NPN, and their respective gates are connected to the first input A and the second input B. Ru. Also, the collector of the first NPN is at the first potential, the emitter is at the output, and the base is at PMO8l.
2, the collector of the second NPN is connected to the output, the emitter is connected to the second potential (ground), and the base is connected to the NM
The resistor 42 is connected between the base of the second NPN and the second potential.

さらに、ＰＭＯ３５１のソースは第一のＮＰＮのベース
に、ドレインは出力に、ゲートは第二の電位にそれぞれ
接続される。Furthermore, the source of the PMO 351 is connected to the base of the first NPN, the drain is connected to the output, and the gate is connected to the second potential.

このように構成された本発明の回路動作は次のとおりで
ある。The circuit operation of the present invention configured as described above is as follows.

いま、入力Ａ、Ｂが共に高レベルから低レベルにスイッ
チした場合、ＮＭＯ３２１，２２でオフとなり、ＮＰＮ
３２もオフとなる。一方、ＰＭＯＳｌ１．１２が共にオ
ンになり、電源子ＶからＮＰＮ３１にベース電流を供給
し、ＮＰＮ３］をオンさせ、出力を低レベルから高レベ
ルにスイッチする。Now, if both inputs A and B switch from high level to low level, NMO321 and 22 turn off, and NPN
32 is also turned off. On the other hand, PMOSl1 and PMOSl12 are both turned on, supplying base current from power supply element V to NPN31, turning on NPN3], and switching the output from low level to high level.

この立上りの初期の過程ではＰＭＯ８５１のソースとゲ
ート間のバイアスはほぼ零の状態になっている。従って
、ＮＰＮ３１のベース電位がＰＭＯ５５］のスレッショ
ールド電圧以下のとき、ＰＭＯ８５］はオフのままであ
り、ＰＭＯＳｌ、］、１２を流れる電流はすべて、ＮＰ
Ｎ３］のベース領域の充電に使われ、ＮＰＮ３１を急速
にターン・オンさせる。In this initial stage of rise, the bias between the source and gate of the PMO 851 is approximately zero. Therefore, when the base potential of NPN31 is below the threshold voltage of PMO55], PMO85] remains off and all current flowing through PMOS1,],12 is
N3] is used to charge the base region of NPN31 and quickly turn on NPN31.

次に入力Ａ、Ｂの少なくとも一つが高レベルから低レベ
ルにスイッチした場合、ＰＭＯ８ＩＩ。Then, if at least one of inputs A and B switches from high level to low level, PMO8II.

１２の少くとも一つがオフするため、ＮＰＮ３　］もオ
フとなる。一方、ＮＭＯ３２１，２２の少くとも一つが
オンするため、出力からＮＭＯ８２］。12 is turned off, NPN3] is also turned off. On the other hand, since at least one of NMO321 and 22 is turned on, NMO82] is output from the output.

２２の少くても一つを通して第二のＮＰＮのベースに電
流が流れてＮＰＮ３２をオンするため、出力は高レベル
から低レベルにスイッチする。この立下りの初期の過程
ではＰＭＯ８のソースは高電位であるため、ＰＭＯ３５
１のソースとゲート電圧のバイアスは電源電圧とほぼ同
じ大きさであるため、ＰＭＯ５５１を流れる電流は大き
くなり、ＮＰＮ３１のベース領域の蓄積電荷の放電が速
くなり、ＮＰＮ３１を急速にターン・オフさせる。Current flows through at least one of the NPNs 22 to the base of the second NPN, turning on the NPN 32, thereby switching the output from a high level to a low level. During this initial stage of falling, the source of PMO8 is at a high potential, so PMO35
Since the source and gate voltage bias of 1 is approximately the same magnitude as the power supply voltage, the current flowing through PMO 551 is large and the accumulated charge in the base region of NPN 31 is discharged faster, causing NPN 31 to turn off quickly.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、電界効果トランジスタおよびバイポー
ラトランジスタからなる高速で低消費電力の論理ゲート
回路が得られる。According to the present invention, a high-speed, low-power consumption logic gate circuit consisting of field effect transistors and bipolar transistors can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の一実施例の二入力ＮＯＲ回路図、第２
図、第３図は従来の二入力ＮＯＲ回路図である。 １．１．１３・・・ＰＭＯＳトランジスタ、２１．２２
・・・ＮＭｏ５トランジスタ、３１．３２・・・ＮＰＮ
トランジスタ、４１．４２・・・抵抗、５１・・・ＰＭ
Ｏ８第　１　図Fig. 1 is a two-input NOR circuit diagram of an embodiment of the present invention;
3 are diagrams of a conventional two-input NOR circuit. 1.1.13...PMOS transistor, 21.22
...NMo5 transistor, 31.32...NPN
Transistor, 41.42...Resistor, 51...PM
O8 Figure 1

Claims (1)

【特許請求の範囲】 １、コレクタが第一の電位に、エミッタが出力にそれぞ
れ接続された第一のＮＰＮトランジスタと、コレクタが
前記出力に、エミッタが第二の電位にそれぞれ接続され
た第二のＮＰＮトランジスタと、入力と、各ゲートがそ
れぞれ異なる前記入力に、各ソース及びドレインが第一
の電位と前記第一のＮＰＮトランジスタのベース間に並
列接続されるＰ型電界効果トランジスタと、各ゲートが
それぞれ異なる前記入力に、各ドレイン及びソースが前
記第二のＮＰＮトランジスタの前記コレクタとベース間
に直列接続されたＮ型電界効果トランジスタからなる論
理ゲート回路において、 ソースが前記第一のＮＰＮトランジスタのベースに接続
され、ドレインが出力端子に接続され、ゲートが前記第
二の電位に接続されたＰ型電界効果トランジスタを設け
たことを特徴とする論理ゲート回路。 ２、コレクタが第一の電位に、エミッタが出力にそれぞ
れ接続された第一のＮＰＮトランジスタと、コレクタが
前記出力に、エミッタが第二の電位にそれぞれ接続され
た第二のＮＰＮトランジスタと、入力と、各ゲートがそ
れぞれ異なる前記入力に、各ソース及び各ドレインが第
一の電位と前記第一のＮＰＮトランジスタのベース間に
直列接続されるＰ型電界効果トランジスタと、各ゲート
がそれぞれ異なる前記入力に、各ドレイン及び各ソース
が前記第二のＮＰＮトランジスタのコレクタとベース間
に並列接続されるＮ型電界効果トランジスタからなる論
理ゲート回路において、 ソースが前記第一のＮＰＮトランジスタの前記ベースに
接続され、ドレインが出力端子に接続され、ゲートが前
記第二の電位に接続されたＰ型電界効果トランジスタを
設けた事を特徴とする論理ゲート回路。[Claims] 1. A first NPN transistor whose collector is connected to a first potential and whose emitter is connected to an output; and a second NPN transistor whose collector is connected to the output and whose emitter is connected to a second potential. an NPN transistor, an input, a P-type field effect transistor, each gate of which is connected in parallel to the input, each source and drain of which is connected in parallel between a first potential and the base of the first NPN transistor; In a logic gate circuit comprising an N-type field effect transistor whose drain and source are connected in series between the collector and base of the second NPN transistor, the source is connected to the input of the first NPN transistor, respectively different from each other. 1. A logic gate circuit comprising a P-type field effect transistor connected to a base, a drain connected to an output terminal, and a gate connected to the second potential. 2. a first NPN transistor having a collector connected to a first potential and an emitter connected to an output; a second NPN transistor having a collector connected to the output and an emitter connected to a second potential; and an input; and a P-type field effect transistor, each source and drain connected in series between a first potential and the base of the first NPN transistor, each gate having a different input, each source and each drain connected in series between the base of the first NPN transistor, and each gate having a different input. In a logic gate circuit comprising an N-type field effect transistor in which each drain and each source are connected in parallel between the collector and base of the second NPN transistor, the source is connected to the base of the first NPN transistor. . A logic gate circuit comprising a P-type field effect transistor whose drain is connected to the output terminal and whose gate is connected to the second potential.
JP59140536A 1984-07-09 1984-07-09 Logic gate circuit Expired - Lifetime JPH0622326B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59140536A JPH0622326B2 (en) 1984-07-09 1984-07-09 Logic gate circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59140536A JPH0622326B2 (en) 1984-07-09 1984-07-09 Logic gate circuit

Publications (2)

Publication Number Publication Date
JPS6120426A true JPS6120426A (en) 1986-01-29
JPH0622326B2 JPH0622326B2 (en) 1994-03-23

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Family Applications (1)

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JP59140536A Expired - Lifetime JPH0622326B2 (en) 1984-07-09 1984-07-09 Logic gate circuit

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4779014A (en) * 1986-09-26 1988-10-18 Kabushiki Kaisha Toshiba BiCMOS logic circuit with additional drive to the pull-down bipolar output transistor
US4977337A (en) * 1989-06-13 1990-12-11 Mitsubishi Denki Kabushiki Kaisha Bi-CMOS logic circuit
CN113472343A (en) * 2021-07-14 2021-10-01 山东大学 Construction method of logic gate

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5979641A (en) * 1982-10-29 1984-05-08 Hitachi Ltd Semiconductor integrated circuit device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5979641A (en) * 1982-10-29 1984-05-08 Hitachi Ltd Semiconductor integrated circuit device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4779014A (en) * 1986-09-26 1988-10-18 Kabushiki Kaisha Toshiba BiCMOS logic circuit with additional drive to the pull-down bipolar output transistor
US4977337A (en) * 1989-06-13 1990-12-11 Mitsubishi Denki Kabushiki Kaisha Bi-CMOS logic circuit
CN113472343A (en) * 2021-07-14 2021-10-01 山东大学 Construction method of logic gate

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JPH0622326B2 (en) 1994-03-23

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