JPH0320086B2 - - Google Patents

Info

Publication number
JPH0320086B2
JPH0320086B2 JP58057479A JP5747983A JPH0320086B2 JP H0320086 B2 JPH0320086 B2 JP H0320086B2 JP 58057479 A JP58057479 A JP 58057479A JP 5747983 A JP5747983 A JP 5747983A JP H0320086 B2 JPH0320086 B2 JP H0320086B2
Authority
JP
Japan
Prior art keywords
differential pair
output
differential
gain
pair
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58057479A
Other languages
Japanese (ja)
Other versions
JPS59183514A (en
Inventor
Hiroshi Ihara
Tamio Tomosugi
Masahiro Oochi
Tsutomu Kamoto
Mamoru Yosogi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp, Nippon Electric Co Ltd filed Critical Nippon Telegraph and Telephone Corp
Priority to JP5747983A priority Critical patent/JPS59183514A/en
Publication of JPS59183514A publication Critical patent/JPS59183514A/en
Publication of JPH0320086B2 publication Critical patent/JPH0320086B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03GCONTROL OF AMPLIFICATION
    • H03G1/00Details of arrangements for controlling amplification
    • H03G1/0005Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal
    • H03G1/0017Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal the device being at least one of the amplifying solid state elements of the amplifier
    • H03G1/0023Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal the device being at least one of the amplifying solid state elements of the amplifier in emitter-coupled or cascode amplifiers

Landscapes

  • Control Of Amplification And Gain Control (AREA)

Description

【発明の詳細な説明】 本発明は差動回路を用いた可変利得差動増幅回
路に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a variable gain differential amplifier circuit using a differential circuit.

従来可変利得増幅回路は個別部品で構成したり
混成集積回路で構成する例が多く、また集積回路
としても小規模のものしか実現されていなかつ
た。このため増幅回路間の結合は交流結合(コン
デンサやトランス)が多く採用されていた。
Conventionally, variable gain amplifier circuits have often been constructed from individual components or hybrid integrated circuits, and only small-scale integrated circuits have been realized. For this reason, AC coupling (capacitors and transformers) was often used for coupling between amplifier circuits.

最近集積回路の技術が進み、大規模回路が集積
化できるようになつているが、コンデンサやトラ
ンスは集積化が困難であり、従つて従来の回路は
大規模集積化には不適当である。
Recently, integrated circuit technology has advanced and it has become possible to integrate large-scale circuits, but capacitors and transformers are difficult to integrate, and conventional circuits are therefore unsuitable for large-scale integration.

本発明はモノリシツク大規模集積化に適し段間
を直接結合できる可変利得増幅回路を提供するこ
とを目的とする。
SUMMARY OF THE INVENTION An object of the present invention is to provide a variable gain amplifier circuit that is suitable for large-scale monolithic integration and allows direct coupling between stages.

また本発明は利得可変範囲を大きくできる増幅
回路を提供することを目的とする。
Another object of the present invention is to provide an amplifier circuit that can widen the variable gain range.

さらにまた本発明は差動増幅回路に適用できる
可変利得増幅回路を提供することを目的とする。
A further object of the present invention is to provide a variable gain amplifier circuit that can be applied to a differential amplifier circuit.

本発明による差動増幅回路はトランジスタ対を
含む第1、第2および第3の差動対、第1および
第2の負荷抵抗、電流源および負帰還回路から少
なくとも構成され、第1の差動対の入力に信号電
圧を与え、第2の差動対の入力に負帰還回路の出
力を与え、第3の差動対の入力に利得制御信号を
与え、電流源の出力を第3の差動対に与え、第3
の差動対の一方の出力を第1の差動対に与え、第
3の差動対の他方の出力を第2の差動対に与え、
第1の差動対の一方の出力と第2の差動対の一方
の出力を第1の負荷抵抗に与え、第1の差動対の
他方の出力と第2の差動対の他方の出力を第2の
負荷抵抗に与える回路構成を有し、上記利得制御
信号を変化することによつて上記信号電圧が第1
および第2の負荷抵抗に伝達される利得を変化す
ることを特徴とする。
A differential amplifier circuit according to the present invention includes at least first, second, and third differential pairs including transistor pairs, first and second load resistors, a current source, and a negative feedback circuit; A signal voltage is applied to the input of the pair, an output of the negative feedback circuit is applied to the input of the second differential pair, a gain control signal is applied to the input of the third differential pair, and the output of the current source is applied to the input of the third differential pair. given to the dynamic pair, the third
giving one output of the differential pair to the first differential pair, giving the other output of the third differential pair to the second differential pair,
One output of the first differential pair and one output of the second differential pair are applied to the first load resistor, and the other output of the first differential pair and the other output of the second differential pair are applied to the first load resistor. It has a circuit configuration that provides an output to a second load resistor, and by changing the gain control signal, the signal voltage changes to the first load resistance.
and changing the gain transmitted to the second load resistor.

更に詳しく説明すれば利得制御信号Vcによつ
て制御される第3の差動対によつて電流源の電流
を任意に分流し、分流された二つの電流をそれぞ
れ第1の差動対および第2の差動対に与え、両者
の利得を相反的に可変としている。第1の差動対
は信号電圧を増幅し、第2の差動対は負帰還信号
を増幅し、二つの差動対が負荷抵抗を共有するこ
とによつて両信号を加算している。したがつて本
回路の総合利得Aは第1の差動対の利得をA1
第2の差動対の利得をA2、負帰還回路の利得を
βとすると次式で表わされる。
More specifically, the current of the current source is arbitrarily divided by the third differential pair controlled by the gain control signal V c , and the two divided currents are divided into the first differential pair and the third differential pair controlled by the gain control signal V c. It is applied to the second differential pair, and the gains of both are variable reciprocally. The first differential pair amplifies the signal voltage, the second differential pair amplifies the negative feedback signal, and the two differential pairs share a load resistance to add both signals. Therefore, the overall gain A of this circuit is the gain of the first differential pair A 1 ,
When the gain of the second differential pair is A 2 and the gain of the negative feedback circuit is β, it is expressed by the following equation.

A=A1/1+βA2 第1の差動対の電流を大きくし、第2の差動対
の電流を少なくすればA1が増加しA2が減少して
総合利得Aは増加する。反対に第1の差動対の電
流を小さくし、第2の差動対の電流を大きくすれ
ばA1が減少しA2が増大して総合利得Aは減少す
る。従つて利得制御信号Vcによつて総合利得A
を制御できる。
A=A 1 /1+βA 2 If the current in the first differential pair is increased and the current in the second differential pair is decreased, A 1 increases, A 2 decreases, and the overall gain A increases. On the other hand, if the current in the first differential pair is decreased and the current in the second differential pair is increased, A 1 decreases, A 2 increases, and the overall gain A decreases. Therefore, the total gain A is determined by the gain control signal V c
can be controlled.

次に図面によつて本発明の実施例を説明する。
第1図は本発明による回路を構成するのに必要と
する回路要素の実施例を示す。第1図aおよびb
は差動対の例であり、aは二つのトランジスタの
みによつて構成した例で、101および102が
信号入力端、103および104が出力端、10
5が電流入力端である。bは二つのトランジスタ
のエミツタを抵抗109および110を介して結
合した差動対の例であり、入出力端はaの場合と
全く同じである。尚両例共にNPNトランジスタ
で構成しているがPNPトランジスタ或はその他
の能動素子でも構成可能である。第1図cおよび
dは電流源の実施例である。cではトランジスタ
112、抵抗113およびダイオード114から
構成された電流源の構成例であり周知の回路であ
る(参考文献;中沢他訳アナログ集積回路近代科
学社)またdは抵抗115のみで構成した電流源
の例でcの場合より性能は劣るが十分実用になる
ものである。第1図eな負荷抵抗の例であり、単
純に抵抗117によつて構成されている。抵抗1
17の一端は電源Vccに接続している。第1図f
は負帰還回路の実施例を示す。118は入力端、
119は出力端であり、トランジスタ120およ
び抵抗123はエミツタフオロアを形成し、抵抗
121および抵抗122は減衰回路を形成する。
抵抗122の一端は電源VRに接続しているがこ
れは抵抗121に直流電流を流さないようにする
目的をもつている。この負帰還回路の利得βはエ
ミツタフオロアの利得を1とすれば抵抗121お
よび122の値で決り次式となる。
Next, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 shows an embodiment of the circuit elements necessary to construct a circuit according to the invention. Figure 1 a and b
is an example of a differential pair, and a is an example configured with only two transistors, 101 and 102 are signal input terminals, 103 and 104 are output terminals, 10
5 is a current input terminal. Component b is an example of a differential pair in which the emitters of two transistors are coupled through resistors 109 and 110, and the input and output terminals are exactly the same as those for component a. Although both examples are constructed with NPN transistors, they can also be constructed with PNP transistors or other active elements. Figures 1c and d are examples of current sources. c is an example of the configuration of a current source consisting of a transistor 112, a resistor 113, and a diode 114, which is a well-known circuit (Reference: Translated by Nakazawa et al., Analog Integrated Circuit Modern Science Co., Ltd.), and d is a current source configured only with a resistor 115. Although the performance is inferior to that of case c, it is sufficiently usable for practical use. FIG. 1 is an example of a load resistor, which is simply constituted by a resistor 117. resistance 1
One end of 17 is connected to the power supply Vcc . Figure 1 f
shows an example of a negative feedback circuit. 118 is the input end;
119 is an output terminal, a transistor 120 and a resistor 123 form an emitter follower, and a resistor 121 and a resistor 122 form an attenuation circuit.
One end of the resistor 122 is connected to the power supply V R for the purpose of preventing direct current from flowing through the resistor 121. The gain β of this negative feedback circuit is determined by the values of the resistors 121 and 122 as follows, assuming that the gain of the emitter follower is 1.

β=R0/R0+R1 但しR1は抵抗121の値、R0は抵抗122の
値である。
β=R 0 /R 0 +R 1 where R 1 is the value of the resistor 121 and R 0 is the value of the resistor 122.

第2図は本発明による回路の一実施例を示す。
第1、第2および第3の差動対201,202お
よび203、第1および第2の負荷抵抗204お
よび205電流源206、負帰還回路207が含
まれる。信号電圧Viは端子208,209から第
1の差動対201に入力される。利得制御信号
Vcは端子210,211から第3の差動対20
3に入力される。負帰還回路207の出力は端子
216,217から第2の差動対に入力される。
本回路の出力電圧は負帰還回路207のエミツタ
フオロアから端子212,213によりとりださ
れている。
FIG. 2 shows an embodiment of a circuit according to the invention.
First, second and third differential pairs 201, 202 and 203, first and second load resistors 204 and 205, current source 206, and negative feedback circuit 207 are included. The signal voltage V i is input to the first differential pair 201 from terminals 208 and 209. gain control signal
V c is from the terminals 210 and 211 to the third differential pair 20
3 is input. The output of the negative feedback circuit 207 is input to the second differential pair from terminals 216 and 217.
The output voltage of this circuit is taken out from the emitter follower of the negative feedback circuit 207 through terminals 212 and 213.

電流源206の出力電流Ipは利得制御信号Vc
よつて制御される第3の差動対203によつて二
つに分流され出力214および215となる。出
力214の電流I1、出力215の電流をI2(但しI1
+I2=I0)とすると I1=eVC/VT/1+eVC/VT I2=1/1+eVC/VT と表わされる。但しVTは熱電圧で常温で約26m
Vである(参考文献;前掲)。これらの電流によ
つて駆動される第1の差動対201および第2の
差動対202の利得A1およびA2はそれぞれ次式
で表わされる。
The output current I p of the current source 206 is divided into two outputs 214 and 215 by the third differential pair 203 controlled by the gain control signal V c . The current of output 214 is I 1 and the current of output 215 is I 2 (however, I 1
+I 2 =I 0 ), then I 1 =e VC/VT /1+e VC/VT I 2 =1/1+e VC/VT . However, V T is a thermal voltage and is approximately 26 m at room temperature.
V (references; supra). Gains A 1 and A 2 of the first differential pair 201 and the second differential pair 202 driven by these currents are expressed by the following equations, respectively.

A1=Rc/2VT/I1+RE1 A2=Rc/2VT/I1+RE2 但しRcは第1および第2の負荷抵抗の値(等
しいとする)であり、RE1は第1の差動対のエミ
ツタ側の抵抗の値、RE2は第2の差動対のエミツ
タ側の抵抗の値である。従つて総合利得Aは次式
となる。
A 1 = R c /2V T /I 1 +R E1 A 2 = R c /2V T /I 1 +R E2 However, R c is the value of the first and second load resistance (assumed to be equal), and R E1 is the value of the resistance on the emitter side of the first differential pair, and R E2 is the value of the resistance on the emitter side of the second differential pair. Therefore, the total gain A is expressed as follows.

A=A1/1+βA2=RC/2VT/I1+RE1/1+β
RC/2VT/I1+RE2 I1とI2は利得制御信号Vcによつて任意に制御で
きるので総合利得Aを制御できる。
A=A 1 /1+βA 2 =R C /2V T /I 1 +R E1 /1+β
R C /2V T /I 1 +R E2 Since I 1 and I 2 can be arbitrarily controlled by the gain control signal V c , the total gain A can be controlled.

具体的設計例として最大利得Amax=10、最小
利得Amin=2が要求されている場合を考える。
最大利得Amaxは利得制御信号Vcが最大のとき
すなわちVc=0.5v位で第3の差動対の一方の出力
I1が最大(I0)となり他方の出力I2が最小〓とな
る場合とすれば次式となる。
As a specific design example, consider a case where maximum gain Amax=10 and minimum gain Amin=2 are required.
The maximum gain Amax is the output of one of the third differential pairs when the gain control signal V c is maximum, that is, V c = 0.5V.
If I 1 is the maximum (I 0 ) and the other output I 2 is the minimum 〓, the following equation is obtained.

Amax=A1=Rc/2VT/I0+RE1 I0=2mA、Rc=500ΩとすればRE1=24Ωとな
る。
Amax=A 1 =R c /2V T /I 0 +R E1 If I 0 =2 mA and R c =500Ω, then R E1 =24Ω.

次に最小利得Aminは利得制御信号Vcが0のと
き、すなわち第3の差動対の二つの出力I1とI2
等しいとき(I1=I2=1/2I0)に設定すれば Amin=RC/4VT/I0+RE1/1+βRC
4VT/I0+RE2 β=1/2とすればRE2=385Ωとなる。以上の定
数によつて回路を構成すれば利得制御電圧Vc
0vから+0.5v程度まで変化することによつて総合
利得Aは2倍から10倍まで変化できる。尚上述の
実施例では第1、第2および第3の差動対の入力
に与える信号電圧、負帰還回路の出力信号および
利得制御信号を平衡信号として与えているが、不
平衡信号として与えることも可能である。この場
合にはそれぞれの差動対の一方の入力に信号を与
え他方の入力に適当な基準バイアス電圧を与えれ
ばよい。
Next, the minimum gain Amin should be set when the gain control signal V c is 0, that is, when the two outputs I 1 and I 2 of the third differential pair are equal (I 1 = I 2 = 1/2I 0 ). Amin=R C /4V T /I 0 +R E1 /1+βR C /
If 4V T /I 0 + R E2 β = 1/2, then R E2 = 385Ω. By configuring a circuit with the above constants, the gain control voltage V c can be
By changing from 0v to about +0.5v, the total gain A can be changed from 2 times to 10 times. In the above embodiment, the signal voltages applied to the inputs of the first, second, and third differential pairs, the output signal of the negative feedback circuit, and the gain control signal are applied as balanced signals, but they may be applied as unbalanced signals. is also possible. In this case, a signal may be applied to one input of each differential pair, and an appropriate reference bias voltage may be applied to the other input.

本発明による可変利得差動増幅回路は次の特長
がある。
The variable gain differential amplifier circuit according to the present invention has the following features.

(1) 差動型であるため良好なS/Nおよび安定動
作が得られる。
(1) Since it is a differential type, good S/N ratio and stable operation can be obtained.

(2) 負帰還によつて利得を制御しているので良好
な周波数特性が得られる。
(2) Since the gain is controlled by negative feedback, good frequency characteristics can be obtained.

(3) 差動対を効果的に利用したため利得制御によ
つて出力電圧の直流レベルが変化しない。した
がつて多段直流結合が可能であり高集積化に適
す。
(3) Since differential pairs are effectively used, the DC level of the output voltage does not change due to gain control. Therefore, multi-stage DC coupling is possible and suitable for high integration.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明による回路を構成するための回
路要素の実施例を示し、第2図は本発明による回
路の一実施例を示す。 201,202,203;差動対、204,2
05;負荷抵抗、206;電流源、207;負帰
還回路。
FIG. 1 shows an embodiment of circuit elements for constructing a circuit according to the invention, and FIG. 2 shows an embodiment of the circuit according to the invention. 201, 202, 203; differential pair, 204, 2
05; Load resistance, 206; Current source, 207; Negative feedback circuit.

Claims (1)

【特許請求の範囲】[Claims] 1 トランジスタ対を含む第1、第2および第3
の差動対、第1および第2の負荷抵抗、電流源、
および負帰還回路から少なくとも構成され、第1
の差動対の入力間に入力信号電圧は与えるも負帰
還回路の出力は与えず、第2の差動対の入力に負
帰還回路の出力は与えるも入力信号電圧は与え
ず、第3の差動対の入力に利得制御信号を与え、
電流源の出力を第3の差動対に与え、第3の差動
対の一方の出力を第1の差動対に与え、第3の差
動対の他方の出力を第2の差動対に与え、第1の
差動対の一方の出力と第2の差動対の一方の出力
を第1の負荷抵抗に与え、第1の差動対の他方の
出力と第2の差動対の他方の出力を第2の負荷抵
抗に与える回路構成を有し、上記利得制御信号を
変化することによつて第3の差動対の両出力の電
流配分比を変化させることを特徴とする可変利得
差動増幅回路。
1 a first, second and third transistor pair comprising a pair of transistors;
a differential pair of first and second load resistors, a current source,
and a negative feedback circuit, the first
An input signal voltage is applied between the inputs of the second differential pair, but the output of the negative feedback circuit is not applied; an output of the negative feedback circuit is applied to the input of the second differential pair, but no input signal voltage is applied; Apply a gain control signal to the input of the differential pair,
The output of the current source is applied to a third differential pair, one output of the third differential pair is applied to the first differential pair, and the other output of the third differential pair is applied to the second differential pair. one output of the first differential pair and one output of the second differential pair are applied to the first load resistor, and the other output of the first differential pair and the second differential pair are applied to the first load resistor. It has a circuit configuration that supplies the other output of the pair to a second load resistor, and is characterized by changing the current distribution ratio between both outputs of the third differential pair by changing the gain control signal. variable gain differential amplifier circuit.
JP5747983A 1983-04-01 1983-04-01 Variable gain differential amplifier circuit Granted JPS59183514A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5747983A JPS59183514A (en) 1983-04-01 1983-04-01 Variable gain differential amplifier circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5747983A JPS59183514A (en) 1983-04-01 1983-04-01 Variable gain differential amplifier circuit

Publications (2)

Publication Number Publication Date
JPS59183514A JPS59183514A (en) 1984-10-18
JPH0320086B2 true JPH0320086B2 (en) 1991-03-18

Family

ID=13056842

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5747983A Granted JPS59183514A (en) 1983-04-01 1983-04-01 Variable gain differential amplifier circuit

Country Status (1)

Country Link
JP (1) JPS59183514A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0691390B2 (en) * 1988-05-02 1994-11-14 株式会社東芝 amplifier
JP2649207B2 (en) * 1993-07-19 1997-09-03 大成建設株式会社 Jig for multiple steel bars

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS514911A (en) * 1974-07-02 1976-01-16 Tokyo Shibaura Electric Co ZATSUONJOKYOKAIRO

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS514911A (en) * 1974-07-02 1976-01-16 Tokyo Shibaura Electric Co ZATSUONJOKYOKAIRO

Also Published As

Publication number Publication date
JPS59183514A (en) 1984-10-18

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