JPH01256806A - Differential amplifier circuit - Google Patents

Differential amplifier circuit

Info

Publication number
JPH01256806A
JPH01256806A JP8561288A JP8561288A JPH01256806A JP H01256806 A JPH01256806 A JP H01256806A JP 8561288 A JP8561288 A JP 8561288A JP 8561288 A JP8561288 A JP 8561288A JP H01256806 A JPH01256806 A JP H01256806A
Authority
JP
Japan
Prior art keywords
capacitor
gain
trs
differential amplifier
amplifier circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8561288A
Other languages
Japanese (ja)
Inventor
Fumio Suzuki
文雄 鈴木
Kazutatsu Kurioka
千立 栗岡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
NEC Engineering Ltd
Original Assignee
NEC Corp
NEC Engineering Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, NEC Engineering Ltd filed Critical NEC Corp
Priority to JP8561288A priority Critical patent/JPH01256806A/en
Publication of JPH01256806A publication Critical patent/JPH01256806A/en
Pending legal-status Critical Current

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  • Amplifiers (AREA)

Abstract

PURPOSE:To prevent an input DC offset voltage from appearing at the output while DC voltage gain is eliminated by connecting emitters of two transistors(TRs) being component of a differential amplifier circuit by a capacitor and providing a constant current source corresponding to each of the two TRs. CONSTITUTION:A capacitor 7 is used for a constant current source and the capacitor 7 couples of both the TRs 1, 2 in terms of AC. Then constant current sources 10, 11 are provided respectively to the TRs 1, 2 individually. Through the constitution above, the voltage gain G is expressed in the following equation; G=R/{(kT/qI+1/(4pifC)}, where R is the resistance of resistors 5, 6, C is a capacitance of the capacitor 7, I is the current of the current sources 10, 11, (k) is the Boltzmann's constant, Q is the electric charge of an electron, T is the absolute temperature and (f) is a frequency. Then the gain G is illustrated as a curve shown in the frequency characteristic 2 and the G approaches zero as the frequency (f) is close to zero and then the gain is G=0 at the DC. In this case, the input DC offset voltage is not sent to the output.

Description

【発明の詳細な説明】 皮亙立ヱ 本発明は差動増幅回路に関するものである。[Detailed description of the invention] Skin lift The present invention relates to a differential amplifier circuit.

良米肱韮 従来の差動増幅回路は第5図に示す様に、2個のトラン
ジスタ1,2と、これ等トランジスタ1゜2のコレクタ
抵抗5,6と、同じくエミッタ抵抗8.9と、共通の定
電流源10とにより構成されている。両トランジスタの
ベース14.15が差動入力となり、コレクタ16.1
7が差動出力となっている。尚、12は直流電源を示し
ている。
As shown in Figure 5, the conventional differential amplifier circuit consists of two transistors 1 and 2, collector resistors 5 and 6 of these transistors 1.2, and emitter resistor 8.9. It is configured by a common constant current source 10. The bases 14.15 of both transistors serve as differential inputs, and the collectors 16.1
7 is a differential output. Note that 12 indicates a DC power supply.

この様な従来の差動増幅回路は第2図に示した周波数特
性1を有しており、直流において電圧利得を持つことは
明らかである。いま、ここで、入力される前段の直流オ
フセット電圧(入力直流オフセット電圧)をVIO1出
力直流オフセット電圧をV。とじ、利得をGとすると、
次式が得られる。
Such a conventional differential amplifier circuit has the frequency characteristic 1 shown in FIG. 2, and it is clear that it has a voltage gain in direct current. Now, here, the input DC offset voltage of the previous stage (input DC offset voltage) is VIO1 and the output DC offset voltage is V. When the gain is G,
The following equation is obtained.

Vo = G V to  ・”・・・(1)この様に
、入力電流オフセット電圧があると、電圧利得Gにより
出力端子16.17に出力直流オフセット電圧が現われ
るという欠点がある。
Vo = G V to ·” (1) As described above, when there is an input current offset voltage, there is a drawback that an output DC offset voltage appears at the output terminals 16 and 17 due to the voltage gain G.

九旦ム旦旬 本発明の目的は、直流利得をなくして入力直流オフセッ
ト電圧が出力へ現われないようにしな差動増幅回路を提
供することである。
SUMMARY OF THE INVENTION An object of the present invention is to provide a differential amplifier circuit that eliminates DC gain and prevents input DC offset voltage from appearing at the output.

1匪ム璽見 本発明によれば、ベースを入力としコレクタを出力とす
る2個のトランジスタからなる差動増幅回路であって、
前記2個のトランジスタのエミツタ間を接続すべく設け
られたコンデンサと、前記2個のトランジスタの各々に
対応して設けられた定電流源とを有することを特徴とす
る差動増幅回路が得られる。
According to the present invention, there is provided a differential amplifier circuit comprising two transistors having a base as an input and a collector as an output,
A differential amplifier circuit is obtained, comprising a capacitor provided to connect the emitters of the two transistors, and a constant current source provided corresponding to each of the two transistors. .

X里ヨ 以下に本発明の実施例を図面を用いて説明する。X Riyo Embodiments of the present invention will be described below with reference to the drawings.

第1図は本発明の一実111例の回路図であり、第5図
と同等部分は同一符号により示している。第5図におけ
るエミッタ抵抗8.9の代りにコンデンサ7を用いてお
り、このコンデンサ7により両トランジスタ1.2のエ
ミッタを交流的に結合している。そして各トランジスタ
1.2の定電流源10.11を夫々個別に設けている。
FIG. 1 is a circuit diagram of a 111th embodiment of the present invention, and parts equivalent to those in FIG. 5 are designated by the same reference numerals. A capacitor 7 is used in place of the emitter resistor 8.9 in FIG. 5, and the emitters of both transistors 1.2 are AC-coupled by this capacitor 7. Constant current sources 10.11 for each transistor 1.2 are provided individually.

他の構成は第5図のそれと同一であってその説明は省略
する。
The other configurations are the same as those shown in FIG. 5, and their explanation will be omitted.

かかる構成において、コレクタ抵抗5.6の抵抗値をR
とし、コンデンサ7の容量値をCとし、電流源10.1
1の電流源を1とすると、電圧利得Gは次式となる。
In such a configuration, the resistance value of the collector resistor 5.6 is R
, the capacitance value of the capacitor 7 is C, and the current source 10.1
Assuming that 1 current source is 1, the voltage gain G is given by the following equation.

G=R/ + (kT/(t I+1/ (4πfC)
)・・・・・・(2) 上式において、kはボルツマン定数、qは電子の電荷、
Tは絶対温度、では周波数である。
G=R/ + (kT/(t I+1/ (4πfC)
)...(2) In the above formula, k is Boltzmann's constant, q is the electron charge,
T is absolute temperature, then frequency.

上記(2)式は第2図に示す周波数特性2の様な曲線と
なり、周波数fが零に近づくとGも零に近づき、よって
直流ではG=0となる。このとき(1)式より、出力直
流オフセット電圧V。は次式となる。
The above equation (2) forms a curve like the frequency characteristic 2 shown in FIG. 2, and when the frequency f approaches zero, G also approaches zero, and therefore, in direct current, G=0. At this time, from equation (1), the output DC offset voltage V. is the following formula.

V o =G V Io = O・・・・・・(3)よ
って、入力直流オフセット電圧は出力に伝達されること
はないのである。
V o =G V Io = O (3) Therefore, the input DC offset voltage is not transmitted to the output.

第3図及び第4図は本発明の他の実施例を夫々示す回路
図であり、第1図及び第5図と同等部分は同一符号によ
り示している。これ等両回路では、夫々エミッタ間に抵
抗器を挿入して、入力ダイナミックレンジや利得を調整
するようにしたものであり、第1図の実施例と同様に出
力に直流オフセ・y トは現れない。
FIGS. 3 and 4 are circuit diagrams showing other embodiments of the present invention, and parts equivalent to those in FIGS. 1 and 5 are designated by the same reference numerals. In both of these circuits, a resistor is inserted between the respective emitters to adjust the input dynamic range and gain, and as with the embodiment shown in Figure 1, no DC offset appears in the output. do not have.

九匪五羞1 本発明によれば、直流の電圧利得をなくすように構成す
ることにより、入力直流オフセット電圧が出力に現われ
ないようにすることができるという効果がある。
According to the present invention, by configuring to eliminate the DC voltage gain, it is possible to prevent input DC offset voltage from appearing in the output.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例の回路図、第2図は本発明の
実施例回路と従来例回路との周波数特性を比較して示し
た図、第3図及び第4図は本発明の他の実施例を夫々示
す回路図、第5図は従来の差動増幅回路を示す図である
。 主要部分の符号の説明 1.2・・・・・・トランジスタ 7・・・・・・コンデンサ to、it・・・・・・定電流源 出願人 日本電気株式会社く外1名)
FIG. 1 is a circuit diagram of an embodiment of the present invention, FIG. 2 is a diagram comparing the frequency characteristics of the embodiment circuit of the present invention and a conventional circuit, and FIGS. 3 and 4 are diagrams of the present invention. FIG. 5 is a circuit diagram showing other embodiments, and FIG. 5 is a diagram showing a conventional differential amplifier circuit. Explanation of symbols of main parts 1.2...Transistor 7...Capacitor TO, IT...Constant current source Applicant: 1 person from NEC Corporation)

Claims (1)

【特許請求の範囲】[Claims] (1)ベースを入力としコレクタを出力とする2個のト
ランジスタからなる差動増幅回路であって、前記2個の
トランジスタのエミッタ間を接続すべく設けられたコン
デンサと、前記2個のトランジスタの各々に対応して設
けられた定電流源とを有することを特徴とする差動増幅
回路。
(1) A differential amplifier circuit consisting of two transistors with a base as an input and a collector as an output, including a capacitor provided to connect the emitters of the two transistors, and a capacitor provided to connect the emitters of the two transistors. What is claimed is: 1. A differential amplifier circuit comprising a constant current source provided corresponding to each of the constant current sources.
JP8561288A 1988-04-07 1988-04-07 Differential amplifier circuit Pending JPH01256806A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8561288A JPH01256806A (en) 1988-04-07 1988-04-07 Differential amplifier circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8561288A JPH01256806A (en) 1988-04-07 1988-04-07 Differential amplifier circuit

Publications (1)

Publication Number Publication Date
JPH01256806A true JPH01256806A (en) 1989-10-13

Family

ID=13863664

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8561288A Pending JPH01256806A (en) 1988-04-07 1988-04-07 Differential amplifier circuit

Country Status (1)

Country Link
JP (1) JPH01256806A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015188178A (en) * 2014-03-27 2015-10-29 日本電信電話株式会社 differential amplifier

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015188178A (en) * 2014-03-27 2015-10-29 日本電信電話株式会社 differential amplifier

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