JPS59813Y2 - amplifier circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an amplifier circuit that is used, for example, in an equalizer amplifier and requires a larger amplification degree without impairing the power supply voltage utilization rate.

Conventionally, in a direct-coupled amplifier with essentially two amplification stages,
The first and second stage amplification elements are of different polarity.

For example, as shown in Figure 1, the first stage amplification element is an N-channel field effect transistor 1, and the second stage amplification element is a P
NP) Use transistor 2.

In an amplifier circuit with two amplification stages as shown in Fig. 1, the first method is to increase the load impedance 3 of the first stage amplification element to increase the signal strength. One method is to increase the shunt ratio to the next stage amplification element, and the second method is to insert an impedance reduction circuit, such as an emitter follower, between the amplification stages to drive the next amplification stage with a lower impedance. be.

Now, in the case of the first method, a voltage drop is provided on the emitter side of the next stage to increase the load impedance 3, but in this case, there is a drawback that the utilization rate of the power supply voltage deteriorates.

In addition, the apparent value of load impedance 3 can be increased by making the load impedance 3 an active load, for example, if the first amplification stage is a differential amplification type, by using a current mirror circuit as the load, but the value of the apparent load impedance 3 can be increased by This method is limited by the input impedance of the amplification stage, and this method has the disadvantage that it is only effective when combined with the second method.

The present invention has been developed in view of the above, and aims to provide an amplifier circuit that eliminates the above-mentioned drawbacks and can obtain a large amplification degree with a simple circuit configuration without impairing the utilization rate of the power supply voltage. shall be.

The present invention is an emitter follower or Connect the source follower,
The output terminal of the emitter follower or the source follower and the input terminal of the next stage amplifying element are connected through a capacitor.

The present invention will be explained below with reference to examples.

FIG. 2 is a circuit diagram of an amplifier circuit according to an embodiment of the present invention,
Components that are the same as those of the amplifier circuit in FIG. 1 are given the same reference numerals.

In FIG. 2, 1 and 2 are respectively denoted as N-channel field effect transistors (hereinafter referred to simply as FETs).

) and PNP) transistors (hereinafter simply referred to as transistors).

), 3 is the load impedance of FET)-transistor 1, 8 is the load impedance of transistor 2, and 9 is a constant current source.

A resistor 4 is connected between the drain of the FET 1-transistor and the resistor 3, and the voltage applied to the resistor 3 is input to the base of the transistor 2, and the drain voltage of the FET 1-transistor 1 is input from the transistor 5, which is the input terminal. The output terminal of the emitter follower is connected to the base of the transistor 2 through the capacitor 7.

Note that +vB is a power supply, and resistor 6 is a load resistance of the emitter follower.

In the amplifier circuit configured as above, the input terminal V1 of transistor 1 (F-ET) and the output voltage of transistor 5
Consider the ratio of 2, that is, the amplification degree of an amplifier circuit consisting of FET) transistor 1 and) FET transistor 5.

First, FET 1 - transistor 1 of the amplifier circuit shown in Figure 1
The amplification degree of the first stage consisting of V2 / Vl = gm R, 3...
...Represented by (1).

Here, gnl is the mutual conductance of the FET transistor 1, and R3 is the resistance value of the resistor 3.

Next, when the impedance of the capacitor 7 is ignored, the amplifier circuit consisting of the FET transistor 1 and the transistor 5 is rewritten as shown in FIG. 3.

Here, the parameters to be considered when calculating the amplification degree are:
FET) transconductance gm of transistor 1, hybrid parameters hie, h fe of transistor 5
and the hybrid parameter of transistor 2) lo
e and hf-e are omitted.

In addition, 11 is the drain current of FET 1 - transistor 1,
I2 is the base current of transistor 5, ■3j is the combined current flowing through resistors 3 and 6, and the resistance values of resistors 4 and 6 are R4 and R6, respectively.
Song...(2) I2= 工t R4/ (hto
+R4) , -9-0, -= (3) I3:I
2(hf,+t)+(II-I2)...
...(4) V2 = I3 (R3/R6)
---(5).

Here, R3/R6 is the parallel combined resistance value of resistors 3 and 6.

From the above formula, if we eliminate L and I3, ・・・・・・・・・(6) becomes.

Now, for example, R3/R6÷R3, R4/ (h +e
+ R, 4) If resistors 4 and 6 are selected to be 1/2, then fs V2/Vl ”:gm ” R3 (+ 1)
---(6'), and as is clear from the comparison with equation (1), in the embodiment of the present invention as shown in FIG. 2, compared to the conventional amplifier circuit shown in FIG. ("Kosen 1) The amplification factor will increase by a factor of two.

Moreover, the output impedance to the next amplification stage is rather reduced.

The above is for the case where the resistance value of the resistor 3 is made exactly the same as that of the conventional amplifier circuit shown in FIG. 1, and therefore the utilization rate of the power supply voltage does not decrease at all.

Furthermore, the explanation of the operation of the embodiment of the present invention described above can be made in exactly the same way even if the first stage is a bipolar transistor.

As explained above, according to the present invention, the load impedance of the amplification element constituting the first amplification stage becomes apparently high impedance, the degree of amplification increases, and the utilization rate of the power supply voltage is not impaired at all.

Further, since the output impedance to the next amplification stage does not become high, the high amplification degree is hardly affected by the input impedance of the next amplification stage.

Further, there is no need for any DC voltage loss in the next amplification stage.

Furthermore, due to the increased amplification degree, there is also the effect that the DC voltage applied to the first stage amplification element can be kept low.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a conventional amplifier circuit, FIG. 2 is a circuit diagram of an amplifier circuit according to an embodiment of the present invention, and FIG. 3 is a circuit diagram when the impedance of the second capacitor is ignored. 1...FET) transistor, 2 and 5...
...Transistor.

Claims (1)

[Scope of utility model registration request] In a two-stage amplifier circuit consisting of amplifier elements with mutually different polarities, the first stage amplifier element 1 and its load impedance 3
A resistor 4 is connected between the emitter follower 5 or a source follower whose input voltage is the voltage at a common connection point between the resistor 4 and the first stage amplification element 1, and an output terminal of the emitter follower 5 or the source follower and the An amplifier circuit characterized in that the base of an amplifying element 2 in the next stage of the two-stage amplifier circuit is connected through a capacitor 7, and the collector of the amplifying element 2 in the next stage is used as an output terminal.