JPS63165846U - - Google Patents

Info

Publication number
JPS63165846U
JPS63165846U JP1987058381U JP5838187U JPS63165846U JP S63165846 U JPS63165846 U JP S63165846U JP 1987058381 U JP1987058381 U JP 1987058381U JP 5838187 U JP5838187 U JP 5838187U JP S63165846 U JPS63165846 U JP S63165846U
Authority
JP
Japan
Prior art keywords
chip
attached
lead frame
tab
wire bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1987058381U
Other languages
English (en)
Japanese (ja)
Other versions
JP2524967Y2 (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1987058381U priority Critical patent/JP2524967Y2/ja
Publication of JPS63165846U publication Critical patent/JPS63165846U/ja
Application granted granted Critical
Publication of JP2524967Y2 publication Critical patent/JP2524967Y2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)
JP1987058381U 1987-04-17 1987-04-17 ワイヤボンデイング実装体 Expired - Lifetime JP2524967Y2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1987058381U JP2524967Y2 (ja) 1987-04-17 1987-04-17 ワイヤボンデイング実装体

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1987058381U JP2524967Y2 (ja) 1987-04-17 1987-04-17 ワイヤボンデイング実装体

Publications (2)

Publication Number Publication Date
JPS63165846U true JPS63165846U (enExample) 1988-10-28
JP2524967Y2 JP2524967Y2 (ja) 1997-02-05

Family

ID=30888901

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987058381U Expired - Lifetime JP2524967Y2 (ja) 1987-04-17 1987-04-17 ワイヤボンデイング実装体

Country Status (1)

Country Link
JP (1) JP2524967Y2 (enExample)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53105970A (en) * 1977-02-28 1978-09-14 Hitachi Ltd Assembling method for semiconductor device
JPS58143541A (ja) * 1982-02-22 1983-08-26 Hitachi Ltd 半導体装置
JPS622626A (ja) * 1985-06-28 1987-01-08 Nec Corp 半導体装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53105970A (en) * 1977-02-28 1978-09-14 Hitachi Ltd Assembling method for semiconductor device
JPS58143541A (ja) * 1982-02-22 1983-08-26 Hitachi Ltd 半導体装置
JPS622626A (ja) * 1985-06-28 1987-01-08 Nec Corp 半導体装置

Also Published As

Publication number Publication date
JP2524967Y2 (ja) 1997-02-05

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