JPS63164709A - Power supply reset circuit - Google Patents

Abstract

PURPOSE: To obtain a constant reset time against the change and the momentary interruption of a leading time of a power voltage by providing a circuit discriminating whether or not the power voltage is established up to a prescribed value so as to control a reset time. CONSTITUTION:When a voltage Vb is higher than a reference voltage Va (that is, the power voltage Vcc is established), since an output Vc of a comparator 5 inactivates a discharge circuit 4, the charging of a charging circuit 3 is first started. Only after a charging potential Vd of the charging circuit 3 is higher than the reference voltage Va, the output of an output circuit 6 is the same as the power supply voltage Vcc to release the reset. Since the power voltage establishing is monitored and the result reaches a prescribed potential in this way and then the charging of the charging circuit 3 is started, the reset time is made constant independently of the leading time of the power voltage.

Description

[Detailed Description of the Invention] [Summary] The present invention provides a power supply reset circuit that sets the operation of a circuit connected to the power supply to an initial state when the power supply voltage rises, and determines whether the power supply voltage has been established to a certain value. A circuit is provided to determine the reset time and control the reset time, so that a constant reset time is always obtained in response to changes in the power supply voltage rise time and instantaneous interruptions.

[Industrial Field of Application] The present invention relates to a power supply circuit, and more particularly to a power supply reset circuit that sets circuit operation to an initial state when powering up a device.

Since the power supply voltage of various devices generally rises with a certain time constant, the guaranteed operation voltage of digital ICs and the like that constitute the circuit differs depending on the model, so there are variations in the time at which they start operating. Therefore, it may not operate as intended, and to prevent this, it is generally necessary to add a power supply reset circuit to detect the rise of the power supply and reset all circuits after the power supply is established.

[Prior Art] FIG. 4 is a diagram showing a conventional power supply reset circuit.
．． 22 is a resistor, 23 is a Zener diode connected in series with the resistor 21 between the power supply Vcc and the ground potential, 24 is a capacitor connected in series with the resistor 22 between the power supply Vce and the ground potential, and 25 is the resistor 22. The switching diode 26 connected in parallel is a comparator that takes the voltage V1 at the connection point between the resistor 21 and the Zener diode 23 as a positive input, and uses the voltage V2 at the connection point between the resistor 22 and the capacitor 24 as a negative input and compares it to generate an output 3. It is.

In this conventional example, a reference voltage is created by a resistor 21 and a Zener diode 23.

Further, the resistor 22, the switching diode 25, and the capacitor 24 constitute a charging circuit with a constant time constant. Incidentally, 27 is an inverter for obtaining a voltage v4 which is an inversion of the voltage 3.

Next, the operation of this circuit will be explained with reference to FIG.

Now, assume that the power supply voltage V c (zero potential) ideally rises to Vs. Then, the voltage V2 rises with a time constant as the charging voltage of the capacitor 24. At this time, if voltage V2 is lower than voltage V1, output v4 becomes L (low) level, and as the potential of voltage v2 becomes higher than voltage V1, voltage V4 becomes H (high) level. Here, after a certain time tl after the power supply voltage Vcc rises, the reset state (V4: L level) of the connected circuit is released.

This tl can be freely set by setting the time constant by the resistor 22 and capacitor 24 and by the reference voltage v1.

On the other hand, when the power supply Vcc falls, the charge charged in the capacitor 24 by the switching diode 25 is immediately discharged, and the voltage V2 drops almost simultaneously with the power supply voltage Vcc, so that the output voltage 4 is reduced without any delay time. is L
level.

[Problems to be Solved by the Invention] The conventional power supply reset circuit described above has the following drawbacks. This will be explained using FIG.

In the waveform of FIG. 5, the power supply voltage Vee ideally rises, but as shown in FIG. 6, if the power supply voltage Vcc itself rises with a certain time constant, This shows that the time t2 in the case of , that is, the time from when the power supply voltage Vcc is established until the reset state is released varies depending on the rise time of the power supply voltage Vcc.

A similar situation occurs in the following cases.

If the power supply voltage Vcc is established,
If cc drops instantaneously and rises again immediately after being released from the reset state, the charging circuit made up of the resistor 22 and capacitor 24 will be charged again in the middle of discharging, so the reset will be performed after the power supply voltage Vcc is established. The time t3 until the state is released is even shorter than the above-mentioned time t2.

In this way, even with the same reset circuit, it is necessary to set the time constant of the charging circuit or the reference voltage v1 each time depending on the rise time of the power supply voltage, so there is a drawback that the same circuit cannot be used for the same purpose. there were.

Also, even if you set a certain time constant, avoid having a difference between the reset time that occurs when the power supply voltage rises (the time that it remains in the reset state) and the reset time that is output when the power supply voltage drops due to a momentary interruption of the power supply voltage, etc. It was a problem that could not be resolved.

Therefore, an object of the present invention is to realize a power supply reset circuit that can always provide a constant reset time.

[Means for Solving the Problems] FIG. 1 is a diagram showing the concept of a power supply reset circuit according to the present invention to achieve the above object, where 1 indicates a power supply voltage Vcc.
2 is a power supply voltage monitoring circuit that monitors a voltage obtained by dividing the power supply voltage Vcc; 3 is a charging circuit that charges the power supply voltage Vae with a predetermined time constant; 4 is a charging circuit 3 5 is a comparator that compares the reference voltage of the reference voltage generation circuit 1 with the power supply voltage division voltage of the power supply voltage monitoring circuit 2 and operates the discharge circuit 4 when the latter exceeds the former; Reference numeral 6 denotes an output circuit that compares the charging voltage of the charging circuit 3 with the reference voltage and generates a reset state signal until the former exceeds the latter.

[Function] In FIG. 1, the reference voltage generating circuit 1 has a constant voltage at a low power supply voltage, and generates a reference voltage v1. 1 source voltage monitoring circuit 2 divides the power source voltage Vcc
For example, voltage Vi is connected to the positive input of comparator 3, and voltage Vb is connected to the negative input.

Assume now that the power supply voltage Vcc rises with a certain time constant. @When the source voltage Vce is low, the voltage vb is lower than the voltage Va, so the output Vc of the comparator 5 is at the power supply potential. Therefore, the discharging circuit 4 operates and prohibits the charging circuit 3 from charging. Therefore, since the voltage Vd is at the earth's potential, the output of the output circuit 6 similarly becomes the earth's potential and exhibits a reset state.

From this state, when the voltage vb becomes higher in potential than the reference voltage ■a (that is, the power supply voltage Vec becomes established), the output Ve of the comparator 3 disables the discharging circuit 4, so the charging circuit is activated for the first time. 5 starts charging.

Then, it is not until the charging potential Vd of the charging circuit 5 becomes higher than the reference voltage Va that the output of the output circuit 6 becomes equal to the power supply potential Vc.
It becomes the same as c, and the reset state is released.

In this way, the established state of the power supply voltage is monitored by circuits 1 to 4, and the charging circuit 5 starts charging only when the result reaches a predetermined potential, so the reset time is constant regardless of the rise time of the power supply voltage. become.

[Example] FIG. 2 shows an example of the present invention, and FIG.
5 is a time chart illustrating the operation of the illustrated embodiment.

The reference voltage generation circuit in FIG. 1 is composed of a resistor 11 and a Zener diode 12 in FIG. I am getting the same voltage. Comparator 5 is shown as 15 in Figure 2, and its negative input is resistor 1.
3 and 14, and the positive input is connected to the connection point of resistor 11 and Zener diode 12, respectively. It is continued.

The charging circuit 3 includes a resistor 17 and a capacitor 18, and the discharging circuit includes a transistor whose collector and emitter are connected to the capacitor 18 and whose base is connected to the output of the comparator 15.
The output circuit 6 is a comparator 19.

Regarding the operation, assume that the power supply voltage Vcc rises with a certain time constant. The voltage VIL is constant when the power supply voltage Vcc is low, and the voltage vb is the power supply voltage V
The relationship between voltages Va and vb, which increase in proportion to ee, is set so that vb becomes equal to Va when the potential x reaches which it can be determined that the power supply voltage Vcc has been established.

When the voltage vb is lower than the reference voltage Va, that is, when the power supply voltage Vee is not established, the voltage Vc is at the potential of the power supply voltage Vec, so the output of the comparator 15 makes the transistor 16 conductive. . Therefore, since the voltage Vd is forcibly set to the earth's potential, the output vO of the comparator 19 becomes the earth's potential, resulting in a reset state.

Here, the power supply voltage Vcc is in an established state, that is, the voltage vb is V
When the voltage Vc becomes higher than a, the voltage Vc becomes the ground potential, and the transistor 16 is turned off. Therefore capacitor 18
charging starts. When the charging voltage Vd becomes higher than the reference voltage Va, the output VO of the comparator 19 becomes the power supply potential, and the reset state is released.

On the other hand, if the power supply voltage Vec is established and momentarily decreases, if the voltage vb becomes lower than Va, the voltage ■
c becomes H level, the transistor 16 is turned on again, and the capacitor voltage Vd that has been charged up to now is forcibly discharged and becomes the earth potential. From this state, the power supply voltage V
When cc increases, voltage Vcl starts charging again from the time when voltage vb becomes higher than reference voltage Va. Therefore, the time T from when the constant value (Vx) of the voltage Vcc is established until the reset state is released is the same as the initial time T.

[Effects of the Invention] According to the present invention, a reference voltage lower than the power supply voltage is set,
This is compared with the partial voltage proportional value of the power supply voltage, and when the latter exceeds the former, this is determined to be the time when the power supply voltage is established, and after that a reset state is created for a certain period of time, so the rise time of the power supply It is possible to always obtain a constant reset time regardless of the circuit used, there is no need to set the reset time each time depending on the circuit used, and even in the case of a momentary power outage, a constant reset time can be obtained, resulting in stable reset. This has the effect of providing a signal.

[Brief explanation of the drawing]

Fig. 1 is a principle block diagram of the power supply reset circuit according to the present invention, Fig. 2 is a block diagram showing an embodiment of the power supply reset circuit shown in Fig. 1, and Fig. 3 is an embodiment shown in Fig. 2. 4 is a block diagram showing a conventional power supply reset circuit, and FIGS. 5 and 6 are waveform diagrams for explaining the operation of the conventional example shown in FIG. 4. 1 and 2, 1 is a reference voltage generation circuit, 2 is a power supply voltage monitoring circuit, 3 is a charging circuit, 4 is a discharge circuit, 5. 1 is a comparator, 6 is an output circuit, 11 is a resistor, 12 represent Zener diodes, respectively. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (4)

[Claims] (1) A reference voltage generation circuit (1) that generates a reference voltage lower than the power supply voltage (Vcc), a power supply voltage monitoring circuit (2) that monitors a voltage obtained by dividing the power supply voltage (Vcc), and the power supply voltage (Vcc) at a predetermined time constant; a discharging circuit (4) for discharging the charging circuit (3); and a discharging circuit (4) for discharging the charging circuit (3). When the former exceeds the latter, a comparator (5) operates the discharging circuit (4), compares the charging voltage of the charging circuit (3) with the reference voltage, and outputs a reset state signal until the former exceeds the latter. A power supply reset circuit comprising: an output circuit (6) that generates; (2) The power supply reset circuit according to claim 1, wherein the reference voltage generation circuit (1) is constituted by a series circuit of a resistor (11) and a Zener diode (12). (3) The reference voltage and the power supply divided voltage are mutually set so that the output inversion time of the comparator (5) is earlier than the establishment time of the power supply voltage (Vcc). Or the power supply reset circuit described in item 2. (4) The power supply reset circuit according to any one of claims 1 to 3, wherein the output circuit (6) is a comparator (19).