JPS63161584A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To quicken entire operating speed without a delay of data transfer in the longest wiring by arranging plural shift registers in two lines and connecting all shift registers in a loop. CONSTITUTION:A ring pointer consists of k-sets of shift registers 1, 2 arranged in two lines, a 1st line consists of m-sets of shift registers 1, 2 and 1 2nd line consists of (k-m)-sets of shift registers 2, and each shift register 1, 2 has an input terminal 3, an output terminal 4, a clock terminal 5 and a set terminal 6. Then the shift registers 1, 2 of each line are connected in series to transfer data in opposite direction and the shift registers located at the same end of each line are connected in series to connect the entire shift register in series in a loop. Then the data is transferred at nearly the same speed as the shift register of the post stage in each shift register and the entire pointer is used as a ring pointer having a fast operating speed.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention is based on F I F O (first in fi
The present invention relates to a semiconductor integrated circuit device that can be used as a ring pointer in a memory or the like.

[Prior Art] FIG. 8 is a circuit diagram showing the configuration of a conventional ring pointer used in a FIFO memory or the like.

First, the FIFO memory will be explained using FIG. 2.

The FIFO memory stores incoming data and outputs previously stored data in response to output requests on a first-come, first-served basis. In FIG. 2, a memory cell array 10 is a ring pointer 2 in which a plurality of memory cells are arranged in a matrix of n bits×rows.
0 selects an arbitrary row of n-pit memory cells from the memory cell array 10, and the input driver 30 is placed in the selected n-pit memory cells.
Input data D I + to DI of n pits are inputted via the n-pits, or data in the selected n-pits memory cells is outputted as output data DO1 to DOo via the output driver 40. control circuit 50
controls the input driver 30 and output driver 40.

Next, the ring pointer will be explained using FIG.

This ring pointer uses the first shift register 1 with a reset terminal as the first stage shift register, and the second shift register 2 with a reset terminal in the subsequent stage (k-1).
They are arranged in rows, sequentially - columns. Each shift register 1, 2 has a data input terminal 3. Data output terminal 4. 5. and a reset terminal 6, and the output terminal 4 of each shift register 1.2 is connected to the input terminal 3 of the shift register 2 in the subsequent stage, and the output terminal of the shift register 2 in the second stage. 4 is connected to the input terminal 3 of the first stage shift register 1, and is connected in a loop as a whole. Further, the output terminal 5 and reset terminal 6 of each shift register 1.2 are commonly connected. Furthermore, address lines ADI to AD h are connected to the output terminals 4 of each shift register 1.2, and these address lines AD, to AD, are connected to the second
They are respectively connected to memory cells constituting each row of the memory cell array 10 of the FIFO memory shown in the figure.

The configuration of the first shift register 1 with reset terminal used as the first stage shift register 1 is shown in FIG.
FIG. 4 shows the configuration of the second shift register 2 with a reset terminal used as the shift register 2 of the second to second stages.

The first shift register 1 with reset terminal shown in FIG.
Transmitter 1 Engagement 2. Second inverter 13
．． 14, and a NOR gate 15, and has a data input terminal 3, a data output terminal 4, a clock terminal 5, and a reset terminal 6. In this first shift register 1 with a reset terminal, when the reset signal R8 inputted to the reset terminal 6 is at the rLJ level, the output signal φ applied to the reset terminal 5 is at the rHJ level or the rLJ level. Regardless of whether the data output terminal 4
The rHJ signal (“H” level signal) is output to the terminal. On the other hand, the reset signal R8 input to the reset terminal 6 is rH
When it is at J level, it operates as a normal shift register. That is, the data Dr input to the input terminal 3 is outputted to the output terminal 4 as the output data DO at the rising edge of the output signal φ input to the output terminal 5, and the data Dr input to the input terminal 3 is outputted as the output data DO to the output terminal 4. Its output data DO
Latch.

The second shift register 2 with reset terminal shown in FIG. 4 includes an NMOS transmission gate 21, a PMO8 transmission gate 22, an inverter 23,
Consists of an AND gate 24, with a data input terminal 3, a data output terminal 4, a clock terminal 5, and a reset terminal 6.
has. This second shift register with reset terminal 2
, the reset signal R8 input to the reset terminal 6 is r
When the signal reaches the LJ level, the rLJ signal (
Outputs a “S” level signal).

On the other hand, when the reset signal □゛R8 inputted to the reset terminal 6 is at the rHJ level, it operates as a normal shift register like the shift register 1 of FIG. 3.

Next, the fifth section regarding the operation of the ring pointer shown in FIG.
This will be explained with reference to the timing chart shown in the figure.

When the rLJ signal is input to the commonly connected reset terminal 6 of each shift register 1.2, the first stage shift register 1 outputs the rHJ signal, and the address line AD becomes r.
becomes HJ level, other shift registers 2 output rLJ signal, and other address lines AD2 to ADh become r
It will be LJ level.

Next, when the rHJ signal is input to the reset terminal 6,
At the rising edge of the OFF signal φ that is input to the OFF terminal 5, only the second stage shift register 2 outputs the rHJ signal, and only the address line A D t becomes at the rHJ level.

At this time, all other shift registers 1.2 are outputting rLJ signals.

At the next fall of the clock signal φ, the output of the second stage shift register 2 is latched to the rHJ level.

Furthermore, at the next rising edge of the clock signal φ, only the third stage shift register 2 outputs the rHJ signal, and only the address line AD becomes the rHJ level.

In the above operation, address line A is synchronized with clock signal φ.
D1. ADz ,...”, up to ADh are sequentially r
At the falling edge of the second clock signal φ, the output of the shift register in the first stage becomes rHJ and is latched to the bell, and then, at the rising edge of the next clock signal φ, the output of the shift register in the first stage becomes rHJ. Register 1 outputs the rHJ signal. In this way, unless a signal at the rLJ level is input to the reset terminal 6, as shown in FIG.
~AD, is selected.

[Problem to be Solved by the Invention] In the conventional ring pointer as described above, the wiring connecting the output terminal of the final stage shift register and the input terminal of the first stage shift register is connected to other shift registers. The wiring is longer than the wiring that connects the registers, so when transferring data from the final stage shift register to the first stage shift register, even if this wiring is aluminum wiring, parasitic capacitance and parasitic resistance This caused a large delay, which slowed down the overall operation speed of the ring pointer.

This invention was made in order to solve the above-mentioned problems, and it is possible to transfer data to the subsequent shift register at almost the same speed in any shift register, and to use it as a ring pointer with a high overall operating speed. The purpose of the present invention is to obtain a semiconductor integrated circuit device that can perform the following steps.

[Means for Solving the Problems] A semiconductor integrated circuit device according to the present invention has a plurality of shift registers arranged in two columns, and the shift registers in each column are connected in series so that data can be transferred in opposite directions. In addition, all the shift registers are connected in series in a loop by connecting the shift registers located at the ends of the same side of each column in series.

[Operation] The semiconductor integrated circuit device according to the present invention has a plurality of shift registers arranged in two rows, and all the shift registers are connected in series in a loop, so that the length of the wiring connecting each shift register can be reduced. All wiring is approximately equal, and no particular wiring becomes long. Therefore, the length of the longest wiring is shortened, avoiding a reduction in operating speed due to routing of wiring, and increasing the overall operating speed. Become.

[Example] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing the configuration of a ring pointer which is an embodiment of the present invention.

This ring pointer consists of shift registers 1.2 arranged in two columns, the first column consists of one shift register 1.2, and the second column consists of (k--) shift registers 2. Consisting of Each shift register 1.2 has input terminal 3
, output terminal 4, clock terminal 5, and reset terminal 6
When the clock signal φ input to the output terminal 5 rises, the data input to the input terminal 3 is output to the output terminal 4, and when the output clock signal φ falls, the data is output to the output terminal 4. The data being output is latched.

The output terminal 4 of each shift register 1.2 in each column is connected to the input terminal 3 of the shift register 2 in the succeeding stage, and each shift register 1.2 in the first column inputs data from the left side in the figure. The shift registers 2 in the second column are connected in series so that data can be transferred sequentially from the right side to the left side in the figure. Furthermore, the output terminal 4 of the rightmost shift register 2 in the first column, that is, the first stage shift register 2, is connected to the output terminal 4 of the rightmost shift register 2 in the second column, that is, the first +
The output terminal 4 of the shift register 2 at the left end of the second column, that is, the output terminal 4 of the shift register 2 at the left end of the second column, is connected to the input terminal 3 of the shift register 2 at the first stage. , that is, the first stage shift register 1
is connected to input terminal 3 of.

The first shift register 1 with a reset terminal shown in FIG. 3, which outputs the rHJ signal when the rLJ signal is input to the reset terminal 6, is used in the first stage of the first column. 2nd row of 1st row - 1st row and 1st + of 2nd row
The first to second stages use the second shift register 2 with a reset terminal shown in FIG. There is.

The output terminal 5 and reset terminal 6 of each shift register 1.2 are commonly connected.

Further, address lines ADI to AD are connected to the output terminal 4 of each shift register 1.2, respectively. These address lines A D + to ADk are connected to the FIF shown in FIG.
It is connected to the memory cells forming each row of the memory cell array 10 of O memory.

The memory cell array is arranged on the side of the shift register 1.2 in the first column of this ring pointer, and is connected to the address lines AD-++ to each shift register 2 in the second column.
AD is connected to the memory cells in each row of the memory cell array through each shift register in the first column.

The operation of this ring pointer will be explained with reference to the timing chart of FIG.

The reset signal R8 input to the reset terminal 6 is rLJ
When the level is reached, the first stage shift register 1 is rHJ
A signal is output, and the address line A D + - is rH.
It will be J level. At this time, all other shift registers 2 output the rLJ signal, and the address lines A D t to AD
h is all at the rLJ level.

Next, the reset signal ~R input to the reset terminal 6
8 rises to the rHJ level, the "T1" signal is transferred to the second stage shift register 2 at the rise of the clock signal φ, the address s A D + becomes the rHJ level, and the rise of the clock signal φ On falling, its rHJ level is latched.

In this way, unless a rLJ level signal is input to the reset terminal 6, the 5th ti! As shown in ll, the address line ADD is synchronized with the clock signal φ.

ADz, . . . , ADh are turned to rHJ L/bevel one by one in this order, and after the address line AD reaches the rHJ level, the process returns to address II AD + and the same process is repeated. In the above manner, the address lines AD, , AD
z, -..., AD,..., each row of the memory cell array 10 connected to ADh is selected in turn.

7t'L/suaADt, AD2, ..., ADi
' Nico (if arranged as in Example D, address a
AD+.

Since A D z , . . . , AD are selected in this order, in the memory cell array 10 (FIG. 2),
First, every other row from the left is selected in order, and after the address line AD is selected, every other row from the right is selected in order, and the address lines AD+, ADg- are selected in order.
..., ADh are always selected in this order, so F I
There is no problem with the F O (first in flrst out) operation.

In this way, by arranging a plurality of shift registers 1.2 in two columns and connecting all shift registers 1.2 in a loop, the final stage shift register and the first stage shift register are connected. Since the wiring is short like the wiring connecting other shift registers, there is no data transfer delay in the longest wiring, and the overall operating speed is increased.

FIG. 6 shows another embodiment of the present invention, in which the shift registers 1.2 in each column are connected in pairs close to each other, and each row is connected with a slight distance apart. Address lines connected to each set of shift registers 2 in the column are connected to each row at a corresponding position in the memory cell array 10 through each row of the shift registers 1.2 in the first column. It is.

Further, FIG. 7 shows still another embodiment of the present invention, in which the shift registers 1.2 in the first and second columns are arranged into sets of arbitrary irregular numbers, and each set in the second column is Each set of address lines connected to the shift register 2 is connected to each row at a corresponding position in the memory cell array 10 through each row of the shift register 1.2 in the first column.

The embodiments shown in FIGS. 7 and 8 also produce the same effects as the embodiment shown in FIG. 1.

Note that in the above embodiment, the memory cell array 10 is located on the side of the shift register 1.2 in the first column of the ring pointer 20, but the memory cell array 10 is divided into two, and one Shift register 1 of column
．． 2 and on the side of the shift register 2 in the second column. In this case, the memory cells on the side of shift register 1.2 in the first column are selected by shift register 1.2 in the first column, and the memory cells on the side of shift register 1.2 in the second column are selected.
The shift register 2 in the second column selects the memory cell on the side of .

Further, in the above embodiment, although the distinction between write operation and read operation was not mentioned, by using two ring pointers 20, writing and reading can be performed asynchronously.

Further, in the above embodiment, a case has been described in which the ring pointer 20 is used to select a row of the memory cell array 10, but the ring pointer 20 can also be used to select a column of the memory cell array 10.

Further, in the above embodiment, a shift register that operates with a one-phase clock signal is used as the shift register constituting the ring pointer 20, but a shift register that operates with a two-phase or multiphase clock signal may also be used. For example, when operating with two-phase polarity signals φ and φ, the transmission synchronization gate 2.2 for feedback is
2 (Figs. 3 and 4) are constructed with NMo5 transmission gates, and the gate electrodes of the transfer transmission gates 11 and 21 (Figs. 3 and 4) are connected to the gate electrodes of these NMOS transmission gates. Just give a clock signal opposite to that.

Note that the semiconductor integrated circuit device according to the present invention is a FIFO
In addition to being used as a memory ring pointer,
It is also used for other purposes as a circular register.

[Effects of the Invention] As described above, according to the present invention, by arranging a plurality of shift registers in two columns and connecting all the shift registers in a loop, the last stage shift register and the first stage shift register Since the wires connecting the registers are also short like the wires connecting other shift registers, there is no data transfer delay in the longest wires, and the overall operating speed is increased.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a schematic configuration diagram of a FIFO memory, Fig. 3 is a circuit diagram of a shift register with a first reset terminal, and Fig. 4 is a circuit diagram of a second reset terminal. A circuit diagram of a shift register with a terminal, FIG. 5 is a timing chart for explaining the operation of a ring pointer, FIG. 6 is a block diagram showing another embodiment of the present invention, and FIG. 7 is a diagram of still another embodiment of the present invention. Block diagram showing the embodiment, No. 8
The figure is a block diagram showing a conventional ring pointer. In the figure, 1 is a shift register with a first reset terminal, 2 is a second shift register with a reset terminal, 3 is a data input terminal, 4 is a data output terminal, 5 is an O-lock terminal,
6 is a reset terminal. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (3)

[Claims] (1) By arranging a plurality of shift registers in two columns, connecting the shift registers in each column in series in opposite directions, and connecting the shift registers located at the ends of the same side of each column in series. A semiconductor integrated circuit device consisting of all shift registers connected in series in a loop. (2) Each of the shift registers has a reset terminal, and one of the shift registers outputs a signal at a first logic level when a reset signal is input to the reset terminal; Claim 1, wherein the other shift register outputs a signal at a second logic level complementary to the signal at the first logic level when a reset signal is input to the reset terminal. The semiconductor integrated circuit device described in . (3) A patent characterized in that an address selection line is connected to each of the wirings connecting the shift registers, and the address selection line is connected to a predetermined memory cell of a memory cell array in a FIFO memory. A semiconductor integrated circuit device according to claim 1 or 2.