JP2009538488A - Computer circular register array - Google Patents

Abstract

  The stack processor includes a data stack including a T register and an S register, and eight fixedly wired bottom registers that function repeatedly in an annular pattern. The stack processor also includes a return stack including an R register and eight fixedly wired bottom registers that function repeatedly in an annular pattern. The circular register arrangement described herein avoids overflow and underflow stacking conditions.

Description

  The present invention relates to computers and computer processors, and in particular, to methods and means for further efficient utilization of stacks in a processor of a stack computer.

  A stack machine provides lower processor complexity than a complex instruction set computer (CISC) and lower overall system complexity than either a reduced instruction set computer (RISC) or a CISC machine. Thus, there is no need for a complicated compiler or cache control hardware for good performance. It also achieves competitive raw performance, and excellent performance at a given price in most programming environments. Their first successful field of application is in real-time embedded control environments, surpassing other system design approaches with a wide range of advantages. In the past, stacks were mostly held in memory, but in new stack machines, each stack is held in a separate memory chip or on-chip memory area. These stack machines offer extremely fast subroutine call capabilities and excellent performance in interrupt handling and task switching.

  However, there was no hardware detection of overflow and underflow stacks. A stack overflow occurs when there are not enough available registers and push on the stack continues, overwriting the bottom registers. Stack underflow occurs when all registers are emptied, and continued pops of the stack will lead to unintended or inaccurate results. Other stack processors use a stack pointer and memory management to flag an error condition when the stack pointer deviates from the memory range assigned to the stack. U.S. Pat. No. 6,057,097 to Zahir et al. Discloses a register stack engine that provides sufficient registers for the register stack in memory and provides more available registers in a stack overflow event. The register stack engine also delays the microprocessor in the event of a stack underflow until the engine can recover the appropriate number of registers.

  Patent document 2 by Mr. Story discloses a method of comparing an operation result with a threshold value. However, this approach does not distinguish between the result when rounded to a threshold (which results in an overflow exception) and the result when exactly equal to the threshold. Another method disclosed by Mr. Stori identifies an overflow or underflow condition by reading and writing a hardware flag.

US Pat. No. 6,367,005 US Pat. No. 6,219,685

  However, the instructions must be executed in sequence, and the instruction following the register read / write cannot proceed to the next until the read / write operation is completed, causing a delay operation.

  In a stack in memory, an overflow or underflow can overwrite a stack item or use a stack item that is not intended to be part of a stack. There is a need for an improved method of reducing or eliminating overflow and underflow in the stack.

  SUMMARY OF THE INVENTION It is an object of the present invention to provide an apparatus and method in which the data stack and return stack of a dual stack processor are not wired in an array that is accessed in memory using a stack pointer, but instead are fixed wire accessed by separate dedicated shift registers. That is.

  Another object of the present invention is to reduce or eliminate overflow or underflow of the data or return stack.

  Another object of the present invention is to minimize the electrical connection length between single bit (1 bit) stack registers of a bidirectional stack register, thereby minimizing the required driver size and buffering. Minimizing what to do.

  These and other objects are achieved by the invention described herein, in which the conventional stack is replaced by a register array that functions repeatedly in a circular (circular) pattern. . This repeated circular pattern is achieved by the use of connected bidirectional shift registers, which include a plurality of 1-bit shift registers that are electrically interconnected in every other pattern. This configuration prevents reading from outside the stack and prevents reading an unintended empty register value.

  The dual stack processors described above can function as stand-alone processors or can be used in an interconnected computer arrangement with several other same or different processors.

  The present invention will be described with reference to the figures, wherein like reference numerals represent like or similar elements in the figures. While the invention will be described in connection with embodiments that achieve the objectives of the invention, the invention may be embodied in various forms without departing from the spirit and scope of the invention as claimed herein without departing from the spirit and scope of the invention as claimed herein. It will be appreciated by those skilled in the art.

  The embodiments and variations of the present invention described in this specification and / or shown in the drawings are illustrative and do not limit the scope of the present invention. Unless otherwise stated, individual aspects and elements of the invention are omitted as long as they are within the spirit and scope of the claimed invention, since the invention is intended to be amenable to many variations. Or various modifications.

  FIG. 1 is a block diagram showing a schematic layout of a dual stack computer 12 used in the present invention. The computer 12 is typically a self-contained computer having its own RAM 24 and ROM 26.

  Another basic component of the computer 12 is a return stack 28, which includes an R register 29, an instruction area 30, an arithmetic logic unit (ALU or processor) 32, a data stack 34, and a decode for decoding instructions. And a logic unit 36. The computer 12 is a dual stack computer having a data stack 34 and another return stack 28. In general, those skilled in the art are familiar with the operation of a stack-based computer, such as the computer 12 of this embodiment.

  In the embodiment described herein, the instruction area 30 includes a number of registers 40, including an A register 40a, a B register 40b, and a P register 40c in this example. In this embodiment, the A register 40a is a full 18-bit register, while the B register 40b and the P register 40c are 9-bit registers.

  The present invention discloses a stack computer processor, in which the data and return stacks include a register array that functions in a cyclic iteration or circular pattern. The data stack and return stack are not memory arrays accessed by the stack pointer in many prior art computers.

  FIG. 2 discloses an embodiment of an 18-bit data stack according to the present invention. The top two registers in the data stack are an 18-bit T register and an 18-bit S register. The rest of the data stack contains 8 additional 18-bit hardware registers, in this example labeled S2-S9. The circular registers S2 to S9 can operate without the T and S registers. However, the presence of at least the S register in combination with the registers S2-S9 provides faster access circuitry and optimal timing conditions, thus providing a higher operating speed of the annular register arrangement. In addition, the S register acts as a buffer between the addressable registers S2-S9 and the rest of the processor system. This provides timing independence between registers S2-S9 and the rest of the processor system.

  This embodiment also includes a bidirectional shift register that includes a plurality of 1-bit shift registers. The number of 1-bit shift registers is equal to the number of bottom side stack registers S2 to S9 arranged below the S register. Each 1-bit shift register is connected to the corresponding stack register S2-S9 shown in FIG. Every other 1-bit shift register is electrically interconnected in a pattern, so that the stack registers S2 to S9 are connected as shown in FIG. 2 to S2, S4, S6, S8, S9, S7, S5, S3, It works with the sequential annular interconnect pattern given by S2. This sequential selection of the bottom stack register works repeatedly in an annular pattern. Interconnection wiring for a 1-bit shift register does not extend beyond three or more adjacent shift registers, avoiding the need for long wiring to connect the bottom shift register to the top shift register Yes. These shorter wires require smaller drivers and buffering is also minimized. The given example uses 8 additional stack registers for a circular register array. However, other combinations of bottom registers used in multiples of 4 can be used.

  FIG. 2 also discloses a read bus and a write bus that interconnect the registers S2 to S9, as well as the T and S registers. Each one-bit shift register of the bi-directional shift register is connected to the corresponding bottom stack register in the S2-S9 array, where only one bit of the shift register is on at one time, while all other This bit is read as zero. At power up, the shift register is initialized and exactly one bit must be set to 1 and the other bit must be set to zero. In the given embodiment, the top bit of the shift register points to register S2 for reads and to the adjacent adjacent register S4 for writes as shown by the dashed line in FIG. The remaining bits of the 1-bit shift register are similarly connected to corresponding ones of registers S2-S4, but other wiring is not shown to avoid unnecessarily obscuring the drawing.

  A push down stack with a cell depth of 10 is formed by resistors T, S and S2-S9. Since the eight bottom registers form a circular buffer, the hardware wraps rather than overflows or underflows. Don't expect to put more than 10 items and then return them all, but you can keep taking a copy of the last 8 items from the bottom of the stack forever. There is no underflow in the sense that it is not an error. If the program continues to take values from the stack, the bottom 8 will be read many times, so replicating the pattern of 8 (or 4 or 2 or 1) words is the fastest way. is there.

  Similarly, there is no stack overflow in the sense that the stack pointer allows the stack to go elsewhere. If the stack is finite and more than 10 items are put there, only the last 10 remains, and what is stored after the first 10 overwrites one of the registers S2-S9. There is no need to "initialize" the stack to a preset location, just declare the stack empty by starting to use it from anywhere in the stack.

  FIG. 3 is an enlarged view of each register in the data or return stack. Each 18-bit register includes 18 latches numbered 0-17. There is a set of 18 input pass gates (numbered 0-17), each selectively connecting a corresponding one of the 18 latches to the write bus. There is a set of 18 output pass gates (numbered 0-17), each selectively connecting a corresponding one of the 18 latches to the read bus. The input pass gate is controlled by a write control signal asserted on the input control line via an inverting amplifier connected to the input control line (write line in FIG. 2), and the output pass gate is controlled by the output control line (read in FIG. 2). Controlled by a read control signal asserted on the output control line via an inverting amplifier connected to the line).

  FIG. 4 discloses the 18-bit return stack of the present invention. The top register of the return stack is an 18-bit R register, and eight additional 18-bit hardware registers are located below the R register, here numbered R1-R8. The eight registers R1 to R8 on the bottom side function in a pattern of every other pattern as a repeating annular array, similar to the data stack described above.

  The annular register arrays R1 to R8 can operate without an R register. However, the presence of the R register in combination with the registers R1-R8 provides faster access circuitry and optimal timing conditions, thus providing faster operation of the annular register arrangement. In addition, the R register acts as a buffer between addressable registers R1-R8 and the rest of the processor system, and timing independence between addressable registers R1-R8 and the rest of the processor system. I will provide a.

  This embodiment also includes a bidirectional shift register that includes a plurality of 1-bit shift registers. The number of 1-bit shift registers is equal to the number of additional bottom registers R1-R8 located below the R register. Each 1-bit shift register is connected to a corresponding one of the bottom-side stack registers R1 to R8 shown in FIG. The 1-bit shift registers of the bidirectional shift register are electrically interconnected in a pattern of every other, so that the registers R1 to R8 of the stack are R1 → R3 → R5 → R7 → as shown in FIG. It works with a sequential annular interconnection pattern given by R8 → R6 → R4 → R2 → R1. This sequential register selection operates repeatedly in an annular pattern. Shift register interconnect wiring does not extend beyond three or more adjacent 1-bit shift registers, and the need for long wiring to connect the bottom 1-bit shift register to the top 1-bit shift register Avoid. These shorter wires require smaller drivers and buffering is also minimized. In the given embodiment, eight additional return registers have been disclosed, but multiple combinations of other bottom multiples of four can be used in an annular register arrangement. The read bus and the write bus interconnect the registers R1 to R8. Each 1-bit register of the shift register is connected to a corresponding stack register in the R1-R8 array. Only one bit of the shift register is on (read as 1) at a time, while all other bits are read as zero. At power up, the shift register must be initialized so that exactly one bit contains a 1 and all other bits contain a zero. In the given embodiment, the top bit of the shift register points to register R1, i.e., reads R1 and writes to the interconnected adjacent register R3.

  In the present invention, there is no hardware detection for stack overflow or underflow conditions. Typically, prior art processors use a stack pointer and memory management, etc., to flag an error condition when the stack pointer goes outside the memory area assigned to the stack. In the case where the stack is managed in memory, an overflow or underflow will overwrite the stack item or use something other than intended. However, since the bottom register of the present invention functions in an annular arrangement, the stack cannot overflow or underflow from the stack area. Instead, the toric array simply wraps around the register array. Since the stack has a finite depth, pushing to the top side of the stack means that it is overwritten on the bottom side. In a given embodiment, a push operation of 10 items or more on the data stack or a push operation of 9 items or more on the return stack has the knowledge that such an operation results in an item being overwritten on the bottom side of the stack. Must be.

  It is the software's responsibility to keep track of the number of items on the stack and do not try to push more items than each stack can hold. The hardware does not detect item overwrites at the bottom of the stack, nor does it flag as an error. It should be noted that the software can obtain the benefits of an annular arrangement at the bottom of the stack in several ways. As one example, the software can simply assume that the stack is “empty” at any time. Since old items are pushed down towards the bottom and disappear at the bottom as the stack fills, there is no need to clear old items from the stack, so the program is empty without initialization. It can be assumed that there is.

  Another advantage that can be used is that register items are reused without the restriction that the item must be reloaded for reuse. The bottom eight items in these stacks can be read or written in a loop that takes advantage of stack wrapping. After two data stack reads, registers T and S have two entries from the toric array of the bottom eight stack registers. After 8 more reads, registers T and S are reloaded with the same value read again from below using stack wrap. There is no limit as to how many times these eight items can be read out of the stack on the sequence, in which case there are no constraints that must be duplicated or that they must be rewritten to the stack. A cycle algorithm over a set of parameters that can be repeated on 8, 4 or 2 cells on the data or return stack will iterate over if the bottom register is just wrapping and a stack error is not intended. Can be read from the stack.

  Although the present invention has been described in the embodiment for the data stack and return stack of a dual stack 18-bit processor, other bit size processors may be used by the present invention.

  The annular register arrangement described above has been described for a single dual stack processor. However, multiple iterations in a stack processor including an annular register arrangement as described above can be used in a self-contained computer arrangement such as the computer arrangement 10 shown in FIG. The computer array 10 includes a plurality (24 in the example) of computers 12 (also often referred to as “cores” or “nodes” in the example of the array). In the embodiment shown, all of the computers 12 are located on a single die 14. According to one embodiment of the present invention, each of the computers 12 is typically a computer that functions independently. Computers 12 are interconnected by a plurality of interconnect data buses 16. It is within the scope of the present invention that other interconnection means may be used for that purpose, but in this embodiment data bus 16 is a bi-directional, asynchronous and high speed parallel data bus.

  Computer 12e is an example of one that is not on the periphery of computers 12 in array 10. That is, the computer 12e includes four computers 12a, 12b, 12c and 12d which are adjacent at right angles. This grouping of computers 12a-12e is used as an example in connection with a more detailed discussion of communication between multiple computers 12 in array 10. As can be seen from FIG. 5, an internal computer such as computer 12 e comprises four other computers 12 that can communicate directly via bus 16. In the discussion that follows, the principles discussed apply to all of the computers 12, which is that the computer 12 on the periphery of the array 10 is in direct communication with only the other three or the corner computer 12 is a computer. Excluded by being in direct communication with only the other two 12 units.

  FIG. 6 further refines a portion of FIG. 5 and shows only some of the computers 12, and in particular includes computers 12a-12e. The diagram of FIG. 6 also reveals that each of the data buses 16 includes a read line 18, a write line 20, and a plurality (18 in this example) of data lines 22. The data line 22 has the ability to transfer all bits of one 18-bit instruction word simultaneously, usually in parallel.

  In accordance with the method of the present invention, a computer 12, such as computer 12e, is ready to receive data from an adjacent computer 12 by setting one, two, three, or all four of its lead lines high. The Similarly, the computer 12 can set one, two, three or all four of its light lines 20 high.

  When one of adjacent computers 12a, 12b, 12c or 12d sets the write line 20 between itself and the computer 12e high, if the computer 12e already sets the corresponding read line 18 high The word is transferred on the dedicated data line 22 from the computer 12a, 12b, 12c or 12d to the computer 12e. Next, the transmitting computer 12 opens the write line 20, and the receiving computer (12e in this example) pulls the write line 20 and the read line 18 low. In the subsequent operation, the transmission side computer 12 is notified that the data has been received.

  As shown in FIG. 1, in this embodiment of the invention, computer 12 has four communication ports 38 that communicate with adjacent computers 12 as described above. The communication port 38 is a three status driver having an off status, a reception status (for a drive signal to the computer 12), and a transmission status (for a drive signal to the outside of the computer 12). If a particular computer 12 is not within the array (FIG. 5), such as the computer 12e example, one or more of the communication ports 38 are not used in that particular computer for at least the above purposes. However, the communication port 38 that abuts the edge of the die can have additional circuitry designed for internal or dedicated external use of the computer 12 and can be used as an external FO port 39 (see FIG. Operate as 5). Examples of such external I / O ports 39 include, but are not limited to, USB (General Purpose Serial Bus) ports, RS232 serial bus ports, parallel communication ports, analog to digital and / or digital to analog conversion ports, And many other possible variations. In FIG. 5, an “edge” computer 12 f is represented with a dedicated interface circuit 80 that communicates through an external I / O port 39 that includes an external device 82.

  Various modifications may be made to the invention without changing its value and scope. For example, although the present invention has been described herein as using a particular computer 12, many or all aspects of the present invention can be readily adapted to other computer designs, other computer arrangements, and the like.

  Although aspects of the present invention have been disclosed herein primarily in the context of communication between multiple computers 12 in an array 10 on a single die 14, the same principles and methods may be used or modified from use to use. Thus, other device-to-device communication such as communication between the computer 12 and its dedicated memory or between the computer 12 in the array 10 and an external device can be achieved.

  Similarly, although the invention has been disclosed herein for a dual stack processor, the invention can also be implemented for a single stack processor or a processor including two or more stacks.

  All of the above are only some of the available examples of the present invention. Those skilled in the art will readily recognize many other variations thereof, and such variations may be made without departing from the spirit and scope of the present invention. Accordingly, the disclosure herein is not intended to be limiting and the appended claims should be construed to encompass the full scope of the invention.

It is a block diagram which shows the schematic layout of a stack computer. FIG. 4 illustrates a data stack according to one embodiment of the present invention. FIG. 4 is a diagram showing more details of a single register in the stack. FIG. 6 illustrates a return stack according to one embodiment of the present invention. FIG. 2 illustrates a computer arrangement that includes multiple interactions of the computer of FIG. FIG. 6 shows the computer portion of FIG. 5 and more details of the interconnect data bus of FIG.

Claims (42)

A stack computer,
A memory for storing data and codes;
A processor for processing the data and the code;
And a plurality of fixed-wiring registers that can be used as a stack by the processor.   The computer of claim 1, wherein the plurality of registers are accessed in normal or reverse order according to a predetermined repetitive sequence. If the plurality of registers are accessed in the normal order, after the last register of the registers is accessed in the sequence, the first register of the registers is accessed in the sequence;
The last register of the registers is accessed after the first register of the registers is accessed when the plurality of registers are accessed in the reverse order. The computer according to 2.   A bi-directional shift register including a plurality of single bit registers, wherein the output of each single bit register is connected to at least partial control access to an associated one of the registers, thereby The computer of claim 1, wherein a direction shift register functions as a stack pointer that shifts bits along the single bit register.   The last of the plurality of single bit registers is connected to the first of the plurality of single bit registers, so that the plurality of single bit registers are bits shifted along themselves. The computer of claim 1, wherein the computer provides an annular path. A stack computer processor,
A data stack having at least one data register;
A return stack having at least one return register;
And the data stack and the return stack can accommodate an 18-bit instruction word.   The processor of claim 6, wherein the at least one data register comprises a top stack (T) register.   The processor of claim 7, wherein the at least one data register has a second position in a stack (S) register.   The processor according to claim 6, characterized in that the at least one return register comprises a top register (R).   The processor of claim 6, wherein the data stack further comprises a hardware register array.   The processor of claim 6, wherein the return stack further comprises a hardware register array.   The processor according to claim 10, wherein the array functions in an annular pattern.   The processor according to claim 11, wherein the array functions in an annular pattern. A method of operating a computer processor, comprising:
An input step of inputting a plurality of instruction words into a corresponding plurality of instruction cells in the processor;
Processing steps for processing the plurality of instruction words,
A method wherein there is no instruction overflow or underflow as a result of the input step and the processing step.   15. The method of claim 14, wherein the input step fills all available instruction cells.   The method of claim 15, wherein the inputting step further inputs additional instructions after all available instruction cells have been filled.   The method of claim 16, wherein the input step and the processing step occur without using a software implemented pointer.   15. The method of claim 14, wherein the processing step repetitively reuses the plurality of instruction words without reloading the plurality of instruction words. A computer processor,
A register array;
A shift register;
The shift register has a plurality of 1-bit shift registers interconnected by electrical wiring, and the number of the plurality of 1-bit shift registers is equal to the number of registers in the register array. Processor.   The processor of claim 19, further comprising at least one register disposed on the register array.   The processor of claim 19, wherein the register array includes a read bus and a write bus interconnecting the array.   The processor according to claim 19, wherein the register array functions in an annular pattern.   21. The processor of claim 20, wherein the register array is stacked.   24. The processor according to claim 23, wherein the one-bit shift registers are interconnected in a pattern every other line by the electric wiring.   The processor of claim 19, wherein the processor is a data stack.   The processor of claim 25, wherein the register array comprises eight data registers.   26. The processor of claim 25, wherein the register array includes multiples of 4 data registers.   The processor of claim 14, wherein the processor is a return stack.   The processor of claim 28, wherein the register array has eight return registers.   30. The processor of claim 28, wherein the register array comprises a multiple of four return registers. A computer processor,
A register array;
A bidirectional shift register fixedly wired to the register arrangement;
Including
The processor further comprising a plurality of 1-bit shift registers interconnected by electrical wiring, wherein the number of the 1-bit shift registers is equal to the number of registers in the register array.   32. The processor of claim 31, further comprising at least one register disposed on the register array.   32. The processor of claim 31, wherein the shift register functions as a hardware pointer for the register array.   32. The processor of claim 31, further comprising a read bus and a write bus.   32. The processor of claim 31, wherein each of the plurality of 1-bit shift registers corresponds to a dedicated register in the register array.   36. The processor of claim 35, wherein only one shift register of the plurality of 1-bit shift registers is activated at a time.   32. The processor of claim 31, wherein the register array includes a read bus and a write bus interconnecting the array.   32. The processor of claim 31, wherein the plurality of 1-bit shift registers are interconnected with electrical wiring to minimize driver size and buffering.   32. The processor of claim 31, wherein all of the electrical wiring extends between three adjacent 1-bit shift registers.   40. The processor of claim 39, wherein the register array comprises eight registers.   32. The processor of claim 31, wherein the processor has a data stack.   32. The processor of claim 31, wherein the processor has a return stack.

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