JPS63160096A - Semiconductor memory circuit - Google Patents

Abstract

PURPOSE:To attain the operation in response to various system needs by selecting word lines of a number designated by a line number signal sequentially so as to clear the data of a connected memory cell thereby clearing lots of data at a high speed. CONSTITUTION:A multi-line selection control section 12 receives a multi-line clear signal MLS, a start lines signal ADS by an address signal AD and a line number signal LN and outputs a multi-line selection signal. A row decoder 2, according to the selection signal, selects word lines 3 of a number designated by the signal LN from a word line 3 of the signal ADS sequentially. On the other hand, a row decoder 6 selects all digit lines 7 according to the signal MLS and connects it to a bus of an I/O switch data bus 8 to send the clear data DTC from the data buffer circuit 9 to a memory cell of the cross points of the selected word lines 3 and digit line 7 thereby clearing the data in each memory cell.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to semiconductor memory circuits, and in particular to semiconductor memory used in high-speed memory systems such as image signals that require the ability to clear large amounts of data at once. Regarding circuits.

[Conventional technology]

Conventionally, in this type of semiconductor memory circuit, data in memory cells on one word line of a memory cell array can only be cleared in one cycle.

For example, a RAM port with a 64K x 4 bit configuration and 2
A dual-port memory circuit for graphic image systems having a serial port I with a 56x4 bit configuration.
256 each of 4 bits of 1 word line J of RAM port,
There is one that handles a total of 1024 memory cells at the same time6
(Ainiscisi Digest of Technical Hehers (l5SCC0IGEST OF T
ECIINICAL PAPERS>, pages 48-49,
February, 19116).

[Problem that the invention seeks to solve]

The conventional semiconductor memory circuit described above is configured to clear data in memory cells on at most one word line in one cycle. The clearing speed is becoming insufficient in such cases. In addition, for the high frequency access required by graphic display systems, dual ports are used as dedicated memory.
This requirement has been met by combining high-speed serial operation with dynamic RAM. Among these, when switching from one screen to the next in a large-screen, high-resolution system that requires clearing the entire screen, it would be ideal to be able to clear all the contents of the memory cells at once; In this semiconductor memory circuit, only one line can be cleared at most, which has the disadvantage that it takes too much time.

In addition to frequent access, various screen operations are emerging as system needs. multi screen,
An example is patterning, in which case it is required to be able to operate within a certain range and to operate at high speed or rearward. Conventional semiconductor memory circuits do not yet meet this requirement.

An object of the present invention is to provide a semiconductor memory circuit that can clear a large amount of data at high speed and can meet various system needs.

[Means for solving problems]

The semiconductor memory circuit of the present invention inputs a basic clock signal including a row-related control signal, a column-related control signal, and a write control signal that have a specific timing relationship different from a normal write/read cycle, and generates a multi-line clear signal. a multi-line clear mode setting section for outputting a multi-line clear mode setting section; a multi-line selection control section for inputting the multi-line clear signal, start line signal and line number signal and outputting a multi-line selection signal; A row decoder selects a predetermined word line according to an address signal, and when a multi-line selection signal is input, sequentially selects a plurality of word lines in accordance with this multi-line selection signal, and a column address for the normal write/read cycle. a column decoder that selects a predetermined digit line according to a signal and connects it to a data bus to transmit data; and when the multi-line clear signal is input, selects all digit lines and connects it to the data bus to transmit clear data; , a memory cell array that includes memory cells at the intersections of the word lines and digit lines, respectively, and writes and reads data to and from memory cells at the intersections of the selected word lines and digit lines.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

When the basic clock signal CK including the row-related control signal RAS, column-related control signal CAS, and write control signal 1 is in a normal write/read cycle, the timing signal output from the timing signal generation circuit 10 causes the address signal AD to be A predetermined word line 3 is selected by the row address inverter 1 and the row decoder 2 according to the row address A D R of the address signal AD, and a predetermined digit line is selected by the column address inverter 5 and the column decoder 6 according to the column address A D c of the address signal AD. 7 is selected and I10 switch
It is connected to the data bus 8. The data DT then passes through the data buffer circuit 9.1/Q4, the data bus 8, and the column decoder 6 to the memory cell array 4.
is written to or read from the memory cell at the intersection of the selected word line 3 and digit line 7.

Row-related control signal RAS and column-related clock signal C, which have a specific timing relationship different from normal write/read cycles.
When K is input, the multi-line clear mode setting section 11 first determines that this basic clock signal CK is in the multi-line clear mode and outputs the multi-line clear signal MLS.

Next, the multi-line selection control section 12 receives the multi-line clear signal MLS, the start line signal ADS based on the address signal AD, and the line number signal LN based on the address signal AD, and outputs a multi-line selection signal.

According to this multi-line selection signal, the row decoder 2
The number of word lines 3 specified by the line number signal LN is sequentially selected from the word lines 3 of the start line signal A D s. On the other hand, the column decoder 6 selects all digit lines 7 according to the multi-line clear signal MLS, connects them to the data bus of the I10 switch data bus 8, and selects the clear data DTc input from the data buffer circuit 9. Word line 3. The signal is transmitted to the memory cells at the intersections of the digit lines 7, and the data in these memory cells is cleared.

Therefore, the data of all the memory cells connected to the number of word lines 3 specified by the line number signal LN are cleared at once, and a large amount of data can be cleared at high speed.

Note that the line number signal LN can also be input using a data DT signal instead of using the address signal AD.

FIG. 2 is a waveform diagram of various signals when the line number signal LN is input as a data DT signal.

In a normal write/read cycle, column-related control signals such as AS are activated after the row-related control signal τT'J is activated, but in the multi-line clear mode, the timing relationship is reversed.

〔Effect of the invention〕

As explained above, the present invention sequentially selects the word lines specified by the number of lines signal from the word line specified by the start line signal, and data contents of all memory cells connected to these word lines are selected. By adopting a configuration that clears a large amount of data, it is possible to clear a large amount of data at high speed, and there is an effect that data clearing can be performed immediately in response to various system needs, especially screen data operations.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a waveform diagram of various signals when a line number signal is input as a data signal. 1... Row address inverter, 2... Row decoder,
3... Word line, 4... Memory cell array, 5...
・Column address inverter, 6...column decoder, 7.
...Digital line, 8...I10 switch data bus, 9...Data buffer circuit, 10...Timing signal generation circuit, 11...Multi-line clear mode setting section, 12...Multi-line selection control section.

Claims (1)

[Claims] Multi-line clear mode setting unit that inputs basic clock signals including row-related control signals, column-related control signals, and write control signals that have specific timing relationships different from normal write/read cycles and outputs multi-line clear signals. a multi-line selection control section that inputs the multi-line clear signal, start line signal and line number signal and outputs a multi-line selection signal; a row decoder that sequentially selects a plurality of word lines in accordance with the multiline selection signal when a multiline selection signal is input; and a row decoder that selects a predetermined digit line in accordance with a column address signal in the normal write/read cycle. a column decoder that connects to the data bus to transmit data, selects all digit lines when the multi-line clear signal is input, connects to the data bus to transmit clear data, and each of the word lines and digit lines. 1. A semiconductor memory circuit comprising: a memory cell array having a memory cell at each intersection of the selected word line and digit line, and writing and reading data to and from the memory cell at the intersection of the selected word line and digit line.