JPS6150296A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To shorten the time required for writing of a semiconductor memory by dividing a memory cell array into a plurality of blocks and writing the same data into each block. CONSTITUTION:When CS of a control signal becomes L, MOS transistors Tx1, Tx2 and Ty1, Ty2 are turned off and MOS transistors Tx3, Tx4 and Ty3, Ty4 are turned on. Thereby, the most significant input signals Bxn, -Bxn and Bym, -Bym of X. and Y address decoder 12, 13 are respectively set at earthing potential. Under this condition, when the least significant X address Ax1 is changed to X address Xn-1 and the least significant Y adddress Ay1-1 is changed to Y address Ayn-1, all memory cells can be selected. At this time, a memory cell array is quadrisected and to each block of the memory cell arrays 11a-11d, the same data is written and accordingly the writing time can be shortened to 1/4.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor memory device that performs high-speed writing of arbitrary data, shortening test time, high-speed initialization of stored data, and the like.

[Technical background of the invention]

Generally, a memory cell selection section of a semiconductor memory device is configured as shown in FIG. 2, for example.

In the figure, reference numeral 11 denotes a memory cell array in which memory cells are arranged in a matrix, and each memory cell in this memory cell array 1 is selected by the outputs of an X address decoder 12 and an X address decoder 13. Above X
Address signals Ax, ~AX are sent to the address decoder 12.
From the X address buffer circuit 14 to which n is supplied, this 1
. A1,7. . A8, ~□,. Yo14. . , 3゜1~BXn and the opposite phase signal H~; are supplied, and the above X
The address signal Ay+ "' is sent to the address decoder 13.
A) Y address signal supplied with rm Tsufa circuit 1
5, signals B, l to Bym having the same phase as the address signals Ay1 to Ay7B and signals B and 1 to Bym having the opposite phase are supplied from the address signals Ay1 to Ay7B, respectively.

In the above configuration, the X address is n1ll, Y
When there are m addresses, it is possible to select any one of the 2 (m+n) memory cells provided in the memory cell array 11. " or "0" data is input, and this data is written into the selected memory cell by controlling the write signal, etc. [Problems in the Background Art] By the way, all the memories in the first part of the memory cell array 11 In order to write arbitrary data to a cell, it is of course necessary to select all memory cells, and this requires changing the address twice. For this reason, it takes a long time to write data, and as the storage capacity increases in the future as the degree of integration increases, the writing time will become even longer. Additionally, there are also problems such as an increase in the time required for testing and initializing the memory cell.

[Purpose of the invention]

This invention was made in view of the above circumstances,
The purpose is to provide a semiconductor memory device that can write data at high speed and also shorten the time required for testing and initialization.

[Summary of the invention]

That is, in the present invention, in order to achieve the above object, the !X address buffer circuit to the X address decoder! A switching means is provided for each of the uppermost signal line α and the uppermost signal line from the Y address 22fu circuit to the X address decoder, and when these switching means are cut off, the uppermost signal line to the X address decoder and the X address decoder is By setting the potential of the memory cell array to a predetermined potential, dividing the memory cell array into multiple blocks, and selecting all the memory cells in one divided block, the same data can be simultaneously applied to each block. This is the one that writes .

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, components 419 that are the same as those in FIG. 2 are given the same reference numerals, and detailed explanation thereof will be omitted. The highest signal line 16 from the X address buffer circuit 14 to the X address decoder 12. ．． 16. The sources and drains of N-channel MOS trannostars Tx+ + Tx2 are connected above, and the N-channel ~10S transistors Tx5*Tx4 are connected between the drains of these MOS trannostars Tx+l Tx2 and the ground. The drain and source are connected respectively. The conduction of the ~10S transistor TX2 is controlled by the control signal C8K, and the conduction of the MO8) transistor Tx4 is controlled by a signal obtained by inverting the control signal C8 by the inverter 17.

Similarly, on the upper signal images 171 and 172 of U from the Y address buffer circuit 15 to the Y address decoder 13, an N channel type MOS)
The drains and drains of N-channel type MOS transistors Ty51 and Ty4 are connected between the drains and the ground points of these MOS transistors Ty, , T, and 2, respectively. Then, the above MOS transnostar T aj+Ty
2 is conduction-controlled by the control signal C8, and the MOS
) Runnostar'ry5, Ty4 is the above control signal C
The conduction is controlled by a signal obtained by inverting 8 with an inverter 17y.

Next, the operation in the above configuration will be explained. When the control signal C8 is at the high (pan n'') level, the MOS
transistors TXI r Tz2 and Tyl.

When Ty2 is on, MOS transistor TX5
rT unit 4, Ty5, and Ty4 are turned off.

According to this 1, X at...2 f circuit 74
The outputs Bx1 to Bxn and Bx1 to Bxn are all supplied with the X address decoder ri;tVc, and the outputs By1 to B7m and By1 to Bym of the Y address buffer circuit 15
are all supplied to the Y address decoder 13. Therefore,
The same operation as the circuit shown in FIG. 2 is performed.

On the other hand, when ;h1] control signal CS goes low ('L'') level, MOS transistors TX1+TX2 and T
yl r']'y2 is off state, MOS) Languta Tx5.

Tx4, Ty3, and Ty4 are turned on. As a result, the highest input signal BXn l"Xn of the X address decoder 12 and the J of the Y address decoder 13
The upper input signals 87mlB)'m are respectively set to the ground potential ("L" level).In this state, the X address signals n- from the lowest X address signal 1 to the one before the highest 1 and also change the Y address signal n-1 from the lowest Y address signal to the one before the highest, all memory cells can be selected.At this time, the memory cell array 11 is divided into four. The memory cell arrays lla to 116 of each divided block are in the same state as the address signal AXI.
-Azn-1+ The same r-t is written in accordance with changes in Ay1 to A and n-1, respectively. Therefore, the data writing time can be reduced to 1/4.

This is particularly advantageous when writing the same data to all memory cells, such as initializing data stored in memory cells or writing test data.

Although the above embodiment describes the case where the memory cell array 1 is divided into four parts, it is also possible to provide a similar circuit on the signal line one line before the top of the It is also possible to divide the file into 16 parts. It's a moat, MOS) Lannostar Tx5 r Tx4
and Ty6r Ty4 source is grounded, but X, Y
Depending on the bottom of the address decoder 12, 13, it may be connected to a power source. In this case, MO8) In order to prevent the PH# level from decreasing due to the threshold voltage of the transistor, the P/rOS transistor 'rx31 TX4 and Ty3*Ty4
It is sufficient to use a P-channel type for the inverter 1.
7x and J 7y are unnecessary. Furthermore, MOS) Rannosta Tx, , Tx2 and Tyl r Ty2
Although the N-channel type has been described, it is of course possible to use a P-channel type, and the type may be selected as appropriate depending on the system configuration.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to obtain a semiconductor memory device that can write data at high speed and also shorten the test time and the time for f and rJ periodization.

[Brief explanation of the drawing]

FIG. 1 shows a semiconductor memory device 1 according to an embodiment of the present invention.
FIG. 2 is a circuit diagram showing a memory cell selection section of a conventional semiconductor memory device. Horn...Memory cell array, 12...X address decoder, 13...Y address decoder, 14...X
Address buffer circuit, 15...771718277
Circuit, 161 1J62 +I71 r172...
・Top signal line, A11 to AXn...X address signal, A I to Aym・Y address signal, TX1+T
M0...MOS) transistor (first switching means), TX3 r TX4...MOS) rannostar (second switching means), Tyl, Ty2.
...MOS) Runnostar (third switching means)
, Tys, 'ry,...MOS) Runnostar (fourth switching means), C3...+1ilI control signal.

Claims (4)

[Claims] (1) Memory cell array and the X of this memory cell array
An X address decoder that selects an address, a Y address decoder that selects a Y address of the memory cell array, and an X address signal is supplied to the X address decoder, and a signal that is in phase with the X address signal and a signal that is in reverse phase are supplied to the X address decoder. an X address buffer circuit, a Y address buffer circuit to which a Y address signal is supplied and which supplies a signal in phase with the Y address signal and a signal in opposite phase to the Y address decoder, and a signal from the X address buffer circuit to the X address decoder. a first switching means provided on the uppermost signal line and whose switching is controlled by a control signal;
When the first switching means is cut off, a second switching means connects the highest signal line to the X address decoder to a potential supply source, and a second switching means connects the highest signal line from the Y address buffer circuit to the Y address decoder. a third switching means provided on the line and whose switching is controlled by the control signal; and when the third switching means is cut off;
and fourth switching means for connecting the highest signal line to the Y address decoder to a potential supply source. (2) The semiconductor memory device according to claim 1, wherein each of the first to fourth switching means comprises a MOS transistor. (3) The second and fourth switching means each include:
2. The semiconductor memory device according to claim 1, comprising an N-channel MOS transistor, and wherein the potential supply source is a ground potential. (4) The second and fourth switching means each include:
2. The semiconductor memory device according to claim 1, comprising a P-channel MOS transistor, and wherein the potential supply source is a power supply potential.