JPS63159847U - - Google Patents
Info
- Publication number
- JPS63159847U JPS63159847U JP5329287U JP5329287U JPS63159847U JP S63159847 U JPS63159847 U JP S63159847U JP 5329287 U JP5329287 U JP 5329287U JP 5329287 U JP5329287 U JP 5329287U JP S63159847 U JPS63159847 U JP S63159847U
- Authority
- JP
- Japan
- Prior art keywords
- type
- package
- view
- external connection
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 6
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/49105—Connecting at different heights
- H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Description
第１図はこの考案の一実施例による半導体装置
のもので、第２図、第３図はそれぞれ従来よりＤ
ＩＰ型とＰＬＣＣ型として知られている半導体装
置の例を示す外形図で、それぞれａは平面図、ｂ
は側面図、ｃは底面図、ｄは正面図、ｅは断面図
である。 図において、１は半導体パツケージ、２，２ａ
は外部接続端子、３は半導体チツプ、４はワイヤ
、５はダイパツド。なお、図中同一符号は同一又
は相当部分を示す。
のもので、第２図、第３図はそれぞれ従来よりＤ
ＩＰ型とＰＬＣＣ型として知られている半導体装
置の例を示す外形図で、それぞれａは平面図、ｂ
は側面図、ｃは底面図、ｄは正面図、ｅは断面図
である。 図において、１は半導体パツケージ、２，２ａ
は外部接続端子、３は半導体チツプ、４はワイヤ
、５はダイパツド。なお、図中同一符号は同一又
は相当部分を示す。
Claims (1)
- 半導体装置において、１つのパツケージにＰＬ
ＣＣ（Ｐ１ａｓｔｉｃ Ｌｅａｄｅｄ Ｃｈｉｐ
Ｃａｒｒｉｅｒ）型とＤＩＰ（Ｄｕａ１ Ｉｎ
―Ｌｉｎｅ Ｐａｃｋａｇｅ）型の両方の外部接
続端子を設けたことを特徴とする半導体装置。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5329287U JPS63159847U (ja) | 1987-04-08 | 1987-04-08 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5329287U JPS63159847U (ja) | 1987-04-08 | 1987-04-08 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63159847U true JPS63159847U (ja) | 1988-10-19 |
Family
ID=30879220
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5329287U Pending JPS63159847U (ja) | 1987-04-08 | 1987-04-08 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63159847U (ja) |
-
1987
- 1987-04-08 JP JP5329287U patent/JPS63159847U/ja active Pending