JPS6416699U - - Google Patents

Info

Publication number
JPS6416699U
JPS6416699U JP1987109967U JP10996787U JPS6416699U JP S6416699 U JPS6416699 U JP S6416699U JP 1987109967 U JP1987109967 U JP 1987109967U JP 10996787 U JP10996787 U JP 10996787U JP S6416699 U JPS6416699 U JP S6416699U
Authority
JP
Japan
Prior art keywords
conductor
chip
package
die pad
die
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1987109967U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1987109967U priority Critical patent/JPS6416699U/ja
Publication of JPS6416699U publication Critical patent/JPS6416699U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)

Description

【図面の簡単な説明】
第1図は本考案の一実施例の断面を示す図、第
2図は同じく、その要部のリードフレームを示す
上面図、第3図は同じくパツケージ段階の要部に
おける断面図、第4図は従来のICパツケージの
断面の一例を示す図、第5図は同じく、従来のI
Cパツケージにおけるリードフレームの一例を示
す上面図である。 1……ICチツプ、2……ダイパツド、3……
リード、4……ワイヤー、5……パツケージ樹脂
、6……導体、7……接続部。

Claims (1)

    【実用新案登録請求の範囲】
  1. ダイパツド上にダイボンドしたICチツプを有
    するICパツケージにおいて、上記ICチツプの
    上面部分に導体を設け、この導体を上記ダイパツ
    ドに電気的に接続した構成を有することを特徴と
    するICパツケージ。
JP1987109967U 1987-07-20 1987-07-20 Pending JPS6416699U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1987109967U JPS6416699U (ja) 1987-07-20 1987-07-20

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1987109967U JPS6416699U (ja) 1987-07-20 1987-07-20

Publications (1)

Publication Number Publication Date
JPS6416699U true JPS6416699U (ja) 1989-01-27

Family

ID=31346695

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987109967U Pending JPS6416699U (ja) 1987-07-20 1987-07-20

Country Status (1)

Country Link
JP (1) JPS6416699U (ja)

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