JPS63158915A - Decoding circuit - Google Patents

Abstract

PURPOSE:To correct a code detecting error in probability of 3/4, by inputting a bi-phase code series and a clock with a cycle of T/2 by the sum of two pulse strings, and providing a feedback circuit to a code error detection circuit and a phase switcher. CONSTITUTION:The bi-phase code series (a), when generating an error, is inputted to the shift register 11 of a detection circuit 12. The output pulse strings (b) and (c) of a frequency 1/2-demultiplier 1 are inputted to a code detector 3 and an AND gate 4. The output of the gate 4 is set as the clock input of the register 11 with the cycle of T/2. The circuit 12 outputs a phase switching signal (e) via gates 6-9 when three bits of the same logic are continued to appear on the code series (a), and no signal is outputted at a fourth bit. Meanwhile, the decision output (f) of a code detecting part 3 is inputted to an exclusive OR gate 10 with the signal (e), and no switching 2 is performed due to an output (g)=0, and erroneous judgement 3 is corrected. Code errors of 12 events out of all of 16 events generated by the bi-phase signal can be detected by such constitution, and the probability of 3/4 can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a decoding circuit for a bi7 code.

[Conventional technology]

When the original code is a 1-bit code with a bit period T and a logical person (where A is either logical ``1'' or logical rOJ), this original code is converted into a logical AA (or 1jA) with a bit period T/2.
A) converted into a 2-bit code is called a biphase code. As a decoding circuit for decoding such a biphase code to an original code, there is a conventional decoding circuit shown in FIG. In FIG. 5, (1) is a 172 frequency divider, and (21 is a phase switcher).

(3) is a code detector 6 Also, FIG. 6 is a waveform diagram showing the waveforms of each part of the circuit in FIG. 5.
((:).

(d) Ha! The waveforms of each signal indicated by a*b+C*d in Fig. 5 are shown. The number 1.0 at the top of FIG. 6 indicates the logic rIJ, rOJ of each bit of the original code;
It is assumed that the time interval between the vertical dotted lines in the figure is T, and a 1-bit original code is inserted between them. In the example shown in FIG. 6, a 1-bit original code with bit period T and logic A is converted into a 2-bit biphase code with bit period T/2 and logic AA, and this is transmitted as signal a to the code detector (3: Extract the pulse of T/2 from the signal a and use it as the signal P.
/2 frequency divider +11, and as the output of the 1/2 frequency divider (II), a pulse train C with a period T and a mutual phase difference T/2 is obtained. will be temporarily referred to as the second pulse train.Pulse train S,
c is input to the phase switch 121 and the phase switch (21
A code detector (3) performs code detection using the pulse train output from the code detector (3). By the way, the pulse train is cal/2
Since the pulse train is generated by the frequency divider (1), it is not determined which pulse train comes in the first half of the period T. In Fig. 6, the pulse train C comes in the first half of the period T and the pulse train C comes in the second half, and in this case, an output as shown in Fig. 6 (dl) can be obtained as the output d of the sign detector (3). .If one period T
The pulse train comes in the second half.

When the pulse train C comes in the first half of the period T, the signal logic of the pulse train and the pulse train C match at the time when the logic of the original code changes from "1" to "0" or from "0" to "1". do. When such a match is detected, the sign detector (
3) switches the outputs of the pulse trains i and c in the phase switch (2). The correct code d is output from the code detector (3).

[Problem that the invention seeks to solve]

Even if the phase order of the first pulse train and the second pulse train C is normal, if a code error occurs, this pulse train is
There is a drawback that the order of the pulse train b+c may be reversed by erroneously determining that this is due to an error in the phase order of pulse train c.

The present invention was made to solve such problems, and an object of the present invention is to obtain a decoding circuit that can correct a code detector's erroneous judgment when a code error occurs with a probability of 374. .

[Means for solving problems]

The decoding circuit according to the present invention inputs a biphase code sequence and clocks a pulse train with a period T/2 generated from the sum of the first pulse train and the second pulse train, and when a code error occurs, and a code error detection circuit that sends out a phase switching signal.

This code error detection circuit and a feedback circuit for inputting the phase switching signal sent from the code detector to the phase switching device are provided.

[Effect]

In this invention, when a code error occurs in the biphase code sequence, the code detector erroneously determines that an error has occurred in the phase order of the pulse train C and sends out a phase switching signal. By sending out the phase switching signal from the code error detection circuit, it is possible to correct the erroneous judgment of the code detector with a probability of 3/4.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention, and in FIG. 2, (!1.(2)+(3L az b
e Cld and P indicate the same parts or signals as the same symbols in FIG. 5, (41, (51 is an AND gate,
+61. (71, (81 is F, XCLUSIVE
NOR gate! 91. QllIHEXCLU
SIVE OR gate, α1lij shift register.

az is a code error detection circuit. Also, e is the output signal of the code error detection circuit 03, and f is the output signal 9g of the code detector (3), which is a phase switching signal input to the phase switching device (2). FIG. 2 is a waveform diagram showing the waveforms of each part of the circuit in FIG. 1, and FIG. FIG. 3(a) shows another example in which the waveform pattern is different from that shown in the figure.

tel, (fl, (glti a + 6 in Figure 1)
The waveform of each signal is shown as +f+g.

Next, the circuit operation will be explained using FIG. 1, FIG. 2, and FIG. 3. The waveform shown by the dotted line in FIG. 2 is the waveform when a code error occurs in the biphase code sequence (a).

This waveform is transmitted to the code detector (31) and the code error detection circuit fi.
It is input to the shift register αυ in 2. The first pulse train C and the second pulse train C which are the outputs of the 1/2 frequency divider
is the sign detector 13+.

AND gate (4: input to AND gate (4)
The output of is a pulse train with period T/2, and the shift register aυ
This is the clock input. The inside of the code error detection circuit @ is as follows.
It is composed of the above-mentioned shift register and gate circuits (6) to (9), and when three consecutive bits of the same logic are present in the bi-7 code series, a phase switching signal is sent to the output e. If 4 bits have the same logic in succession, a phase switching signal is sent out at the 3rd bit, and no phase switching signal is sent out at the 4th bit. The waveform indicated by the dotted line in FIG. 2 1el is a phase switching signal that is sent out when the biphase code sequence generates a code error as shown in FIG. 2 1al. On the other hand, the code detection section (3) detects a violation of the code rule due to a code error in a pulse train.

Figure 2 (f
), the waveform shown by the dotted line is sent to the output f.

Since eef is input to the exclude-jig-or gate, the output gdO is not input, and no phase switching signal is input to the phase switch (2), which means that the erroneous judgment at the sign detector (37) has been corrected. In the case of Fig. 3, the output e of the code error detection circuit aZ is delayed by 1 bit compared to the output f of the code detector (31), so the phase switching signal to the 1 phase switch (21) has the waveform shown in Fig. 3g. After making a mistake in the phase order of the 1-bit pulse train c, the phase order must be corrected again. Figure 4 shows possible events when a biphase code sequence generates a code error. .

In Fig. 4, events A to 1 have biphase codes 1 and O.
is incorrectly O20 or 1.1, and event A has a leading sign of 0, 1 . Event B has a trailing sign of 0.1° and a leading sign of 0.1°.
1. The trailing code is 1. O0 event C has a leading code of 1. If the O1 trailing code is 0.1°, the leading code is 1 and the O1 trailing code is 1.
．． This is the case of 0. Also, the bi7Aze code 0.1 is O20 or 1. In case of IK mistake,
Event E has a leading sign of 0.1. The succeeding sign is 0.1°, the preceding sign of event F is 0.1°, the succeeding sign is 1.00, and the preceding sign of event G is 1.0. Event H has a trailing sign of 0.1° and a leading sign of 1.0.
This is the case where the subsequent code is 1.0. There are 12 events marked with a circle in FIG. 4 when the same logic continues for three or more bits after the code wAb is generated. It is also assumed that the possibility of a code error such as the one marked with HH is zero. Also,
The Qo=Qs bits of each event are output in parallel every 4 bits from the shift register (lυ) shown in FIG.
Since the total number of events is 16 times and 12 times, the probability is 3/4.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to correct a code error when the code detecting section makes an erroneous judgment and switches the phase order of the pulse train.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a decoding circuit showing an embodiment of the present invention, FIG. 2 is a diagram showing waveform examples of various parts of the circuit of FIG. 1,
FIG. 3 is a diagram showing another example of waveforms of each part of the circuit in FIG. 1,
FIG. 4 is a waveform diagram when a code error occurs, FIG. 5 is a block diagram showing a conventional decoding circuit, and FIG. 6 is a diagram showing an example of waveforms of each part of the circuit of FIG. In the figure (gate is 172 frequency divider, (2I is phase switch, (31
is a sign detector, (4) and (5) are AND gates,
(61, (7), (8)dEXCLUSIVE NO
R goo), (9), (let! EXCLU8IVEOR
The gate, aυ is a shift register, and (L3 is a code error detection circuit. In the drawings, the same or corresponding parts are denoted by the same reference numerals.

Claims (1)

[Claims] In a decoding circuit when transmission data is bi-phase encoded and transmitted, there is a phase difference of T/2 between a first pulse train of period T from the transmitted bi-phase code sequence and this first pulse train. means for generating a second pulse train with a period T; a phase switch which receives the first pulse train and the second pulse train and switches outputs of the first pulse train and the second pulse train; Means for generating a phase switching signal when the phase code sequence is a signal input, the first pulse train and the second pulse train outputted from the phase switch are clock inputs, and the phases of the two pulse trains are incorrectly selected. a code detector having the above-mentioned biphase code sequence as a signal input, and a pulse train with a period T/2 generated from the sum of the above-mentioned first pulse train and the above-mentioned second pulse train as a clock input, and a code error occurs. and a feedback circuit that inputs the phase switching signal sent from the code detector and the code error detection circuit to the phase switching device. decoding circuit.