SU1676104A1 - Linear codes latent errors detector - Google Patents

Abstract

The invention relates to computing and communication technology and can be used to determine undetectable errors of linear codes. The aim of the invention is to improve the speed of the device. The device for detecting undetectable errors of linear codes contains register 1 of memory, block 2 of coding, decoder 3, counters 4.1 ... 4.N undetectable errors, selector 5 of states of the input register, element 6, trigger 7, element 9 delay, elements 11.1 ... 11.N matches, information bus 12, clock bus 13, output bus 14. The goal is achieved by introducing the elements of AND 8, the code converter 10 and the formation of new functional connections. In the description of the acquisition, the structural electrical circuits of the coding unit 2, the selector 5 of the states of the input register, the code converter 10 are also given. 1 Cp. Of the file, 4 ill. cl

Description

12

#

ON X

ABOUT

about

The invention relates to computing and communication technology and can be used to determine undetectable errors of linear codes.

The purpose of the invention is to increase the speed of the device.

Figure 1 shows the structural electrical circuit of the device; 2 is the same, coding block 2; fig. 3 - the same, selector 5 states of the input register; figure 4 is the same, the code Converter 10.

The device (Fig. 1) contains a memory register 1 connected in series, a coding unit 2 and a decoder 3, counters 4.1 ... 4.N undetectable errors. The outputs of register 1, bitwise, are connected to the inputs of the selector 5 of the state of the input register, the second output of which is connected to the first input of the first element I b, and the first output to the first input of the trigger 7, the output of which is connected to the first input of the second element 8 and the output of which is connected to the input of the element 9 delay. The outputs of the decoder 3 are bitwise connected to the inputs of the code converter 10. The output of delay element 9 is connected to the first inputs of elements 11.1 ... 11.N matches, the information inputs of register 1 are bitwise connected to the information bus 12, the second inputs of And 6 and 8 elements with clock bus 13, the outputs of counters 4.1 ... 4.N with output bus 14. The counting inputs of counters 4.1 ... 4.N are connected to the outputs of elements 11.1 ... 11.N, respectively, the second inputs of which are bitwise connected to the outputs of the code converter ten.

Coding unit 2 (Fig. 2) is executed on EXCLUSIVE OR elements 2.1 ... 2.4 and the codeword register 2.5 with corresponding links.

The selector 5 (FIG. 3) contains an OR-NOT 5.1 element and an AND 5.2 element, the outputs of which are respectively the first and second outputs of the selector 5, and the inputs are bitwise connected to the inputs of the selector 5.

The code Converter 10 (Fig, 4) contains the elements OR 10.1 ... 10. (N-1), and the inputs of the element OR 10i are connected with. the inputs of the code converter 10, corresponding to the binary code combinations with the number of ones equal to I, where I 1,2 (N-1), and the output - with

The 1st output of the code converter 10, the input of which, corresponding to a single binary code combination, is connected to its Nth output.

The device works as follows.

Before operation, the 4 undetectable error counters are set to the zero state. The device operation time is divided into M cycles (M is the number of code

words of the analyzed code). At the j-th cycle (j 1, M), the input of register 1 in the parallel code is a binary record of the number (j-1), which is a block of information symbols for the j-ro code word. AT

0 the first cycle of operation, when a zero combination is written in the input register 1, a single signal is generated at the output of the element OR NOT 5.1 in the selector 5 of the states of the input register, which translates trigger 7

5 to the one state and the unlocking element AND 8 for the passage of clock pulses to the elements 11. The delay element 9 provides the delay of the clock pulses by the time required for the signals to pass in the code converter 10.

The following operations are performed on each cycle.

The signals from the outputs of the input register 1 are fed to the inputs of the register 2.5 code

The 5 words in the coding block 2, both directly and through the elements 2,1, 2.2, 2.3 and 2.4, as a result of which the code word symbols are formed in the register 2.5 of the code word.

0 From the outputs of register 2.5, the signals arrive at the information inputs of the decoder 3, as a result of which at one of its outputs a signal appears that is fed to the input of one of the elements OR

5 10.1 ... 10 (N-1) in block 10, if the inputs of the decoder 3 in the code combination were one unit, then the signal goes to the OR 10.1 element, if two - to the OR 10.2 element, etc., if all N units in code

0 combinations are then to the second input of the element 11, N. From the output of the element OR 10i, the signal passes to the element AND 11 | (second entrance), where I 1, (N-1). With the arrival of clock delay element 9, one is opened

5 of the elements And 11, the signal passes to the counting input of the corresponding counter 4 undetectable errors.

Claims (2)

The process continues until the input of the selector 5 does not match the combination of all the units, which corresponds to the M-cycle (M is the number of code words of the analyzed code). When such a combination occurs at the input of the And 5.2 element, the latter is unlocked and opens the And 6 element, at the height of which a single signal also appears, which translates the trigger 7 into the zero state. As a result, the AND 8 element is locked, the clock pulses on the delay element 9 are not passed, the error counting is stopped. To continue the work, it is necessary to read the readings of the counters 4 and submit a zero combination to the inputs of register 1. The full cycle of operation in the proposed device is completed in M cycles, and in the known, in M-N cycles, which allows to increase the speed of the device. Claim 1. Device for detecting undetectable errors of linear codes, containing an input memory register, informational inputs of which are connected to the information bus, and outputs are identical to the inputs of the coding block and status selector of the input memory register, the first output of which is connected with the first trigger input, the second output with the first input of the first element I. whose output is connected to the second trigger input, as well as N counters of undetectable errors, whose outputs are connected to the output bus, and The first to the Nth counters of undetectable errors are connected to the outputs of the first to the Nth coincidence elements, the first inputs of which are combined, as well as the decoder, the delay element, and the clock bus. device speed, in It has a second AND element and a code converter, the first through Nth outputs of which are connected to the second inputs of the first to Nth matching elements, respectively, and the inputs are bitwise with the decoder outputs, the first input of the first matching element being connected to the output of the delay element whose input is connected to the output of the second element I. The first input of which is connected to the trigger output, and the second input to the second input of the first element AND and the clock bus, and the output of the coding block of the bit are connected to the information in odes decoder. 2. Device pop.1, characterized in that the code converter contains (N-1) OR elements, and the inputs of the 1st OR element are connected to the code converter inputs corresponding to the binary code combination with the number of ones equal to I, where I 1 , 2 (N-1), a the output of the i-ro element OR is connected to the 1st output of the code converter, and the input of the code converter corresponding to the unit binary code combination is connected to the Nth output of the code converter. I j 1 Ljaj 5.1 First Exit block 5 5.2 second exit .. her block 5 & 2n-1 Fig.Z Figm