JPS63158863A - Static ram - Google Patents
Static ramInfo
- Publication number
- JPS63158863A JPS63158863A JP62280512A JP28051287A JPS63158863A JP S63158863 A JPS63158863 A JP S63158863A JP 62280512 A JP62280512 A JP 62280512A JP 28051287 A JP28051287 A JP 28051287A JP S63158863 A JPS63158863 A JP S63158863A
- Authority
- JP
- Japan
- Prior art keywords
- film
- high resistance
- polycrystalline
- layer
- psg
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000003068 static effect Effects 0.000 title claims description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 10
- 230000001590 oxidative effect Effects 0.000 claims abstract 3
- 238000004519 manufacturing process Methods 0.000 claims description 3
- 238000000034 method Methods 0.000 abstract description 11
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 9
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 9
- 239000011574 phosphorus Substances 0.000 abstract description 9
- 230000007774 longterm Effects 0.000 abstract description 6
- 238000010438 heat treatment Methods 0.000 abstract description 4
- 238000005530 etching Methods 0.000 abstract description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 6
- 229910052681 coesite Inorganic materials 0.000 abstract 3
- 229910052906 cristobalite Inorganic materials 0.000 abstract 3
- 239000000377 silicon dioxide Substances 0.000 abstract 3
- 235000012239 silicon dioxide Nutrition 0.000 abstract 3
- 229910052682 stishovite Inorganic materials 0.000 abstract 3
- 229910052905 tridymite Inorganic materials 0.000 abstract 3
- 229910052581 Si3N4 Inorganic materials 0.000 abstract 2
- 230000006866 deterioration Effects 0.000 abstract 1
- 239000010408 film Substances 0.000 description 34
- 230000003647 oxidation Effects 0.000 description 12
- 238000007254 oxidation reaction Methods 0.000 description 12
- 230000008595 infiltration Effects 0.000 description 5
- 238000001764 infiltration Methods 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 4
- 239000012528 membrane Substances 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 2
- 239000004575 stone Substances 0.000 description 2
- 229920000742 Cotton Polymers 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 230000002747 voluntary effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は多結晶シリコンで形成された菩抵抗を内臓する
スタテックＲＡＭ（ＲＡＮＤＡＭ、ＡＣｃｌｓＢ、ＭＩ
ＭＯＲＹの略、以後ＲＡＭと記す。DETAILED DESCRIPTION OF THE INVENTION The present invention provides a static RAM (RANDAM, ACclsB, MI
Abbreviation for MORY, hereinafter referred to as RAM.
）に関し、Ｎ！１抵抗部上に残す絶縁膜に関すｂ６現在
、高抵抗を内蔵したスタテックＲＡＭＫは全体をＭｆｆ
ｉのＭＯＳ）ランジスタで溝底し？？Ｎ −ＭＯＳのス
タテックＲムＭと、過通回路を相補形ＭＯＢｈ９：／ジ
スタテ構故し７？：Ｃ−ＭＯＢＩ））ｘタテツクＲムＭ
がある。両者とも従来は、高抵抗部分に特別に絶縁膜を
残すと論う工うな事をしてｂない。第１〜４図に一例を
示し、以下に従来の方法につ−て説明する。) Regarding N! 1 Regarding the insulating film left on the resistor part b6 Currently, the static RAMK with built-in high resistance is entirely Mff.
i's MOS) Does the transistor bottom out? ? Complementary type MOBh9:/disstate structure of N-MOS static RM and pass-through circuit 7? :C-MOBI)) x vertical RM M
There is. Conventionally, neither of them has taken any measures such as leaving a special insulating film on the high-resistance portions. An example is shown in FIGS. 1 to 4, and the conventional method will be explained below.
第１図に示すように、１はＰ型８シ単結晶基板。As shown in FIG. 1, 1 is a P-type 8-Si single crystal substrate.
２ ａ ７ （−ル）” ｓｓｏ、 膜−３はゲーｈ
”（Ｏａ８１ｗｅ ４は多結晶ｆＩ（層、５は熱酸化ｔ
Ｈｏｓ膜、６はＳらＮ４膜である参ＩＩＩ図のように形
放した後％ ＣＶ Ｄ Ｅｌ（Ｏ。2 a 7 (-ru)” sso, film-3 is game h
”(Oa81we 4 is polycrystalline fI (layer, 5 is thermal oxidation t
Hos film, 6% CV D El (O.
膜７を形放し必要な部分を残してエツチングする。The film 7 is left unshaped and etched leaving only the necessary parts.
その後、リンをイオン打込みしてソース、ドレインのＮ
拡散層８を形放し、必要な部分の多結晶Ｓｉ層にもト°
−プする。多結晶Ｂ（層のドープしない所で高抵抗９を
形匠する。又、第３図に示すよ５ Ｋ ＆ ＣＶ ”
’ｔ ’ 雪７ ＃ ８１１Ｎ４ Ｋ ６− ｍ％酸化
ＥＤｏ。After that, ion implantation of phosphorus is performed to form the source and drain N.
The diffusion layer 8 is released, and the polycrystalline Si layer is also heated in the necessary areas.
-Pop. Polycrystalline B (forms a high resistance 9 in the undoped part of the layer. Also, as shown in Figure 3, 5K &CV"
't' Snow 7 #811N4 K 6-m% oxidized EDo.
膜５をそれぞれエツチング除去し、さらに熱酸化Ｆｉイ
０５ｇｌ０を膨面する。The film 5 is removed by etching, and the thermally oxidized Fi 05gl0 is expanded.
そして、！４図に示すように、Ｉ’８ＧＩ！１！１１を
形皮シ、；ンタクｈホールの穴掛けをして五！配線臣を
形匠すす０図には示して論ないが、この後。and,! As shown in Figure 4, I'8GI! 1!Hold the 11th hole, hang the hole for the hole, and go to 5! I won't discuss it by showing the wiring officer in the figure, but after this.
パシベーション用のＦＯＧ膜及びＣＶ Ｄ Ｅｉ（Ｏ，
膜を形散し、バット°のホトエッチをおこなη半導体集
積回路装置として完広する。FOG film for passivation and CV D Ei (O,
The film is dispersed and photo-etched to complete the process as a semiconductor integrated circuit device.
以上のように従来の方法によると、最終的Ｋｍ抵抗の部
分の上には薄い熱酸化によるむ０鵞膜が膨面され、その
上にリンの濃度の暮いＰＥＧが形成される。熱酸化に工
ゐＳ（Ｏ，膜は酸化条件の制限に１って、相尚薄す膜で
２００〜４００ ’ｊｈ程！である。As described above, according to the conventional method, a thin film of thermal oxidation is swollen over the final Km resistance portion, and PEG with a low phosphorus concentration is formed thereon. The thermal oxidation process is approximately 200 to 400 h for a relatively thin film, depending on the oxidation conditions.
この理由としては、８化の時に拡散された部分のソース
、ドレイン、それに多結晶ｓ（５も同時ニ酸化される。The reason for this is that the source, drain, and polycrystalline s(5) which are diffused during oxidation are simultaneously oxidized.
その時の酸化レートに大きなちがいがあり、特に拡散さ
れた多結晶Ｂ（層の酸化レートが大きくノント°−プの
多結晶Ｓ（層の５〜６倍程度である。これＦｉ、酸化温
度にもよるが、拡散された後なので暮論温変はかけられ
な込。低２温度では特に酸化レート比が太き一〇 ドー
プされた多結晶Ｓ＜層の酸化膜厚みが厚くなると多結晶
Ｓｉ層そのものの厚みが簿くなる。＊＜ｈると特性が変
り問題になる。以上の１うに１条件の制約から、高抵抗
部の多結晶Ｓ＜層上に！／′１２００〜４００Ａと論う
薄い膜しか形匠できな論。この上に、リンｅｋ闇の濃い
Ｘ’ＢＧが直接形成されるため、高抵抗部の多結晶ｓｊ
層〈リンが浸入して特性が悪化するおそれがある為に、
後工程の熱処理条件が制限されると同時に、長期信頼性
の保障がむずかしくなる。There is a big difference in the oxidation rate at that time, especially the oxidation rate of the diffused polycrystalline B layer is about 5 to 6 times that of the non-topped polycrystalline S layer. However, since it has been diffused, temperature changes cannot be expected.At low temperatures, the oxidation rate ratio is particularly large.10 Doped polycrystalline S The thickness of the material itself becomes a book.If *<h, the characteristics change and become a problem.From the above 1-1 condition constraint, it is argued that on the polycrystalline S<layer of the high resistance part!/'1200~400A The theory is that only a thin film can be formed.Since the dark X'BG is directly formed on top of this, the polycrystalline sj of the high resistance part
layer〈Because there is a risk that phosphorus may enter and deteriorate the characteristics,
At the same time, the heat treatment conditions in the post-process are restricted, and at the same time, it becomes difficult to guarantee long-term reliability.
本発明は以上のような欠点につｂて改良を加えたもので
あり１本発明の目的はＰ日Ｇ膜からのリンの浸入を、後
工程及び長期使用状態におＡて防止する事にある。リン
の浸入を防止するために。The present invention has been made to improve the above-mentioned drawbacks. 1. The purpose of the present invention is to prevent the infiltration of phosphorus from the P/G film in subsequent processes and during long-term use. be. To prevent phosphorus infiltration.
間に絶縁膜を形成するわけであるが、第５〜８図に例を
挙げ以下に本発明につ＾て詳細に説明する。An insulating film is formed in between, and the present invention will be explained in detail below with examples shown in FIGS.
第５図に示すように、２１はＰ型ａｉ単結晶基板。As shown in FIG. 5, 21 is a P-type AI single crystal substrate.
２２はフィールド日１０１瞑、乙はゲーｈＢｔｏ冨膜。22 is field day 101 meditation, and Otsu is game hBto Tomiwa.
２４ｈ多結ａｓ （Ｉｌｌ 、 ２５ｉｄ熱酸化ＳｉＯ
ｍａ１１．ＩＲ８ｊ、Ｎｍ膜、２７はｃ Ｖ Ｄ Ｂ１
０１．２８１１ Ｎ拡散ｇ、ｚｈ高抵抗である。24h polycrystalline as(Ill, 25id thermal oxidation SiO
ma11. IR8j, Nm film, 27 is c V D B1
01.2811 N diffusion g, zh high resistance.
第６図に示すように、熱酸化＋Ｈｏ、膜及びむｓＭ４＃
！Ｘを高抵抗部を残してエツチング除去し、さらに新し
１Ａ熱酸化む０富田を形放する。この後、第７図に示す
ようにＰ８Ｇ膜３１を形ｆｆＬ、コンタクｈホールを形
′放した後ムｊ配線諺を形放する。この工うにすれば、
多結晶８（層を熱酸化したＳｉＯ２ＴＥＬ膜。As shown in Figure 6, thermal oxidation + Ho, film and sM4#
! Remove the X by etching leaving the high resistance part, and then remove the new 1A thermally oxidized 0 Tomita. Thereafter, as shown in FIG. 7, the P8G film 31 is shaped like ffL, the contact holes are shaped, and then the wiring lines are shaped. If you do this,
Polycrystalline 8 (SiO2TEL film with thermally oxidized layer.
ｓｚ、 Ｎ、膜、それにＣＶＤＢイ０１ Ｋ’ｔ ＩＦ
抵抗部上ニ残す事が出来る、
そして、その上にＦＯＧをのせる事になる。それ故、Ｐ
ＥＧをのせるまでの間に、 ４０００〜６０００久程
度の綿層のよい絶縁膜をのせる事が出来る。sz, N, membrane, and CVDB i01 K't IF
You can leave it on top of the resistor, and then put the FOG on top of it. Therefore, P
Before placing the EG, a good insulation film with a cotton layer of about 4,000 to 6,000 years can be placed.
それ故、？８Ｇからのリンの浸入は防止する事ができる
ので、後工程での窩温長時間の熱処理にもたλうると同
時に、長期信頼性にもたえうる。Therefore,? Since the infiltration of phosphorus from 8G can be prevented, it is possible to withstand long-term heat treatment at the cavity temperature in the post-process, and at the same time, it is possible to maintain long-term reliability.
又、第８図を用いて上記とけ別の方法について説明する
。第８図に示した方法は、第５図に示し７？−ように、
Ｎ拡散のためのイオン打ち込みをした後、ｃｖｎ日ｔｏ
、膜ｅ Ｂｔｓ Ｎｔｍ ａ 熱酸化膜’ｋ 除Ｂ Ｌ
−その上に新しｂＣｖＤ ＳｉＯ２ＴＥＬ贋４７を形放
して必要な部分を残して他を工ヴ争ング除去するうさら
Ｋ。Further, the above-mentioned separation method will be explained using FIG. The method shown in FIG. 8 is similar to that shown in FIG. -Like,
After ion implantation for N diffusion, cvn date to
, film e Bts Ntm a thermal oxide film 'k removed B L
- On top of that, Usara K removes the new bCvD SiO2TEL counterfeit 47, leaving the necessary parts and removing the rest.
熱酸化Ｅｌ＜０１！！！！父を形放しｔ後、ＦＩＧ膜５
１を形放し、コンタクトホールを形テする、その上にＡ
Ｊ配＃Ｉ５２を形度す石。以上のようにすると、７８（
）膜と高抵抗部との間に＃−ｊ厚論ｃ ｖ Ｄ ＳｉＯ
２ＴＥＬ膜がある霞め、Ｉｌｌの浸入を気にす♂必要が
なくなる。Thermal oxidation El<01! ! ! ! After releasing my father, FIG membrane 5
Release 1, form a contact hole, and place A on top of it.
A stone shaped like #I52. If you do the above, 78 (
) between the film and the high resistance part #-j thickness c v D SiO
With the 2TEL membrane, there is no need to worry about infiltration of haze and Ill.
以上のように本発明の方法によれば、後工程である熱処
理によって、高抵抗部の多結晶Ｂ（層中に上部のＦＯＧ
膜からリンが浸入して、特性を悪化する事もなく、同時
に熱処理の条件の限定も必要ない。又、長期的信頼性に
お論ても充分な保障のできる本のである。As described above, according to the method of the present invention, the polycrystalline B of the high resistance part (the upper FOG in the layer) is
There is no possibility of phosphorus infiltrating through the film and deteriorating the properties, and at the same time there is no need to limit the heat treatment conditions. Also, this is a book that can be fully guaranteed in terms of long-term reliability.
第１〜４図は従来の方法についての製造工程を頭に追っ
た断面略図である。
第５〜８図は本発明の方法についての製造工程を順に追
った断面略図である。
以下次の通り。
１ 、２１ 、４１ ： Ｉ’型Ｓぜ単結晶基板２ 、
２２ 、４２ ：フイールト°８イ０鵞膜３．２３．４
３： ゲー ｈ ５ｊｏｔ ｌ［ｔＦ４．２４．
４４：多結晶Ｓイ層
５．１０．２５．３０．５０：熱Ｍｌ 化Ｆ３ｔＯｘ
ｆｉｌ！６ 、２６ ： ８ｉ３Ｎ４１ｍ
７ −２７ｅ ４７ ： Ｃｖ” ８”＊ ［１８＠
２８ ＃ ４８ ： Ｈ１拡散層９．２９．４９：Ｘ
抵抗
１１ 、 ３１ 、 ５１ ： Ｐ ＥＩ
Ｇ 膜１２ 、３２ 、５２ ：ム！配線
以 上
第１図
第２図
手続補正書（自発）
昭和６２年１１月６日付提出の特許ＩＮ（１２）２、発
明の名称
ス タ テ ッ り ＲＡＭ３、補正する者
事件との関係 出願人
東京都新宿区西新宿２丁目４番１号
（２３６）セイコーエプソン株式会社
代表取締役 中 村 恒 也
４、代理人
〒１０４ 東京都中央区京橋２丁目６番２１号５、補正
の対象
明 細 書（特許請求の範囲・発明の詳細な説明）、図
面手続補正書
ｌ、特許請求の範囲を別紙の如（補正する。
２、明細書第２頁２行目
「に関し、」とあるを
「に関し、上方の絶縁膜にＰＳＧ膜を用いた場合の」と
補正する。
３、明細書筒２頁５行目
「過通回路」とあるを
「周辺回路」と補正する。
４、明細書第４頁１３行目
「目的はＰＳＧ膜からのり」とあるを
「目的は上方の絶縁膜としてのＰＳＧ膜から高抵抗部の
多結晶Ｓｔ層へのす」と補正する。
５、明細書第６頁８行目
「本発明の方法によれば、」とあるを
「本発明の構成にれば、上方の絶縁膜としてのＰＳＧ膜
と高抵抗部の間には高抵抗部へＰＳＧ膜からのリンの浸
入を防止する膜が存在するので、と補正する。
６、明細書第６頁１３行目と１４行目の間に以下の文を
挿入する。
［さらに、本発明は高抵抗部の多結晶Ｓｔ石層上は上方
のＰＳＧ膜からのりリンの浸入を防止する膜とＰＳＧ膜
を有して絶縁膜が厚くなっているが、コンタクトホール
が形成される低抵抗部の多結晶Ｓｉ層上にはＰＳＧ膜と
熱酸化膜が形成されているだけであるので、コンタクト
ホールを介して低抵抗部の多結晶Ｓｉ層と電気的に接続
する配線の下の絶縁膜の段差が小さくてすみ、配線の断
線を極力防止することができるという効果も有するもの
である。」
７、第４図を別紙のとおり補正する。
以上
特許請求の範囲
ることを特徴とするスタテックＲＡＭ。
第４図1 to 4 are schematic cross-sectional views illustrating the manufacturing process of a conventional method. 5 to 8 are schematic cross-sectional views sequentially following the manufacturing steps of the method of the present invention. Below is as follows. 1, 21, 41: I' type Sze single crystal substrate 2,
22, 42: felt degree 8 i0 occipital 3.23.4
3: Game h 5jot l[tF4.24.
44: Polycrystalline Si layer 5.10.25.30.50: Heat Ml conversion F3tOx
fil! 6, 26: 8i3N41m 7 -27e 47: Cv” 8”* [18@
28 #48: H1 diffusion layer 9.29.49:X
Resistance 11, 31, 51: PEI
G membrane 12, 32, 52: Mu! Wiring and above Figure 1 Figure 2 Procedural amendment (voluntary) Patent IN (12) 2 filed on November 6, 1986, Name of invention Status RAM 3, Relationship with the person making the amendment Applicant 2-4-1 Nishi-Shinjuku, Shinjuku-ku, Tokyo (236) Seiko Epson Corporation Representative Director Tsuneya Nakamura 4, Agent 2-6-21-5 Kyobashi, Chuo-ku, Tokyo 104 Statement of subject matter for amendment (Claims/Detailed Description of the Invention), Drawing Procedure Amendment I, Claims shall be amended as shown in the attached sheet. 2. In the second line of page 2 of the specification, the words ``with respect to'' shall be replaced with ``with respect to''. , when a PSG film is used as the upper insulating film. 3. On page 2 of the specification tube, line 5, "pass-through circuit" is corrected to "peripheral circuit." 4. Specification No. 4 Page 13, page 13, ``The purpose is to paste from the PSG film'' is corrected to ``The purpose is to paste from the PSG film as an upper insulating film to the polycrystalline St layer in the high resistance part.'' 5. Specification, page 6 Line 8, ``According to the method of the present invention,'' is replaced with ``According to the structure of the present invention, between the PSG film as the upper insulating film and the high resistance part, there is a gap between the PSG film and the high resistance part. 6. Insert the following sentence between lines 13 and 14 on page 6 of the specification. On the crystalline St stone layer, the insulating film is thickened by the PSG film and a film that prevents the infiltration of glue from the PSG film above, but on the polycrystalline Si layer in the low resistance part where the contact hole is formed. Since only a PSG film and a thermal oxidation film are formed on the insulating film, the level difference in the insulating film under the wiring that is electrically connected to the polycrystalline Si layer of the low resistance part through the contact hole is small. It also has the effect of being able to prevent wiring breakage as much as possible.'' 7. Figure 4 is amended as shown in the attached sheet. A static RAM characterized by the above claimed scope.
Claims (2)
タテツクＲＡＭおいて、該高抵抗部の上に、該多結晶シ
リコンを酸化したＳｉＯ＿２膜、又はＢｉ＿３Ｎ＿４、
膜及びＣＶＤＳｉＯ＿２等の絶縁膜を、単独で又は組合
せで形成し残した事を特徴とするスタテツクＲＡＭ。(1) In a static RAM with built-in high resistance formed of polycrystalline silicon, a SiO_2 film obtained by oxidizing the polycrystalline silicon, or a Bi_3N_4,
A static RAM characterized in that a film and an insulating film such as CVDSiO_2 are left alone or in combination.
該ＳｉＯ＿２ＴＥＬ膜、又は該Ｓｉ＿３Ｎ＿４膜、及び
該ＣＶＤＳｉＯ＿２膜等の絶縁膜を該高抵抗部上に残し
た事を特徴とする特許請求の範囲第一項記載のスタテツ
クＲＡＭ。(2) A claim characterized in that an insulating film such as the SiO_2TEL film, the Si_3N_4 film, or the CVDSiO_2 film, which is obtained by oxidizing the polycrystalline silicon used in the manufacturing process, is left on the high resistance part. The state RAM according to item 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62280512A JPS63158863A (en) | 1987-11-06 | 1987-11-06 | Static ram |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62280512A JPS63158863A (en) | 1987-11-06 | 1987-11-06 | Static ram |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56095087A Division JPS57210660A (en) | 1981-06-19 | 1981-06-19 | Static ram |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63158863A true JPS63158863A (en) | 1988-07-01 |
| JPH0516186B2 JPH0516186B2 (en) | 1993-03-03 |
Family
ID=17626129
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62280512A Granted JPS63158863A (en) | 1987-11-06 | 1987-11-06 | Static ram |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63158863A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5372483A (en) * | 1976-12-09 | 1978-06-27 | Matsushita Electric Ind Co Ltd | Semiconductor device and its manufacture |
| JPS54105485A (en) * | 1978-02-06 | 1979-08-18 | Mitsubishi Electric Corp | Manufacture of semiconductor unit |
-
1987
- 1987-11-06 JP JP62280512A patent/JPS63158863A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5372483A (en) * | 1976-12-09 | 1978-06-27 | Matsushita Electric Ind Co Ltd | Semiconductor device and its manufacture |
| JPS54105485A (en) * | 1978-02-06 | 1979-08-18 | Mitsubishi Electric Corp | Manufacture of semiconductor unit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0516186B2 (en) | 1993-03-03 |
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