JPS63158653A - Dma transfer control system - Google Patents

Abstract

PURPOSE:To efficiently execute a DMA transfer by setting the number of the transfer bytes of transferred data and the memory address of the transfer destination of the data, instructing a DMA controller to activate and writing the transferred data in an FIFO. CONSTITUTION:A main control part 1 sets the number 17 of the block transfer bytes to a comparator 6 in the DMA controller 2 at the time of the initialization of the entirety of a device. Thereafter, at the time of using the controller 2 and transferring the data from the FIFO 3 to a memory 5, the control part 1 applies the number of the transfer bytes 18 and the memory address 21 of the data transfer destination to the controller 2, activates a starting instructing line 20 and writes the transferred data in the FIFO 3. At that time, when the number of the bytes applied to the controller 2 is larger than the number of the bytes which can be accumulated on the FIFO 3, the control part 1 recognizes that a writing permission line 28 from the FIFO 3 is activated and then it writes the data 11.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a DMA transfer control method, and particularly to an MA transfer control method that enables high-speed processing.

[Conventional technology]

Conventionally, when transferring data from FIFO (first-in-first-out memory) to memory such as RAM'M using a DMA controller, first, the main/sub qrH section is
Write all the transfer data to IF6, then add a startup instruction to the DMA controller including the memory address of the data transfer destination and the number of bytes of transfer data (transfer byte number),
I am trying to start up the DMA controller. Also, if you want to transfer more data to memory than the number of bytes that FIFO can store (the number of bytes that can be stored),
After writing data that is less than the number of bytes that can be stored in the IFO,
The process of adding a startup instruction including the transfer destination memory address and the number of transfer bytes to the DMA controller is repeated until the data transfer is completed.

[Problem that the invention seeks to solve]

In the conventional method described above, the main control unit writes the transfer data to the FIFO and then adds a start instruction to the DMA controller, and generally, the DMA controller does not transfer data after the start instruction is applied. Since there is a hardware waiting time before the start, no processing is performed at all after the activation instruction is given until the data transfer starts, resulting in a problem of a large amount of wasted time. In addition, when transferring data that exceeds the number of bytes that can be stored, write the data that is less than the number of bytes that can be stored to the FIFO, and then add a startup instruction to the DMA controller that includes the memory address of the transfer destination and the number of bytes to be transferred. Since the process is repeated until the data transfer is completed, there is also the problem of inefficiency.

The present invention solves the above-mentioned problems, and its purpose is to enable efficient DMA transfer.

[Means for solving problems]

In order to solve the above-mentioned problems, the present invention uses a DMA transfer control method in which data written by a main control unit to an FTFO is transferred to a memory using a DMA controller. A byte counter indicating the number of bytes is provided, and the DMA controller compares the number of block transfer bytes preset by the main control unit with the number of bytes indicated in the byte counter, and determines the number of bytes indicated by the byte counter. a first comparator that applies a read signal equal to the number of block transfer bytes to the FrFO when the number of bytes exceeds the number of block transfer bytes; and a number of transfer bytes set by the main control unit at the time of data transfer. a transfer completion search circuit that calculates the number of remaining transfer bytes based on the read signal for the FIFO; and a transfer completion search circuit that compares the number of remaining transfer bytes obtained by the transfer completion search circuit with the block transfer byte number. The number of remaining transfer bytes obtained by the above is compared with the number of bytes indicated by the byte counter, and the number of remaining transfer bytes obtained by the transfer completion search circuit and the number of bytes indicated by the byte counter are negative, and the transfer is completed. a second comparator that applies read signals of the same number as the number of remaining transfer bytes obtained by the transfer completion search circuit to the FIFO when the number of remaining transfer bytes obtained by the search circuit becomes less than the block transfer byte number; write means for sequentially writing data read from the FIFO into the memory starting from a memory address set by the main control unit during data transfer; The number of data transfer bytes and the memory address of the data transfer destination are set, the DMA controller is instructed to start, and the transfer data is written to the FIF◯.

[For production]

The main control unit instructs the DMA controller to start, and then
This starts the writing of transfer data to the IFO, and is performed during the hardware-related waiting time between when a startup instruction is given to the DMA controller and when data transfer actually starts, which previously had not been processed at all. FIFO
Since the transfer data can be written to, the data transfer time can be shortened.

The first comparator applies the same number of read signals as the number of block transfer bytes to the FIFO every time the number of bytes of transfer data stored in the FIFO exceeds the number of block transfer bytes. As a result, data corresponding to the number of block transfer bytes is transferred in blocks. The second comparator detects that the remaining number of transfer bytes of the transfer data is less than the number of block transfer bytes, and the FIFO
By storing the entire number of remaining transfer bytes, the same number of continuation signals as the number of remaining transfer bytes are added to the FIFO.

As a result, the remaining transfer data is transferred.

Here, the first comparator creates a read signal based on the number of block transfer bytes preset by the main/sub/J section and the number of bytes indicated by the byte counter, and the second comparator creates a read signal based on the number of bytes indicated by the byte counter. A read signal is created based on the number of block transfer bytes set in advance by the block transfer byte number, the number of bytes indicated by the byte counter, and the remaining transfer byte number, and the remaining transfer byte number is the transfer byte number set by the main control unit at the time of data transfer. and the read signal, so
Even when transferring data that exceeds the number of bytes that can be stored in the FIFO, it is possible to perform startup processing only once.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, which is composed of a main control section 1, a DMA controller 2, a FIFO 3 having a byte counter 4, and a memory 5.

The FIFO 3 having a byte counter 4 activates the addition signal line 12 to count up the byte counter 4 every time one byte of data 11 is added from the main control unit I, and activates the subtraction signal WI3 every time one byte of data 16 is read out. is activated to count down the byte counter 4. That is, the count value 14 of the byte counter 40 indicates the number of bytes of data stored in the FIFO 3. Furthermore, when the number of bytes of data stored therein becomes equal to the number of storable bytes, the FIFO 3 deactivates the write permission signal line 28.

The DMA controller 2 is the first DMA controller. a second comparator 6°7;
It consists of a transfer completion search circuit 8, buffers 9 and 10, and an OR gate 29. The comparator 6 receives the number of block transfer bytes (17) set by the main control unit 1 at the time of initial setting.
(Number of bytes of data to be transferred in one block transfer) is compared with count value 14 of byte counter 4, and when the comparison result is count value 14 ≧ number of block transfer bytes 17, the pro.

It outputs the same number of read signals 22 as the number of transferred bytes (17). The transfer completion search circuit 8 has a counter (not shown) for counting the number of bytes of data actually transferred using the read signal 15 as an input clock.
The count value of this counter is '41'l from the number of transferred bytes set by 18, and the remaining number of transferred bytes is 2.
3 to the comparator 7 and the remaining number of transferred bytes is 23.
becomes “0”, the DMA completion signal 19 is sent to the main control unit 1.
Add to. Note that the above counter is reset when the number of transferred bytes is set to 18. The comparator 7 compares the count value 14 and the number of remaining transfer bytes 23 and also compares the number of block transfer bytes 17 and the number of remaining transfer bytes 23, and the comparison result is count value 14 - the number of remaining transfer bytes 23, and When the number of remaining transfer bytes reaches 23 (the number of block transfer bytes is 17), the same number of read signals 24 as the number of remaining transfer bytes 23 are output.

Next, the operation shown in FIG. 1 will be explained.

The main control unit 1 sets the number of block transfer bytes, 17, in the comparator 6 in the DMA controller 2 when initializing the entire device. After this, when data is transferred from FIFO 3 to memory 5 using DMA controller 2,
First, the main control unit 1 adds the number of transfer bytes 18 and the memory address 21 of the data transfer destination to the DMA controller 2, activates the activation instruction line 20, and then writes the transfer data 11 to the FIFO 3. At this time, if the number of transfer bytes 18 added to the DMA controller 2 is larger than the number of bytes that can be stored in the FIFO3, the main control unit
Data II is written after confirming that the S write permission line 28 from O3 is activated. Also, DM
When the A controller 2 confirms that the activation instruction line 20 has been activated, it stores the memory address 21 from the main control unit 1 in the buffer IO and sets the number of transfer bytes 18 in the transfer completion search circuit 8.

When writing of the transfer data 11 to the FIFO 3 is started, the count value 14 of the byte counter 4 gradually increases. Then, the count value 14 is the block transfer byte number 17
When the count value 14≧number of block transfer bytes 17 is satisfied, the comparator 6 outputs the same number of successive signals 22 as the number of block transfer bytes 17 as described above. This read signal 22 is applied to FIFO3 via OR gate 29, and FIFO3 is applied to FIFO3 via OR gate 29.
One block of transfer data 16 is output in accordance with the continuation signal 15 output from the transfer signal 15. DMA controller 2 is
The data 16 output from the FIFO 3 is sequentially stored in the buffer 9, and the data 27 stored in the buffer 9 is sequentially stored in the memory 5 from the address 25 stored in the buffer 10 according to the timing of the write signal 26, as in the conventional case.
write to. Incidentally, at this time, the memory addresses stored in the buffer IO are sequentially changed in accordance with the write signal 26 in the same manner as in the conventional case.

Even while data is being written to memory 5, transfer data is being written to FIFO 3, and when the count value 14≧block transfer byte number 17, the same operation as described above is performed. If the count value 4=remaining transfer byte number 23, and the remaining transfer byte number 23<block transfer byte number 17, the following operation is performed.

When the above-mentioned conditions are met, that is, when the number of remaining transfer bytes 23 of the transfer data becomes less than or equal to the number of block transfer bytes 17, and when all the remaining data is written to the FIFO 3, the comparator 7 detects the number of remaining transfer bytes as described above. 23 and the same number of read signals 24 are output.

This read signal 24 is sent to the FIFO via an OR gate 29.
The FIFO 3 sequentially outputs transfer data one byte at a time in accordance with the read signal 15 output from the OR gate 29. The data output from the FIFO 3 is temporarily stored in the buffer 9, and the data 27 stored in the buffer 9 is sequentially written from the address 25 stored in the buffer 10 of the memory 5 according to the timing of the write signal 26. In other words, if the number of remaining data bytes is 17 or more, the number of block transfer bytes is 17, the data is transferred in units of block transfer bytes, and the number of block transfer bytes is 1.
If the number is 7 or less, data is transferred in units of that number of bytes. When the data transfer is completed and the remaining transfer data count 23 becomes "0", the DMA controller 2 notifies the main control unit 1 of the end of the DMA transfer using the DMA completion signal 19.

Note that it is also possible to integrate the portion surrounded by the dashed line in FIG.

〔Effect of the invention〕

As explained above, the present invention writes data to the FIFO after instructing the DMA controller to start up. Conventionally, this invention instructs the DMA controller to start up and then writes data to the FIFO. Since the transfer data can be written to the FIFO during the hardware-based waiting time from the time to when the data transfer actually starts, there is an effect that the data transfer time can be shortened.

Further, the present invention further provides a first comparator circuit that applies read signals of the same number as the number of block transfer bytes to the FIFO every time the number of bytes of transfer data accumulated in the FIFO exceeds the number of block transfer bytes; a second comparator circuit that applies read signals of the same number as the number of remaining transfer bytes to the FIFO when the number of remaining transfer bytes becomes less than the number of block transfer bytes and all the remaining transfer bytes are stored in the FIFO. Therefore, even when transferring data that exceeds the number of bytes that can be stored in the FIFO, DM
The processing required to start up the A controller can be reduced to one time, which has the effect of improving data transfer efficiency.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the invention. In the figure, 1... Main control unit, 2... DMA controller, 3... FIFo, 4... Byte counter,
5...Memory, 6.7...Comparator, 8...Transfer completion search circuit, 9.10...Buffer.

Claims (1)

[Scope of Claims] In a DMA transfer control method in which data written by a main control unit in a FIFO is transferred to a memory using a DMA controller, a byte counter indicating the number of bytes of data stored in the FIFO is provided. and the DMA controller is configured to compare the number of block transfer bytes preset by the main control unit with the number of bytes indicated in the byte counter, and to determine whether the number of bytes indicated by the byte counter is the block transfer byte number. a first comparator that applies a read signal of the same number as the number of block transfer bytes to the FIFO when the number of block transfer bytes is greater than or equal to the number of block transfer bytes; a transfer completion search circuit that calculates the number of remaining transfer bytes based on the transfer completion search circuit; and a transfer completion search circuit that compares the remaining transfer byte number obtained by the transfer completion search circuit with the block transfer byte number, and also compares the remaining transfer byte number obtained by the transfer completion search circuit. and the number of bytes indicated by the byte counter, and if the number of remaining transfer bytes determined by the transfer completion search circuit matches the number of bytes indicated by the byte counter, and the remaining transfer bytes determined by the transfer completion search circuit a second comparator that applies to the FIFO the same number of read signals as the number of remaining transfer bytes determined by the transfer completion search circuit when the number of remaining transfer bytes becomes less than the number of block transfer bytes; write means for sequentially writing into the memory from a memory address set by the main control unit during transfer, and the main control unit, when transferring data to the memory, determines the number of transfer bytes of the data to be transferred and the data size. A DMA transfer control method characterized in that a memory address of a transfer destination is set, the DMA controller is instructed to start, and then transfer data is written to the FIFO.