JPS63156259A - Accessing method - Google Patents

Abstract

PURPOSE:To speed up access by allowing a processor to fetch two data corresponding to a specified address and a next address or specified address at the same time. CONSTITUTION:A storage device is divided into an even address storage device 5 and an odd address storage device 6. When the processor 1 fetches data corresponding to an odd and an even address at the same time, the address part excluding the least significant digit bit of the specified address is supplied to the device 5 or 6 having data corresponding to the odd or even address. Then an adder 41 adds 1 or 0 to the address part and supplies the result to the device 5 or 6 having odd or even addresses. Thus, two data corresponding to the same address part or two data corresponding to different address parts are obtained at the same time. Consequently, the access is speeded up.

Description

[Detailed Description of the Invention] [Summary] In an access method, when a computer simultaneously takes in data corresponding to an odd number address and an even number address, the address part excluding the least significant bit is used as the data corresponding to the odd number address or the even number address. As well as providing equipment with
The adder adds 1 or O to the above address portion and supplies it to a device having an even address or an odd address to speed up access.

[Industrial application field]

The present invention relates to an improved access method.

Generally, a computer gives one address to a storage device and reads the data corresponding to that address, but when performing sequential processing, in the second step, it gives the previous address an address that is incremented by 1, for example. The operation of fetching data corresponding to this address is often repeated.

In this case, it is not possible to give an address incremented by one unless the processing power corresponding to the previous address is increased by q, so the time from when the computer gives the address until it reads the data from the storage device, that is, the access time, is long. Become.

Therefore, it is necessary to shorten this access time.

[Conventional technology]

FIG. 4 is a block diagram for implementing the conventional example, and FIG. 5 is an explanatory diagram of the operation of FIG. 4. Hereinafter, the operation of FIG. 4 will be explained with reference to FIG.

First, in order to shorten the time it takes for a computer (hereinafter referred to as a processor) to import data stored in a storage device after giving an address, it is possible to import two pieces of data in one access. good.

For this reason, for example, an 8-bit storage area in a storage device is divided into a 4-bit even address area 2 that stores data corresponding to even addresses and a 4-bit odd address data area 3 that stores data that corresponds to odd addresses. divided into
This divided area is accessed using the address part excluding the least significant bit of the address.

That is, as shown in FIG. 5, the data corresponding to the address oooo is stored in the even number address area, the data corresponding to the address 0001 is stored in the odd number data address area, and the two addresses are accessed at the same time using address 000.

The same goes for the address 001, 0010 and 001
Data corresponding to two addresses of 1 are accessed simultaneously.

Therefore, when the processor sends address OOO to the storage device, ooo is output from the even address area.

Since the data corresponding to 0001 and the data corresponding to 0001 can be fetched from the odd address area at the same time, the access speed can be increased.

[Problem that the invention seeks to solve]

However, as shown in Figure 5, for example, the processor cannot capture data corresponding to addresses 0001 and 0010 at the same time, so in this case, address 000 is sent to the storage device, data corresponding to 0001 is fetched, and the There is a problem in that it is necessary to send address 001 to address 001 and take in data corresponding to address 0010, making it difficult to speed up O access.

[Means for solving problems]

The above problems are solved by the access method shown in FIG.

That is, the address part of the specified address excluding the least significant bit is given to a device having data corresponding to an odd numbered address or an even numbered address.

After adding 1 or 0 to the address part by the adding means 4,
It is given to devices that have data corresponding to even or odd addresses.

[Effect]

The present invention provides an address portion excluding the least significant bit of a specified address to a device having data corresponding to an odd numbered address or an even numbered address.

By adding 1 or O to the address part by the adding means 4 and then giving it to a device having an even address or an odd address, two data corresponding to the same address part,
Alternatively, two pieces of data corresponding to different address parts can be obtained at the same time, making it possible to speed up access.

〔Example〕

FIG. 2 is a block diagram for implementing the present invention, and FIG. 3 is an explanatory diagram of the operation of FIG. 2. Note that the same reference numerals refer to the same objects throughout the plan.

The operation of FIG. 2 will be described below with reference to FIG. 3 in the case of fetching data corresponding to addresses 0001 and 001O.

First, the storage device is divided into an even address storage device 5 and an odd address storage device 6, and as shown in FIG. 3, the address part excluding the least significant bit of the address is 000.001,010.
, the storage device 5 with an even address has the address oooo
, ooio, ot.

Odd address storage devices 6 store data corresponding to addresses 0001, 0011, 010.1.

Then, the address 000 sent from the processor is directly given to the odd number address storage device 6, and the address 0001 is
The data corresponding to is taken into the processor 1. On the other hand, address 00 is obtained by adding 1 to address 000 in adder 41.
1 to the even address storage device 5 and the address 0010
Similarly, data corresponding to is taken into the processor 1.

Note that when the adder 41 adds 0, data corresponding to address 0000 is fetched from the even number address storage device 5, and data corresponding to the address ooot is fetched from the odd number address storage device 6.

It is the same as the conventional example.

That is, a designated address and the next address, or two pieces of data corresponding to the designated address, can be taken into the processor at the same time, resulting in faster access.

〔Effect of the invention〕

As described above in detail, the present invention has the effect of speeding up access.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is an example of a block diagram for implementing the present invention, Fig. 3 is an explanatory diagram of the operation of Fig. 2, and Fig. 4 is a block diagram for implementing the conventional example. 5 shows an explanatory diagram of the operation of FIG. 4. In the figure, 4 indicates an adding means. Uninvented Torari Pro... 7-ri diagram 1st concave! Figure 4

Claims (1)

[Scope of Claims] A computer that simultaneously takes in data corresponding to odd and even addresses, further comprising an adding means (4), and an address portion excluding the least significant bit of the specified address corresponds to the odd or even address. An access method characterized in that the data is given to a device having data, and after the adding means adds 1 or 0 to the address part, the data is given to a device having data corresponding to an even number address or an odd number address.