JPS60117334A - Selection system of address information - Google Patents

Abstract

PURPOSE:To improve the processing efficiency for selection system of address information by obtaining the next address to receive an access within an execution cycle of the preceding instruction and in an access mode of continuous areas and therefore executing immediately the next instruction after the execution cycle is over with the preceding instruction. CONSTITUTION:In case the value of either one of registers 1' and 2' is renewed with consecutive accesses, the output B of an adder 3' is selected through a gate and sent to a buffer storage BS control part 5'. A signal B is delivered from the adder 3' with addition of the register contents and the data length and then set to the register with the next timing. In such a way, the signal B is transferred to a BS access control part before it is set to the register. Thus the address information necessary for the BS access to be executed next in an execution cycle of a microinstruction can be fed to the BS access control part.

Description

DETAILED DESCRIPTION OF THE INVENTION α) Technical Field of the Invention The present invention relates to a microinstruction in the case where control of instruction execution 5, etc. in an information processing device is realized by the operation of the microinstruction.

Depends on the memory (e.g. buffer storage.

address when accessing the website (BS).

It's about control. +.

(2) Conventional technology and problems FIG. 1 shows a diagram related to conventional BS access control.

1.2 is a block diagram of a register;

3 is an adder, 4 is a BS access address control unit, 5 is a BS access control unit, 6 is a buffer, 15 is a storage (
BS).

Buffer storage via microinstructions.

If the microinstruction is accessed, the microinstruction is accessed.

The logical address specified by the first operand is the first.

The logical address specified by 2° in the second operand is set in register 1 in FIG. 1 and in register 2. The contents of these registers are then sent to the BS access control unit 5 and used as actual access points.

After conversion to address and identification of whether or not data at the corresponding address is secured in the buffer storage 6, the buffer is stored.

Access to storage 6 is executed. .

Reading data from buffer storage 6.

Extrusions and writing are of a certain length, for example 8 bars.

If the access is performed in units of 10 bits and continues, the adder 3 adds the current value.

Add the number of accessed bytes to the value of the register.

Set in the register again as the next address value.

Then, this new address value is sent to the BS access/control unit 5.
15 accesses to buffer storage are made.

Microinstructions are usually set in registers.

The logical address t-Bs is transferred to the access control unit.

"Pre-process" that performs sending, conversion to real address, etc.

``process cycle'' and actual to buffer storage.

Processing is divided into "execution cycles" that are accessed at the time of access. The processing time is increased by performing preprocessing for the next microinstruction during the execution cycle of a certain microinstruction. ' Figure 2 is a diagram showing the time relationship between the preprocessing cycle and execution cycle of an instruction, where 7.7' is the preprocessing cycle, 8.7' is the preprocessing cycle, and 8.
8' represents an execution cycle.

For example, in the case of a BSIJ-code instruction, the evening of preprocessing cycle 7 will be explained with reference to FIG.

At the timing, register (Register x 1t in Figure 1)
ti2) to the BS access section.

Then, at the timing of execution cycle 8, data 15 is read from the BS using the transferred address. If data is to be read continuously, the corresponding data is added to the register value in this execution cycle.

The length is added. The addition result is shown in Figure 2 (A).

The corresponding register is loaded at the timing indicated by .

will be played. At the timing of execution cycle 8, 2°・
a. Preprocessing cycle 7' for the next instruction to be executed at the same time.

is being carried out.

In the control as described above, for example.

Like the load multiple register instruction.

In the case of an instruction to read data continuously from the BS, the microinstructions that execute this are the same.

As mentioned above, it is necessary to read data from the BS continuously while updating the value of the register.

Then, the address value is updated and stored in the register.

Since the access to the current BS is completed at 10 o'clock, the command is sent to the BS access control unit during the execution cycle of the previous instruction.

It is not possible to transfer the address value to be accessed next, so the previous instruction is executed.

After the cycle is completed, the updated address value is obtained from the 15 registers and sent to the BS access control section. Therefore, compared to the case of other instruction processing, the processing by micro-instruction is
The drawback was that the delay was 2°·4· by 1 cycle for each access.

(3) Purpose of the invention In view of the above-mentioned conventional drawbacks, the present invention uses the same cash register.

BS while updating its value using Star.

For normal microinstruction processing, there is no delay of one cycle even when accessing the microinstruction.

Similarly, as soon as the execution cycle of the previous instruction is completed.

This provides a method that allows the next instruction to be executed immediately.

The purpose is to

(4) Structure of the Invention 10 According to the present invention, this purpose is achieved when executing a micro-instruction that accesses memory, as specified by the operand of the microphone/mouth instruction. The start address of the area to be accessed is held in the register, and after the core access is completed, continuous access to the area is continued.
When accessing an area, the value of the register is the data length of the area that was accessed immediately before.

Add the value to the adder and register the result again.

Microprogram processing device, which stores stani.

In the method, means is provided for selecting whether to obtain an address for accessing the memory from the register or the output of the adder.

When executing microinstructions that access memory.

However, when the microinstruction is compared with the microphone 50 instruction executed immediately before, if both instructions are instructions that access memory, and the register numbers indicating the address of the data specified by their operands are the same. , an address 10 characterized in that the adder output is selected by said means.
This is achieved through an information selection method.

(5) Embodiment of the invention FIG. 3 is a block diagram of one embodiment of the invention.
' to 6' are the same as 1 to 6 in Figure 1.015 In Figure 3, normal buffer storage (BS
), the logical address specified by the operand of the mosquito microinstruction is stored in register 1'.

This is stored in the storage register 2', and is transferred to the 88 access control unit 5' to access the buffer storage 6', but the value of one register is updated and accessed one after another. .

access (e.g. load multiple).

For execution of a register instruction), the output of adder 3/ (signal indicated by B in FIG. 3) is sent to the gate.

It is selected and sent to the BS access control unit 5I.

It will be done. The signal B is output from the adder 3' after adding the contents of the register and the data length.

The number 10 is set in the register at the next timing, but it is set in the register like this.

It is transferred to the BS access control section before doing so.

During the execution cycle of the microinstruction, the next

Addresses required for B and S accesses to be executed.

It is possible to send information to the BS access control unit.

FIG. 4 is a block diagram showing an embodiment of a control signal generation/circuit for selecting address information, and shows a signal generation circuit for selecting an adder output/output as address information for B/S access. o20 In Figure 0, 9 and 10 are registers, 11 is a comparison circuit, 12 is an execution cycle control unit, 1
3 indicates a pre-processing cycle control section. Read from control storage (CS).

The received microinstruction is first set in register 9 for preprocessing, and then moved to register 10 for execution. Therefore, usually Regis.

Register 9 contains the microinstruction during the preprocessing cycle, and register 10 contains the microinstruction during the execution cycle.

Microcommands are set. A part of the instruction code and the register number of the operand in both registers 10 and 10 are respectively led to a comparator circuit 11. When the designated register numbers are the same, 15'''1'' is output.

(6) Effects of the invention As described above in detail, the method of the present invention.

According to the preprocessing cycle and execution cycle in minutes.

2゜・8 to the microinstruction processing device that processes the
- When executing a microinstruction that accesses a contiguous area of memory, it is possible to obtain the next address to be accessed during the execution cycle of the previous instruction, which is similar to the conventional method.

Because there is no need for a cycle of waiting for address information,
□ Improved efficiency of processing equipment, high processing efficiency.

The effect is great because it can be linked. .

[Brief explanation of drawings]

FIG. 1 is a block diagram of a circuit related to conventional BS access control, FIG. 2 is a diagram showing the time relationship between an instruction preprocessing cycle 10 and an execution cycle, and FIG. 3 is a block diagram of an embodiment of the present invention. , Figure 4 is Ato. FIG. 2 is a block diagram showing an embodiment of a response information selection control signal generation circuit. 1.1', 2.21S9.10...Register,
3.3'... Adder, 154.4'...
...BS access address control section, 5.5I...
・B・S access control unit, 6.6'...Buffer storage, 7.7'...Preprocessing cycle, 8.8' Song...Execution cycle, 11.・・・・・・
Comparison circuit, 12...Execution cycle control unit. 13...Pretreatment cycle control section.

Claims (1)

[Scope of Claims] When executing a microinstruction that accesses memory, the microinstruction specified by the operand of the microinstruction. The first address of the area where the register to be accessed should be accessed. The response is retained and continues to be used in the area after the access ends. Not applicable when accessing an area that is contiguous with the area. The adder adds the value of the data 10 length of the area accessed immediately before to the value of the register, and the result is regenerated. An address used when accessing memory in a microprogram processing device that stores data in a register. means is provided for selecting whether to obtain the microinstruction from the register or the output of the adder, and when executing a microinstruction that accesses the memory 15 times, the microinstruction and the previously executed microinstruction are selected. Compare both instructions to access memory, and the data specified by their operands. - An address information selection method characterized in that when the register numbers indicating the next address are the same and 2 degrees, the output of the adder is selected by the means. .