JPS63153672A - Hardware simulator - Google Patents

Abstract

PURPOSE:To provide flexibility equivalent to the software simulator by realizing a logic function section by a memory element so as to apply correction of logic though the rewrite of a data in the memory only. CONSTITUTION:Addresses A0-A9 of a memory 9A are connected to an input signal line group 2 and data lines D0-D5 are connected to an output signal line group 3. In the memory 9A, the data D5 is decided by addresses A9, A8 only corresponding to the logical value of an input/output signal of a NAND gate as shown in table. Similarly, the data D4 depends on addresses A7, A6 the data D3 depends on addresses A5, A4, the data D2 by addresses A3, A2 and the data D1 by the address A1 and the data D0 depends on the address A0 by means of data setting in the memory. The output signal lines D10, D11 of the memory 1A are connected to the input signal line as shown in the switching section 4.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to digital circuit technology, and more particularly to a hardware simulator made by LSI stage clock-eared logic.

[Conventional technology]

When designing an LSI, it is necessary to perform some form of logic circuit simulation in order to verify the logic design. Conventionally, there have been two main methods for this purpose.

The first method is software simulation on a computer using a simulation program configured by a group of logical formulas equivalent to the logical design of the target LSI. The second method is hardware simulation using a breadboard model created by actually connecting individual logic elements such as various gates, flip-flops, and latches using wire wrapping or a printed circuit board.

FIG. 5 is a block diagram of the hardware simulator.

The logic element group (functional unit) 1 is a logic element group necessary to configure the target simulator, and specifically includes various gates, buffers, flip-flops, and other small scale devices, as well as counters, ALUs, and memories. This includes items up to the LSI level such as. In addition, the input and output of each element are completely separated, and in bidirectional devices such as data buses, input and output are separated using internal signals. The input signal line group 2 is connected to the input terminal of the logic element group 1, and the output signal line group 3 is similarly connected to the output terminal. The switching matrix 4 connects any signal line in the output signal line group 3 to any (plural) arbitrary signal line in the input signal line group 2, and the connection information can be easily changed by giving it from the outside. can. External input signal line group 5, which is input to the simulator from the outside, is connected to a buffer in logic element group 1, and external output signal 1! is output from the simulator to the outside. i16 is derived from the switching matrix 4.

With this configuration, the connection between the output signal line group 3 and the input signal line group 2 can be changed using external connection information, making it possible to create a simulator that combines the flexibility of software and the high speed of hardware. can be realized. The logic element group 1 and the switching matrix 4 will be described in detail below.

FIG. 6 is a diagram showing the standardized module and standardized module socket of the logic element group (m, oil section) 1, and FIG. 7 is a diagram showing the standardized board.

As mentioned above, the logic element group (functional unit) 1 includes various gates, buffers, flip 70 blocks, counters, ALUs, etc.
It is composed of functional parts of various sizes, up to LSI-level devices such as 1 memory. All of these functional parts are used by being incorporated into various modules as shown in FIG. 6, in which actual ICs having respective functions are used. This module 7, the color is the internal IC
The input and output for the power supply terminal 12 are completely separated.
, 13, GND 14, 15, the positions of the input terminal rows 16, 17, and the output terminal rows 18, 19, etc. are determined by the unified standard. Furthermore, this module 7.9 is used by being mounted on a board 20 of a uniform standard. This standard board 20 also has module sockets 8 and 10, similar to the module 7°9.
The positions of the power supply terminal, GND, input terminal row 21, output terminal row 22, etc. are determined by the unified standard, and each module can operate no matter which module socket of the same size is mounted. It has become. By standardizing as described above, not only the wiring but also the configuration of the logic element group 1 can be made variable, resulting in higher flexibility.

FIG. 8 is a block diagram of the 4×4 switching matrix 4, and FIG. 9 is a diagram showing an example of the wiring of the switching matrix 4 of FIG. 8.

The switching matrix 4 is realized by a RAM IC. Now, consider connecting a 4×4 switching matrix as shown in FIG. 8 with A-d, B-b, C-c, and D-a. The wiring state is shown as a model in FIG. The switching matrix 4 with such a connection state is created when (A, B, C, D) = (0, O, O, O) is input to the input line array (A-D) on the left side. The side output line array (a-d) is (a, b, c,
d) = (0, O, O, O), and when (A, B, C, D) = (0, O, 0, 1), (a, b: c, d) = (1, O, O, O). Similarly, the switching matrix 4 has a total of 16 combinations (a, b, c) corresponding one-to-one to each combination of (A, B, C, D).

It has the pattern d). Such a switching matrix 4 has exactly the same function as a 16 word x 4 bit (4 address lines, 4 data lines) RAM IC. Therefore, in order to realize the switching matrix 4 shown in FIG. The signal line group 3 may be connected to the data bus, and the input signal line group 2 may be connected to the address bus.

RAM I as a switching matrix like this
When using C, it is necessary to be able to write connection information as shown in Table 1 before making it function as a simulator.

Table 1 FIG. 10 is a diagram showing an example of a hardware simulator having a functional section 1C and a switching matrix 4C each consisting of several gates.

The logic element group 1C corresponds to the logic element group 1 in FIG. 5, and here two NAND gates, two NOR gates, and two NUT gates each are incorporated into the module 9C.

In addition, the switching matrix 4C corresponds to the switching matrix 4 in FIG. 5, and for the purpose of explanation, it is modeled here as several lines intersecting in a grid pattern, and in the following description, only the necessary parts are indicated by black circles. The connection information is shown by connecting them with . Signal lines AO to A9 are functional unit 1
Included in input signal line group 2 input to C, signal line Do-D
5 is included in the output signal line group 3.

[Problem that the invention seeks to solve]

Both of the above-mentioned conventional simulation methods have their advantages and disadvantages; software simulation is flexible but lacks high speed, and hardware simulation has high speed but is limited by the speed of the IC built into each module. There are limitations on gates, and if there is a shortage of logic gates due to modification or the like, it is necessary to replace the module or add a new module, which has the disadvantage of lacking flexibility.

An object of the present invention is to provide a simulator that has flexibility comparable to a software simulator and high speed comparable to a hardware simulator in logic circuit simulation during LSI design.

[Means for solving problems]

The hardware simulator of the present invention includes a functional unit having the same function as a logic element group, which is an array of logic elements that are not connected to each other and whose input signal lines and output signal lines are separated; Same function as a switching matrix that connects any signal line in the input signal line group of the element group to the output signal line group of the logic element group and any signal line in the external input signal line group using a control signal In the hardware simulator having a switching unit, the functional unit is a memory, address lines and data lines of the memory correspond to input signal lines and output signal lines of the logic element group, respectively, and the memory has , characterized in that data corresponding to a signal that the logic element should output when a signal is input to the input signal line of the logic element is stored at an address corresponding to the input signal of the logic element. .

[Effect]

In this way, by storing data corresponding to the output of a logic element in the memory address corresponding to the input of the logic element, the logic can be modified without changing the hardware by simply rewriting the data in the memory. This provides a hardware simulator with the flexibility of a software simulator.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a conceptual diagram of the first embodiment of the hardware simulator of the present invention. FIG. 1(a) is a circuit diagram of a half adder, and FIG. FIG. 2 is a block diagram of a 1 word×6 bit memory 9A in which the module 9C of FIG. 10 is replaced.

In this embodiment, the logic circuit shown in FIG. 1(a) is realized by replacing the functional section 1C shown in FIG. 10 with a memory 1A. The logic element groups depicted in the memory 1A are drawn to show that the memory 1A has the same function as these logic element groups.

The module 9C is replaced with the memory 9A as follows. That is, address line AO of memory 9A
-A9 is connected to input signal line group 2, and data line Do-D5 of memory 9A is connected to output signal line group 3. Memory 9A has address A9. Data D5 is determined only by the value of A'8 as shown in Table 2, corresponding to the logical values of the input/output signals of the Nant gate.

Table 2 Similarly, address A7. A6. Then data D4, address △
5. Data D3 at A4, data D at address A3゜A2
2. Address A1 determines data D1, address AO determines data Do, and the data in the memory is set as shown in Table 3. In this way, module 9C in FIG.
has been replaced by memory 9A.

Table 3 Next, output signal lines DO to D5 and Dlo of memory 1A
, Dll are connected to the input signal line as shown modeled in the switching unit 4 (an actual switching matrix may be used, or a memory may be used as in E). ) Thereby, the function of the circuit of FIG. 1(a) is realized on the device of FIG. 1(b). 1st
In the figure, reference numbers 31 to 34 are written to indicate the correspondence between the input/output signal lines of the logic element in FIG. 1(a) and the address lines and data lines of the memory 1A in FIG. 1(b). It is. Furthermore, signals (a, b) indicate input signals, and (X, V) indicate output signals.

FIGS. 3 and 4 respectively show the second part of the hardware simulator of the present invention. FIG. 3 is a conceptual diagram of a third embodiment. Figure 3 (
a) is a 4-man power, 1-output logic circuit, and Fig. 3 (b) is
It is a circuit diagram in which the function of the logic circuit in a) is realized using memory 9B. Reference numbers 41 to 41 indicate the correspondence between the address lines and data lines of the memory 9B and the input/output signal lines of the logic element in FIG. 3(a). In addition, the signals (a, b, c, d) in FIG. 3(a) are the input signals,
Signal X indicates the output signal.

Furthermore, if an attempt is made to realize the logic circuit of FIG. 3(a) using the functional section shown by the module 9C of FIG. 10, one NAND element will be missing. However, if the memory of FIG. 2 is used, address A5. A4 and A3. The functions of the circuit shown in FIG. 3(a) can be easily realized by simply using the memory 9B in which the data D3 and D2 in the memory generated at A2 are rewritten to the data shown in Table 4.

FIG. 4(a) is a circuit diagram of a D flip-flop, and FIG. 4(b) is a circuit diagram in which the D flip-flop is realized using a memory 1A equivalent to the functional section 1C of FIG.

In this embodiment, a D flip-flop is realized by replacing the functional unit 1C in FIG. 10 with a memory 9A of 1 word x 6 bits in which the truth value data shown in Table 3 is written. .

〔Effect of the invention〕

As explained above, the present invention includes a logic function section composed of an element having a logic function or a memory function, an input line,
By using memory elements to realize the logic function section of a hardware simulator, which consists of a switching matrix section that connects output lines freely, the logic can be modified by simply rewriting the data in the memory, making it as flexible as a software simulator. It has the effect of being a hardware simulator.

[Brief explanation of the drawing]

FIG. 1 is a conceptual diagram of a first embodiment of the hardware simulator of the present invention, FIG. 2 is a block diagram of a 1 word x 6 bit memory in which module 9C in FIG. 10 is replaced, and FIGS. FIG. 4 is a conceptual diagram of the second and third embodiments of the hardware simulator of the present invention, FIG. 5 is a block diagram of the hardware simulator, and FIG. A diagram showing a standardized module kit, FIG. 7 is a diagram showing a standardized board,
FIG. 8 is a block diagram of the 4×4 switching matrix 4, FIG. 9 is a diagram showing an example of the wiring of the switching matrix 4 in FIG. 8, and FIG. 10 is a functional unit 1C composed of several gates. FIG. 4 is a diagram showing a hardware simulator having a switching matrix 4C and a switching matrix 4C. 1A, 1B...Memory, 2...Input signal line group, 3...Output signal line group, 4...Switching matrix, 5...External input signal line group, 6...External output signal Line group, a, b, c, d...input signal, x, y...output signal.

Claims (1)

[Scope of Claims] A functional unit having the same function as a logic element group that is an array of logic elements that are not connected to each other and whose input signal lines and output signal lines are separated; and the logic element group. It has the same function as a switching matrix that connects any signal line in the input signal line group to the output signal line group of the logic element group and any signal line in the external input signal line group by a control signal. In a hardware simulator having a switching unit, the functional unit is a memory, address lines and data lines of the memory correspond to input signal lines and output signal lines of the logic element group, respectively, and the memory Hardware characterized in that data corresponding to a signal that a logic element should output when a signal is input to an input signal line of the logic element is stored at an address corresponding to the input signal of the logic element. simulator.