JPH0429425Y2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a hardware simulator for discovering errors in the design of a logic device constituted by one or more custom LSIs.

As logic devices become larger in scale, there is a growing need for high-speed logic simulators. In the past, almost all logic simulators were performed using software. However, in large-scale systems, software simulation not only takes a lot of time to simulate, but also allows you to check everything about the logic, making it difficult to actually complete the device. The practice was to have a computer and debug it on top of it. Japanese Patent Application Laid-open No. 51-85344 is
This paper proposes a logic simulator that actually uses ICs used in equipment.The purpose of this is to avoid unclear descriptions of ICs in software and complexity of descriptions of input/output relationships. The aim is to shorten the simulation time. However, this logic simulator cannot be used with current technology. This is because this logic simulator is based on the IC actually used in logic devices.
However, today's large-scale logic devices are created using custom LSIs specific to that device. This custom LSI becomes usable at the stage of actually assembling the device, not at the time of design. i.e. actually used
The first simulation will be performed after the IC fabrication is completed. Therefore, the proposed logic simulator cannot perform a logic simulator at the time of design.

Logic devices using custom LSI require a logic simulator at the time of design. This is because once a custom LSI is created, it is impossible to correct the custom LSI even if an error is discovered in the custom LSI. As a result, design changes and LSI production must be repeated until the logical design is correct, which poses a major obstacle to efficient work in terms of man-hours, costs, and time.

The purpose of the present invention is to provide a hardware simulator for detecting errors in the design of large-scale logic devices using custom LSIs, which eliminates such conventional drawbacks.

The present invention consists of a hardware node that realizes the same function as a custom LSI using one or more PLA, a connection list memory for storing a connection list representing the connection relationship between the custom LSI, and a connection list memory for storing the connection list representing the connection relationship between the custom LSI. Status list memory and customization for storing the status list representing input/output status
An event list memory is used to store an event list representing LSI input changes, and the event list is used to determine the occurrence of an event, and the status of the custom LSI input corresponding to the event is obtained from the status list in the status list memory. input it to the hardware node, get the output from the hardware node and compare it with the output state of the state list, and if it is different, input this output from the connection list in the connection list memory. A control unit that obtains the input destination custom LSI name and its pin, writes the new input value to the state list in the state list memory, and records this custom LSI name in the event list, the state list memory, and the connection. It consists of a list memory and an operation panel that writes to the event list memory and displays its contents.

PLA can realize the same logical functions as a custom LSI before manufacturing it. This expands the logical functions of the custom LSI into logical expressions,
This can be achieved by writing the bit pattern representation into PLA. Therefore, in a logic device using a custom LSI, by creating a logical formula for each type of custom LSI and creating a PLA that converts it into a bit pattern, its operation can be simulated based on the connection relationships in the custom LSI. can do. If the behavior differs from the expected behavior during the simulation process,
This is a case where there is an error in the logic of the custom LSI. In this case, after redoing the logic design of the custom LSI and correcting any logic errors, a PLA that implements this logic is created again, and the simulation is performed again. In this way, the simulation operation is repeated until it becomes the same as the specification operation. Once this has been completed, we will begin manufacturing and shipping the custom LSI for the first time, reducing man-hours and
Costs, periods, etc. can be greatly reduced.

The present invention will be explained below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the hardware simulator of the present invention. A connection list memory 1 stores a connection list between custom LSIs, and a status list memory 2 stores a list of connections between custom LSIs. A state list representing the state of each input and output is stored, and the event list memory 3 stores an event list representing the custom LSI whose input has changed. Further, the control unit 4 controls the entire hardware simulator, and the hardware node 5 is composed of a plurality of PLAs.
In this figure, it is assumed that it is composed of PLAs 5a to 5c. The operation panel 6 writes data into the status list memory, connection list memory, and event list memory and displays the contents thereof. For example, consider simulating a logic device designed using four custom LSIs as shown in FIG. It is assumed that the custom LSI 2 and the custom LSI 3 are of the same type. At this time, a status list as shown in FIG. 3 is written into the connection list memory 1 via the operation panel 6. In addition, the status list memory 2 includes a fourth
Assume that the input and output states are given via the operation panel 6 as shown in the figure. At this time, assuming that the input to pin 5 of LSI 1 changes and changes from 0 to 1, the LSI is transferred from the operation panel 6 to the event memory 3.
1 and also register the status list memory 2.
Suppose that the state of pin 5 of LSI1 changes to 1.

The control unit 4 always checks the event list memory 3 to check whether an LSI name is registered there. Since LSI1 is registered from the operation panel 6, get LSI1 and delete it from the event list. Then, the control unit 4 obtains the input and output states of the pins of the LSI from the state list memory. Next, the control unit 4 accesses the hardware node corresponding to the LSI 1. In FIG. 1, it is assumed that the hardware node is composed of three types of PLAs 5a to 5c. Among these, PLA5a is LSI1
, PLA5b is LSI2 and LSI3, PLA5c is
It was created based on the logical formula of LSI 4, and is assumed to simulate the operation of each custom LSI. At this time, the control unit 4 gives the input state obtained from the state list memory 2 to the PLA 5a of the hardware node. Then, the control unit 4 receives an output from the PLA 5a of the hardware node, and compares it with the output state obtained from the state list memory. Suppose now that the output state of pin 1 is 1 and the output state of pin 3 is 1. As a result of the comparison, a change is found in the output state of pin 3, so the custom LSI connected to this pin is found from connection list memory 1. Since LSI3 and LSI4 are obtained from the connection list memory, they are written to the event list memory 3. Furthermore, LSI3 connected to pin 3 of LSI1
Get the input side pin of LSI4 side from the connection list memory. In this case, it is the third pin for LSI3, and it is also the third pin for LSI4. Therefore, the control unit 4 writes the value 1 of the output just obtained to the third pin of LSI3 and LSI4 of the state list memory. As a result, the event processing for the LSI 1 has been completed, and the control section 4 goes to check the event list memory again. There are
Since LSI3 and LSI4 are stored, select one and process the event using the same procedure as now.

On the other hand, from the operation panel 6, the output status of each custom LSI stored in the status list memory is checked. When this output state is the same as the output state in the inspection specifications, the logic function of the custom LSI satisfies the specifications, but if it differs from the output state in the inspection specifications, then the logic function of the custom LSI satisfies the specifications. does not meet the specifications. In this case, the logic circuit of the custom LSI is reviewed, the errors are corrected, the PLA is created again based on the logic formula, and the simulation is repeated by replacing the previous PLA.

This invention allows customization for use in logical devices.
PLA with the same functions as LSI simulation
By replacing them with We have been able to provide a hardware simulator that makes it possible to repeatedly eliminate errors and use the final results for custom LSI production, which has had great results. To date, there have been no proposals that suggest that such effects can be achieved by using custom LSIs that are actually used or by using anything other than software, so we believe that this will greatly contribute to future logic design. It will be done.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing an embodiment of the present invention, Figure 2 is a block diagram showing an example of a logic device realized by a custom LSI, and Figure 3 is a connection between the LSIs shown in Figure 2. FIG. 4 is a diagram showing an example of a status list representing the status of each LSI in FIG. 2. In the figure, 1 is a connection list memory, 2 is a status list memory, 3 is an event list memory, 4 is a control unit, and 5a to 5c are PLAs.

Claims (1)

[Scope of utility model registration request] In a hardware simulator for discovering errors in the design of logical devices composed of one or more custom LSIs, hardware that implements the same functions as the custom LSIs using one or more PLAs. A connection list memory for storing a connection list representing the connection relationship between a node and a custom LSI, a state list memory for storing a state list representing the input and output states of the custom LSI, and a custom An event list memory for storing an event list that represents LSI input changes, and a custom LSI that recognizes the occurrence of an event from the event list and responds to that event.
Obtain the input state of from the state list in the state list memory and input it to the hardware node, obtain the output from the hardware node and compare it with the output state of the state list in the state list memory. , if the connection list is different from the connection list in memory for this output destination custom
A control unit that obtains the LSI name and its pin, writes a new input value to the status list in the status list memory, and records this custom LSI name in the event list, a status list memory, a connection list memory,
A hardware simulator comprising an operation panel for writing to an event list memory and displaying the contents.