JPS6386040A - Hardware simulator - Google Patents

Abstract

PURPOSE:To realize a hardware simulator having flexibility equivalent to that of a software simulator by changing a switching matrix which performs free connection between input and output lines by means of the software. CONSTITUTION:When a switching matrix of 4X4 has connections like A-a, B-c, C-b and D-d, an output line train is defined as (a, b, c, d)=(0, 0, 0, 0) with input of (A, B, C, D)=(0, 0, 0, 0) and then as (a, b, c, d)=(1, 0, 0, 0) with input of (A, B, C, D)=(0, 0, 0, 1) respectively. In other words, the data shown in the 1st table is written to a RAM of 16 word X4 bits together with an output signal line group 103 and an input signal line group 102 connected to an address bus and a data bus respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to digital circuit technology, and particularly to a hardware simulator created by wired logic during LSI design.

[Background Art] When designing an LSI, it is necessary to perform some form of simulation of the logic circuit in order to verify the logic design. Conventionally, there have been two main methods for this purpose.

The first method is software simulation on a computer using a simulation program composed of a group of logical formulas equivalent to the logical design of the target LSI. Another method is hardware simulation using a breadboard model created by actually connecting individual logic elements such as various games, F/Fs, and latches using wire wrapping or printed circuit boards.

First, software simulation will be explained.

Digital LSIs generally only have digital information of O or 1 in each signal line and memory circuit of the internal electronic circuit, and each state is a reference given to the LSI from the outside, called a clock. It changes only in synchronization with a constant frequency pulse wave as a time signal. Therefore, the state of each signal line in the electronic circuit in the target LSI is virtually made to correspond to each variable on the electronic computer, and all internal states are reproduced on the computer as mere software information every clock. However, by advancing the clock, it is possible to imitate the operation of an LSI. At this time, the logic gates (NAND,
(NOR, NOT, etc.) can reproduce the output on a computer by using logic functions that have the same function and combining them with variables that correspond to signal lines.

Next, hardware simulation will be explained.

Whereas software simulation only virtualizes the internal state of an LSI as software information, hardware simulation actually physically reproduces it using electronic components. Logic gates, flip-flops, latches, buffers, etc. that are included in the design of the target LSI are implemented on the board using real electronic components, and the LSI
The idea is to wire the device in the same way as the design drawing of I, create an electronic device that has exactly the same functions as the target LSI, and use it to imitate the LSI. These electronic devices are referred to as B, B, M, (BreadboardMachine)
e) Or called mock-up.

[Problems to be Solved by the Invention] The conventional simulation methods described above have advantages and disadvantages in both cases.

When using software simulation, it is relatively easy to create the simulator itself, and
Although it is superior in flexibility for design changes and freedom in design, simulation speed is extremely slow. On the other hand, when hardware simulation is used, it is much faster than software simulation, but creating a simulator is more difficult than creating a simulation program. Furthermore, once the design has been created, it is difficult to modify it if the design is changed, and the degree of freedom in design may be limited by digital circuit technology.

[Object of the Invention] An object of the present invention is to provide a simulator that has flexibility comparable to a software simulator and high speed comparable to a hardware simulator in logic circuit simulation during LSI design.

Means for Solving Problems] The hardware simulator of the present invention consists of a functional section composed of elements having a logic function or a memory function, and a switching matrix that freely connects input lines and output lines, The present invention is characterized in that the connection between the input line and the output line of the logic element or memory element of the functional section can be changed by changing the switching matrix using software.

[Example] FIG. 1 shows a conceptual diagram of the present invention.

101 is a group of logic elements necessary to configure the target simulator, specifically various gates, buffers, F/F, etc., from small scale to counters, AL
It includes things up to LSI level scale such as U and memory.

It is also assumed that the input and output of each element are completely separated, and for bidirectional devices such as data buses, input and output are separated by using internal signals. For example, in the case of a data bus for RAM 31 that is input during writing and output during reading,
Using the read signal W/R, the circuit shown in FIG. 12 is connected only to the input-only data bus 32 and the output-only data bus 33 at the time of input and output, respectively.

102 is a group of input signal lines connected to each input terminal of the logic element group, and 103 is a group of output signal lines connected to each output terminal.

104 is a switching matrix that can connect any signal line in the output signal line group 103 to any (plural) arbitrary signal line in the input signal line group 102, and the connection information is as follows. It can be easily changed by applying it externally.

105 and 106 are an input signal line group and an output signal line group to the outside of the simulator, the input signal line group 105 is usually connected to a buffer in the logic element group, and the output signal line group 106 is drawn out from the switching matrix. .

The logic element group 101 and the switching matrix 104 will be described in detail below.

As described above, the logic element group 101 includes various gates, buffers, F/Fs, counters, ALUs, memories, etc.
It is composed of functional parts of various sizes, up to the I level. All of these are used by incorporating actual ICs with respective functions into various modules as shown in FIG.

2(a), 2(b), and 2(C) are a perspective view and a bottom view showing one logic element module 21, and FIG. 2(d),
(e) and (e) are a perspective view and a bottom view showing another logic element module 22. This module has an internal I
The input and output for C are completely separated, and the power terminal,
The positions of GND, input terminal rows, output terminal rows, etc. are determined by unified standards.

Further, this module is used by being mounted on a board of uniform standard as shown in FIG. Similar to modules, this standard board also has the following specifications for module sockets and board terminals:
The positions of the power supply terminal, GND, input terminal row, output terminal row, etc. are determined by unified standards, and each module can operate even if it is mounted in any module socket of the same size.

By standardizing as described above, not only wiring but also
The configuration of the logic elements can also be made variable, providing greater flexibility.

The switching matrix 104 can be realized by R,AMIC.

Now, consider connecting a 4×4 switching matrix as shown in FIG. 4(a) with A-a, B-C, C-b, ])-d. The wiring state is shown as a model in FIG. 4(b). Switching machine with this kind of connection state) I
J socks, when inputting (A, B, C, D) = (0, 0, 0, 0) into the left input line array (A-D), the lower output line array (a-d) is (alblcld) = (o, o, o, o), and when (A, B, C, D) = (0, 0, 0, 1), (alblcld) = (1,010,0 ). Similarly, each (A, B, C).

There should be a total of 16 patterns (a+ b+ C+ d) that correspond one-to-one to the combination D).

In other words, such a switching matrix has R of 16 words x 4 bits (4 address lines, 4 data lines).
It will have exactly the same functions as AM IC. Therefore, in order to realize the switching matrix shown in FIG. 4(b) using a RAM IC, data as shown in Table 1 is written in a 16 word x 4 bit RAM, and the logic element group 10 is
It is sufficient to connect the output signal line group 103 from 1 to the address bus and the input signal line group 102 to the data bus.

Next, details of embodiments of the present invention will be described.

First, FIG. 5 shows a basic configuration for realizing a simple logic circuit that can be configured with several gates. 501 is a logic element group corresponding to 101 in FIG. 1, and here six buffers and two NAND%NOR%NOT gates are prepared.

Furthermore, for the sake of explanation, the switching matrix 502 shown at 104 in FIG. Let us show the following.

FIG. 7 shows a half adder having the circuit configuration shown in FIG. 6 realized on the circuit shown in FIG. 5. Table 2 is a truth table corresponding to FIG.

It can be seen that a similar circuit is constructed by connecting individual logic elements to a switching matrix using only the hardware prepared in Table 2. (The symbols such as ■, ■, ..., etc. correspond to logic elements that operate in the same way in Figures 6 and 7.) Similarly, X = a + b + C - The case of a four-man power logic circuit having an output d is shown in FIGS. 8 and 9, and the case of a D7 lip-flop is shown in FIGS. 10 and 11.

In this way, the circuit can be rearranged by changing only the connection information given to the switching matrix without changing the configuration of the prepared hardware at all.

[Effects of the Invention] As explained above, the present invention uses a freely changeable switching matrix for connections between individual logic elements in a hardware simulator, thereby changing the connection information given to the matrix. This has the effect of making it possible to create a hardware simulator with flexibility comparable to that of a software simulator.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing the configuration of the present invention, Figure 2 (a)
, (b), (C), (d), (e), ge) are perspective views of a logic element module used in an embodiment of the present invention,
3 is a perspective view of a standard board used in an embodiment of the present invention, FIGS. 4(a) and 4(b) are explanatory diagrams of a switching matrix used in an embodiment of the present invention, and FIG. 5 is a perspective view of a standard board used in an embodiment of the present invention. A circuit diagram showing the basic configuration of an embodiment of the present invention, FIG. 6 is a circuit diagram of a general half-adder circuit, and FIG. 7 is a circuit diagram of a general half-adder circuit.
The circuit diagram when realized in the figure, Figure 8 is a general 4-person car 1
Figure 9 is a circuit diagram showing the output logic circuit. Figure 9 is a circuit diagram when this four-person car one output logic circuit is realized in Figure 5. Figure 10 is a circuit diagram showing a general D flip-flop. Figure 11 is a circuit diagram showing the output logic circuit. FIG. 5 is a circuit diagram when this D flip-flop is realized, and FIG. 12 is a block diagram illustrating a part of the logic element group in FIG. 1. 101.501...Logic element group, IQ 2.
502...Switching matrix, 21.
22...Logic element module. Agent Patent Attorney Susumu Uchihara ``t'1, Width No. 1, Chrysanthemum 3 (, 2) (b) 躬4, 躬5, j; Diagram Otsu Diagram 7

Claims (1)

[Claims] It consists of a functional section composed of elements having a logic function or a memory function, and a switching matrix that freely connects input lines and output lines.By changing the switching matrix with software, the logic elements or memory functions of the functional section can be changed. A hardware simulator characterized in that connections between input lines and output lines of memory elements can be changed.