JPS58206138A - Simulation device for logic circuit - Google Patents

Abstract

PURPOSE:To enable simulation at velocity approximately close to the actual operation of the circuit by constituting a circuit equivalent to the circuit to be simulated in a hardware manner. CONSTITUTION:A logic-circuit array 1 is constituted by a plurality of fundamental circuit element arrays 4 and a wiring matrix 5 consisting of a conductor piece and switches. The states of each switch of the wiring matrix 5 are set by a circuit constituting section 2, and the logic-circuit array 1 is made equivalently equal to the circuit to be simulated. An input test system is applied to the logic- circuit array 1 by a simulation execution section 3 and the circuit is operated, and the simulation is performed.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a device for simulating the operation of a logic circuit, particularly for logic circuit design of digital systems and integrated circuits. It is used to verify the operation of the circuit.

[Background technology of the invention]

Traditionally, large-scale integrated circuits (hereinafter referred to as LSI), etc.・8・
In rational circuit design, the following two methods are mainly used to verify the operation of the circuit. One method is to actually create a circuit on a printed circuit board using an existing integrated circuit (IC). How to configure and verify whether the design is correct by making it work,
Generally called a breadboard.

Another method is computer program simulation. Generally, a program called a logic simulation program is used (for example,
Junshita: [Logic device CAD J, Information Processing Society of Japan (19
81) F [Problems with the background technology] The background technology described in the previous section has the following problems.

In the case of a breadboard, (I) it takes time and money to create a breadboard; (b) It is not easy to repair. (…)
Since it is a manual process, it is difficult to connect it with an automatic design system. (iv) In the case of LSI design, accurate operation simulation is often difficult because the breadboard and actual LSI circuits have different conditions in terms of circuit delays and the like.

On the other hand, in the case of software simulation, (v)
It takes a long time to sequentially simulate the operation of the circuit valleys using the combinator, and therefore, it is often practically impossible to completely confirm all the operations of the circuit.

[Purpose of the invention]

This invention provides an improved logic circuit simulation device in view of safety issues. , a wiring matrix for realizing arbitrary mutual wiring, a means for inputting connection information of the circuit to be simulated, and a means for inputting connection information of each switch in the wiring matrix in order to realize an equivalent circuit from the connection information of the circuit. A means for optimally determining opening and closing, a means for manually inputting an input test sequence for a circuit to be run, a means for simulating the operation of a logic circuit by printing an input test sequence, and a means for simulating the operation of a logic circuit by inputting an input test sequence, and a means for simulating the operation of a logic circuit by inputting an input test sequence. It consists of means for outputting the state of an arbitrary part. Since this device is basically a hardware simulation, it has the same speed as a breadboard and has the same advantages as software simulation in that circuit connections can be changed freely. , thus solving the problem of injection points in the prior art.

[Embodiments of the invention]

Next, one embodiment of the present invention will be explained in detail with reference to the drawings. Figure 1, which shows one embodiment, shows the device configuration, which can be roughly divided into general-purpose "
-Logic circuit array section J tl), circuit connection information (4)
Input the circuit configuration section J (2), which has the function of realizing the circuit to be simulated with equal constraints, and then perform a test using the configured circuit. 3 of "/Mielation Execution Unit" (3) which applies pattern gold and executes staining
It is made up of several departments. Each of the above parts will be explained in more detail below.

FIG. 2 shows an example in which the logic circuit array section t1) is implemented using an LSI. The main part of the above-mentioned array consists of 1-basic circuit element array i' J f41''' and "wiring matrix" (5). Then, the basic circuit element array (4
) is constructed by regularly arranging one type of cell including two NAND gates. It is known that arbitrary logic functions can be realized by combining two NAND gates, but from now on, all logic elements or functional blocks used in general logic circuits will be realized by combining and interconnecting the above cells. (This can be realized as follows. For example, two-person OR is as shown in Figure 3.
The OR output (q) is obtained for the inputs (5) and (B).

For example, as a cell of a basic circuit element array, 3-man power NO.
Other basic logical dates such as R may also be used, and
More basic transistor combination frames may also be used.

Furthermore, it is not limited to one type of wiring, and two or more types of cells may be arranged. %v)5, an example of its realization is, for example, by connecting a plurality of conductor pieces and connecting them as shown in FIG. This is a regularly arranged array of switches for releasing c and d. In addition, (7a) indicated by a solid line in FIG. 4 is the first layer conductor, (7b) is the second layer thick body,
(8) shows a switch that connects each conductor. By opening and closing each switch, arbitrary mutual wiring can be realized. The method of laying out the conductor pieces and switches is not limited to that shown in FIG. 4, and other methods may be used. Wiring mark IJ box 1! As an example of how to realize this with cL8I, a conductor piece can be formed into a diffusion layer, a polycrystalline silicon layer,
Or make it with an aluminum layer etc. and make the switch MOS.
It can be configured with a transistor, a floating gate type MOS transistor, or the like. When these transistors are used as gold switches, it is well known that the switch is made conductive by storing charge in the gate of the transistor, and the switch is disconnected by discharging it. A specific gate can be fully charged (this can be achieved by applying a potential through another wiring layer, or by using an electron beam, laser beam, etc.). A method of melting the fuse may also be used.

An example of the configuration of the circuit configuration section is shown in Figure 1, which includes a connection information input section (9) for inputting connection information of the ethical circuit to be simulated, and a logic circuit array realizing the circuit based on the input information. (tio) for determining the allocation of circuit elements to cells and the opening/closing of each switch in the wiring matrix.

It consists of three parts: wiring implementation part I for realizing the above-determined switch by electrical, electronic or optical means.
A keyboard or the like can be used. The wiring pattern determination unit u1 for determining the cell allocation of circuit elements and the opening/closing determination of switches incorporates a microcomputer or other combination device, and contains therein a program for determining the optimum layout. Furthermore, it goes without saying that the wiring implementation unit Uυ that fully realizes the opening and closing of the switch has different principles depending on the structure of the wiring matrix.

As shown in Fig. 1, the configuration of the simulation section is as follows: a test series human section that manually generates information on the input test series that should excite the logic circuit and the expected output value of the circuit, and a logic circuit layout section that inputs the test inputs. a simulation control unit for applying a simulated voltage to the circuit and operating the circuit in a simulated manner;
131. It consists of an internal state reading section d41 which outputs the state of any part of the circuit in operation, and a simulation result output section 115+ which compares it with an expected value and outputs a simulation result t40. In addition, 7) memory storage is provided to store test series, expected output values, or actual output values.

Although the above embodiment is an example in which the logic circuit array section is implemented using LSI, it is possible to use a plurality of LSI chips or LSI wafers in conjunction to simulate a large-scale circuit.

As another embodiment, for example, a part of the module 7 side part can be incorporated into the same LSI as the logic circuit array part.

Furthermore, as another embodiment, the logic circuit array section can be realized using a hybrid IC, a printed board, or the like other than an LSI.

As yet another embodiment, a part of the circuit to be simulated, for example, the memory part, is not realized in the first part of the logic circuit array part, but isometrically simulated by a storage device prepared elsewhere. .

〔Effect of the invention〕

This invention has the following effects.

First, since a circuit equivalent to the circuit to be simulated is configured in hardware, it is possible to simulate the operation of the actual circuit at a speed that is quite close (within one order of magnitude). Dramatically compared to Elle/Go/
(more than 2 orders of magnitude) in a short time, so it is possible to achieve almost complete motion simulation within a practical amount of time.

Furthermore, compared to large-scale computers that use Noft Wafer/Murray 7 Yonni, it is a specialized hardware, so it is less
is small and therefore can be realized with low complexity. Since it is possible to simulate at even higher speeds, it is expected that the performance cost of simulation will become even lower.

In addition, when compared with conventional breadboards, this device has the advantage of being versatile and can be used for drying and drying, which saves money.

Furthermore, compared to the time it takes to create a breadboard, this invention only requires the input of circuit connection information, which means that you can start working on your knowledge in a short period of time, and that you can make corrections to your circuit design. It has advantages such as being extremely easy.

When this device is used to design an LSI or the like, the circuit connection information and test series can be used in common with the data of the LSI design system, which has a remarkable effect on shortening the overall period of the LSI design process.

[Brief explanation of drawings]

The drawings depict one embodiment of the present invention; FIG. 1 is a block diagram showing the configuration of a logic circuit simulation device, FIG. 2 is a front view showing a part of the logic circuit array section, and FIG. 3(a)
, (1)) are all circuit diagrams showing the configuration of logic elements or distance blocks, Figure 4 (a) is a front view showing the structure of the wiring matrix, and Figure 4 (b) is equivalent to Figure (a). FIG. l Logic circuit array section 2 Circuit configuration section 3 Simulation execution section 4 Basic circuit element array 5 of the logic circuit array section Wiring matrix 6 of the logic circuit array section Human output pad and buffer 7a
First layer thick body 7b Second layer thick body 8 Switch (interconductor connection) 9 Connection information input section 10 of circuit configuration section
Wiring pattern determination section 11 of the circuit configuration section Wiring execution section 12 of the circuit configuration section
Test series human power section 13 of simulation execution section Simulation control section 14 of simulation execution section Internal state reading section 15 of simulation execution section Simulation result output section 20 of simulation execution section Circuit connection information 30 Test series information 40 Simulation result agent Patent attorney Inoue - Male No. 1 No. 2 Figure 3 (α) tb> Figure 4

Claims (1)

[Claims] A logic circuit array having a plurality of basic circuit elements, conductor pieces, and switches regularly arranged; and means for setting the state of each switch to make the logic circuit array isometrically equal to a logic circuit to be simulated. , means for operating the circuit by applying an input test sequence to the equivalent logic circuit.