JPH0677047B2 - Selective connection method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention arranges a plurality of horizontal lines and a plurality of vertical lines in a matrix, and turns on and off the intersections of the vertical lines and the horizontal lines to turn the vertical lines and the horizontal lines. The present invention relates to a method of selectively connecting intersections in a relay matrix for connecting and disconnecting the two, which can be suitably used for testing an electric circuit of a printed board and the like.

[Conventional technology]

FIG. 6 is a circuit diagram showing a circuit connection when the relay matrix is used for testing an electric circuit of a printed board.

In the figure, 101 is a printed board, 102 is a voltmeter, A1 to A2
56 is a vertical line (vertical connection line), B1 to B16 are horizontal lines (horizontal connection line), C1 to Cn are input / output terminals of the printed board 101, a1b1 to a25
6b16 are contacts of relays A1B1 to A256B16 (not shown) (shown in FIG. 7 described later). In this example, 256
40 at the intersection of 16 vertical lines and 16 horizontal lines (matrix intersection)
In the example, 96 (256 x 16) contacts are arranged.

In FIG. 6, terminals C1 and C2 from the printed board 101 are shown.
To connect to the voltmeter 102, contact a1b1 and contact a10
By turning on 1b1, terminal C1-horizontal line B1-vertical line A101
And forming the first circuit, the contact a2b2 and the contact a102
By turning on b2, a second circuit composed of the terminal C2-horizontal line B2-vertical line A102 may be formed.

Similar to the voltmeter 102, if a voltage generator or a counter is connected in a vertical line, it can be freely connected to a desired terminal of the printed board 101, and the electric circuit of the printed board 101 is tested. be able to.

Since the horizontal line B has 16 lines B1 to B16, the number of circuits that can be formed as independent circuits is limited by the number of horizontal lines B, and it will be understood that the maximum number is 16.

FIG. 7 is a circuit diagram showing a relay control circuit corresponding to the relay matrix of FIG.

In FIG. 7, 1 is a data processing device such as a microcomputer, 11 is a central processing unit (CPU), and 12 is a memory unit (R).
AM), 13 is a digital output section (DO), 2 is an address bus, 3 is a data bus, 4 is a control signal line, L1 to L256 are latch circuits, and A1B1 to A256B16 are relays.

It is assumed that the memory unit (RAM) 12 in the data processing device 1 stores data such as which intersection of the matrix intersections in the relay matrix shown in FIG. 6 and which intersection should be turned on.

Based on the read data, the CPU 11 that has read this data calculates which of the relays A1B1 to A256B16 should be turned on, and the result is the latch circuit L1 to
The L256 address and the data in one latch circuit are output via the digital output unit (DO) 13.

The address signal is output via the address bus 2 (in this case, 8 bits are required to represent 256 addresses, so 8 signal lines are required as the address bus), and for example, the latch circuit L1 If so, L1 is specified.

Since 16 relays belong to one latch circuit, data indicating which of the 16 relays is selected is output to the data bus 3. As a result, if the relay A1B1 belonging to the latch circuit L1 is designated, the relay A1B1 is turned on by the write signal (WT) given from the data processing device 1 side via the control signal line 4.

Thus, in the relay matrix of FIG. 6,
The vertical lines A1 to A256 and the horizontal lines B1 to B16 can be freely connected.

[Problems to be Solved by the Invention]

In the description of the prior art described above, it is said that the memory unit (RAM) 12 in the data processing device 1 shown in FIG. 7 should be turned on at which intersection among the matrix intersections in the relay matrix shown in FIG. It said that various data are stored.

A display example of such data in the prior art is shown in FIG.
Is shown in. That is, FIG. 8 (a) shows a horizontal line B1 and a vertical line A1.
Connecting horizontal line B1 and vertical line A2, horizontal line
It shows a display example of data consisting of five instructions of connecting B2 and vertical line A3, connecting horizontal line B2 and vertical line A4, and connecting horizontal line B2 and vertical line A5.

When this data (five instructions) is executed, Fig. 8 (b)
The connection state is as shown in. Considering this connection state, this is essentially due to the two instructions of connecting vertical lines A1 and A2 and connecting vertical lines A3, A4 and A5 (however, respectively In the connection of, the separate horizontal line B is used, and the horizontal line B is B1 to B1.
If there are six 16 lines, there is an implicit assumption that any free horizontal line can be used).

FIG. 8C shows such two instructions displayed as data. That is, what is described with reference to FIG. 8 is that, as the data for instructing the connection as shown in FIG. 8B, conventionally, complicated data including five instructions as shown in FIG. Although it was necessary, if this could be done with simple data consisting of two instructions, as shown in Fig. 8 (C), the required amount of information would decrease,
It is very convenient.

An object of the present invention is to provide a desired connection without specifying a horizontal line (bus) by specifying only a vertical line terminal to be connected as data for instructing a desired connection in a selective connection method in a relay matrix. It is to provide a selective connection method that can be realized.

[Means for Solving the Problems]

To achieve the above object, in the present invention, a plurality of horizontal lines in parallel and a plurality of vertical lines in parallel are arranged in a matrix, and the intersections of the vertical lines and the horizontal lines are turned on, whereby each of the vertical lines is Of the terminals belonging to, at least two desired terminals are connected via a horizontal line that is unique to each other, and when a circuit is completed, one terminal is designated to specify a required terminal that constitutes one circuit. When one or more sets of information are given, determine the horizontal line corresponding to each, and in the selective connection method that turns on the intersection point to form one or more circuits, if terminal designation information is newly given, First to remember
A memory (51) and a second memory that stores the terminal designation information and horizontal line information corresponding to the existing circuit established at that time as old connection information in association with each circuit.

[Action]

A synthesis processing step of synthesizing the new terminal designation information read from the first memory and the terminal designation information in the old connection information read from the second memory to create terminal designation information to be realized; When the terminal designation information to be realized includes overlapping terminal designation information, the grouping processing step of grouping them and the terminal designation information to be realized after the grouping processing are set to the old connection information ( The old connection information is stored as much as possible in comparison with the terminal designation information and horizontal line information), and the required horizontal lines are assigned as a bus to the terminal designation information to be realized after the above-mentioned grouping process, and the final connection information (to be realized). Bus determination processing step for creating terminal designation information and horizontal line information), comparing the final connection information with the old connection information, and determining the end of the old connection information that overlaps with the final connection information. If there is designating information, leave the pin designating information and the horizontal line information corresponding to it, erase the others to make it empty, and then, for the pin designating information that does not overlap with the old connection information of the final connection information, By selecting a horizontal line and assigning it, it is actually turned on,
A relay control step of determining and executing a matrix intersection point to be turned off and a step of storing the final connection information in the second memory are executed.

Hereinafter, a more specific description will be given with reference to FIGS. 5A to 5C so that the features of the selective connection method according to the present invention can be understood. 5A to 5C are explanatory views illustrating the selective connection method according to the present invention.

It should be noted that the present selective connection method can be said to essentially have a certain connection status in the relay matrix and change it to realize a new connection status. Therefore, description will be given below from such a viewpoint. .

Please refer to FIG. 5A. (A) shows the connection status up to that point (old connection status) in the relay matrix. That is, the vertical line P1 and the horizontal line B1 are connected, and the vertical line P2 and the horizontal line B1 are also connected (in other words, the vertical lines P1 and P2 are connected via the horizontal line B1).

In this situation, it is assumed that a new instruction is given to connect the vertical lines P2 and P3. So when I received this instruction,
As shown in FIG. 5A (b), even if the vertical lines P2 and P3 are connected via the horizontal line B2, it can be said that the instruction is satisfied.

However, in this case, as shown in FIG. 5A (c), there is no substantial difference from connecting the vertical lines P1, P2, P3 via one horizontal line B1, but the required horizontal line is ,, B1 and B2 2
This is necessary, and it is uneconomical to use horizontal lines. (The number of horizontal lines limits the number of independent circuits. Therefore, wasteful use of horizontal lines reduces the number of independent circuits required. It is necessary and inconvenient).

Therefore, in the present invention, when the above instruction is given, the connection shown in FIG. 5A (b) is not taken, but the connection shown in FIG. 5A (c) is taken to effectively use the horizontal line (bus). The first feature is that it can be achieved.

Refer to FIG. 5B. (A) shows the connection status up to that point (old connection status) in the relay matrix. That is, the vertical lines P1 and P2 are connected via the horizontal line B1, and the vertical line P3
And P4 are connected via a horizontal line B2.

In this situation, connect vertical lines P3 and P4
Suppose that it is instructed to connect P5 and P6. Therefore, when this instruction is received, the connection of (a) is abolished, and as shown in FIG. 5B (b), the vertical lines P3 and P4 are connected via the horizontal line B1, and the vertical lines P5 and P6 are connected. Can be said to satisfy the instruction even if it is connected via the horizontal line B2.

However, with this, as shown in Figure 5B (a) showing the old connection state,
Comparing (b), the vertical lines P3 and P4, which were connected via the horizontal line B2 in (a), are now connected via the horizontal line B1 in (b). In the process of executing instructions,
A temporary disconnection state may occur between the vertical lines P3 and P4, which may be inconvenient.

Therefore, in the present invention, when the above-mentioned instruction is given, the connection as shown in FIG. 5B (c) is not adopted, but the connection as shown in FIG. 5B (c) is adopted. The second point is that the contents of the connection state are left as they are without any change, and the occurrence of a temporary disconnection state is avoided.
It is a feature of.

Refer to FIG. 5C. (A) shows the connection status up to that point (old connection status) in the relay matrix. That is, the vertical line V and P1 are connected via the horizontal line B1, and the vertical line G
And P2 are connected via a horizontal line B2.

In this situation, it is assumed that it is newly instructed to connect the vertical lines V and P2 and connect the vertical lines G and P1. Therefore, when receiving this instruction, if the vertical lines V and P2 are connected via the horizontal line B1 as shown in FIG.
There is a case where a short circuit (short circuit) from G to G is formed, which is inconvenient.

Therefore, in the present invention, when the above instruction is given, the contents (connection between V and B1 and connection between G and B2) left in the old connection state are left as they are, as shown in FIG. 5C (c). ,
The rest is abolished, and instructions are executed on that to shift to the state shown in Fig. 5C (D) to avoid the occurrence of a temporary short circuit state. This is the third feature.

〔Example〕

Next, examples of the present invention will be described. FIG. 1 is a flow chart showing an embodiment of the present invention. FIG. 2 is a functional block diagram functionally showing the processing of the present invention.

In FIG. 2, 51 is a connection command information storage means (see FIG. 7).
It corresponds to the RAM12 and stores new connection instruction data), 55 is the old connection information storage means that stores the previous connection status in the relay matrix, and 52 is the planned connection information storage means (new connection instruction data and (Means for storing the connection status to be realized obtained from the connection status up to that point), 53
Is a collective connection information storage means, 54 is a final connection information storage means, and 56 is a relay control circuit.

In addition, in FIG. 2, is a combining process, is a grouping process, is a bus determination process, and is a relay control process, and corresponds to that shown in the flowchart of FIG.

First, the outline of the circuit operation will be described with reference to FIG.

If the data stored in the connection command information storage means 51 is the connection instruction data (terminal designation information) to be newly added, it is read out and the old connection information storage means 55 is read.
Data representing the connection state up to that point (specifically, the terminal designation information in the data consisting of the terminal designation information and the horizontal line information) is synthesized to obtain the data of the connection state to be actually realized. It is created as (terminal designation information) and stored in the planned connection information storage means 52.

The processing of this synthesis processing step is performed when an intersection that is currently turned on (that is, an old connection) is left as it is and a new intersection is added (when a connection is added).
When adding a new intersection to turn off some or all of the old connections (when updating the connections), the contents of the connection command information storage means 51 are directly used as the contents of the planned connection information storage means 52, and the combining processing is performed. The processing of the step is not performed, and the process proceeds to the next grouping processing.

Next, the planned connection information (terminal designation information as data representing the connection state to be actually realized) is read from the planned connection information storage means 52, and if there is an overlapping portion, the overlapping portions are merged into one. After applying the summary process,
The connection information storage means 53 stores the information.

Next, a bus determination process is performed on the grouped connection information (terminal designation information) after the grouping process read out from the grouped connection information storage unit 53. In the bus determination process, the collective connection information (terminal designation information) is compared with the old connection information (terminal designation information and horizontal line information) read from the old connection information storage means 55,
The old connection information is saved as much as possible, the horizontal connection is assigned to the collective connection information (terminal designation information) as a bus, and the final connection information (terminal designation information and horizontal line information) is created and stored in the storage means 54. To do.

Next, relay control processing is applied to the final connection information (terminal designation information and horizontal line information) read from the final connection information storage means 54.

In the relay control process, the final connection information (terminal designation information and horizontal line information) is compared with the old connection information (terminal designation information and horizontal line information) read from the old connection information storage means 55, and the old connection information overlaps with the final connection information. If there is pin designation information that is being used, leave the pin designation information and the horizontal line information corresponding to it, and erase the others to make it empty, and then, for the pin designation information that does not overlap with the old connection information of the final connection information. hand,
By selecting and allocating the required horizontal lines, the matrix intersection points to be actually turned on and off are determined and executed. The execution is performed in the relay control circuit 56.

Thereafter, the stored contents of the final connection information storage means 54 are copied (transferred) to the old connection information storage means 55 as a processing step to prepare for the next operation.

It will be apparent that FIG. 1 is a flow chart in which the processing steps 1 to 3 in the above-described operation outline are summarized in time series.

Next, the processing steps (1) to (3) will be specifically described with reference to specific examples. Before that, the data format will be described with reference to FIGS.
It will be described with reference to the drawings.

FIG. 3 is an explanatory diagram showing the configuration of each storage means, and FIG. 3A is an explanatory diagram showing a display example of the stored contents.

As shown in FIG. 3, each storage means has a width of 16 words (256 words) corresponding to the intersection of the relay matrix of FIG.
(Bit), vertical 16 words matrix configuration.

Each of the 256 bits forming the horizontal 16 words corresponds to each of the relays A1 to A256, and the data of one horizontal line is
It represents one connection data. In the final connection information storage means 54 and the old connection information storage means 55 shown in FIG. 2, the rows display the buses (horizontal lines) B1 to B16 as they are.

In the display example of FIG. 3A, in the first row of the matrix, 12, 16,
Each bit position (matrix intersection) of 129 is on, in the 2nd row, each bit position (matrix intersection) of 3, 5, 10 is on, and in the 3rd row, all bit positions (matrix intersection) are off 4 rows The eye indicates that each of the 4 and 20 bit positions (matrix intersections) is on, and the other rows are all bit positions (matrix intersections) off.

Now, each of the processing steps (1) to (4) will be specifically described with reference to FIGS. 4A to 4D.

First, FIG. 4A is an explanatory diagram used for explaining the combination processing step.

FIG. 4A (a) shows the old connection information. That is,
The intersections 3 and 4 are connected to the first circuit through the horizontal line B1 (here, the intersections 3 and 4 are the terminal designation information, and the horizontal line B1 is the horizontal line information), and the intersections 9 and 10 are Horizontal line B3
And a second circuit connected via (where the intersections 9 and 10 are the terminal designation information and the horizontal line B3 is the horizontal line information).

On the other hand, it is assumed that the connection command information is given as shown in FIG. 4A (b). That is, the connection command information indicates that the intersections 4 and 6 should be connected (using an empty horizontal line somewhere) to form the third circuit.

Therefore, FIG. 4A (c) shows the planned connection information as a result of combining the connection command information and the old connection information. As described above, the synthesizing process is performed by paying attention to the terminal designation information.
As the result of the synthesizing process (planned connection information), only the terminal designation information is displayed by filling the empty horizontal lines (buses) (that is, the horizontal line information corresponding to the terminal designation information is undecided at this stage). ).

The following is a generalization of the processing of the above-described combining processing step and a description of the flowchart of the combining processing of FIG. 9A.

First, the means for storing old connection information from the old connection information storage means 55
The memory blocks are read out in the order of 55 storage blocks, and are sequentially stored in the storage blocks of the planned connection information storage means 52 (step 1
5), when all of the old connection information from the storage means 55 has been transferred to the planned connection information storage means 52 (step 6), the connection command information is read from the connection command information storage means 51 in the order of the storage blocks of the storage means 51. Planned connection information storage means 52
, The blocks next to the last block in which the old connection information is stored in step 4 are sequentially packed and stored (step 7
11 to 11), it is confirmed that all of the connection command information from the storage means 51 has been transferred to the planned connection information storage means 52 (step 9 or 12), and the combining process ends. If the stored data of the block m read out from the storage means 51 in step 9 does not include the intersection data, the processing ends.
This is because it is premised that the connection instruction information is stored in the storage means 51 in ascending order from the youngest address.

As described above, the processing of this combining processing step is performed in the case of connection addition, and in the case of connection update, the contents of the connection command information storage means 51 are stored in the planned connection information storage means 52 as they are. The contents are not included, and the processing of the combining processing step is not performed.

Next, FIG. 4B is an explanatory diagram used for explaining the grouping processing step.

FIG. 4B (a) shows the planned connection information. That is, the first circuit in which the intersection points 3 and 4 are connected (using an empty horizontal line) and the second circuit in which the intersection points 5 and 9 and 10 are connected (using an empty horizontal line) And the third circuit to which the intersection points 4 and 8 are connected (using an empty horizontal line somewhere) is a planned connection.

Here, the planned connection information in Fig. 4B (b) is shown in Fig. 4A (c).
It is different from the planned wiring information of. If this is explained using a consistent example throughout the processing steps, the planned connection information in FIG. 4B (a) should be the same as the planned connection information in FIG. 4A (c), but here, For convenience of explanation of the processing steps, a convenient example is assumed for each case, and thus such a case may differ.

The summarizing process is performed as follows. That is, Fig. 4B (B)
, The terminal designation information “4” is in the first line, and the terminal designation information “4” is also in the third line. Therefore, if you put them together into one, the result will be as shown in Figure 4B (b). Physically speaking, the command "Connect intersection points 3 and 4" and the command "Connect intersection points 4 and 8" are "connect the intersection points 3 and 4 and 8"
It means that they can be combined into one directive.

This process is a process that helps limit the number of horizontal lines used to a minimum number (see the above explanation given with reference to FIG. 5A).

Generalizing the processing of the above summary processing step,
The explanation will be given below with reference to the flowchart of the summarizing process in the figure.

The storage contents (intersection data) of the storage blocks of the planned connection information storage means 52 are sequentially compared between the storage contents of the blocks having the smaller addresses and the storage contents of the blocks having the larger addresses (steps 1 to 6). If there is a storage block in which the intersection data matches even in part, the contents of the block with the smallest address that stores the matching data
The contents of the other memory blocks having the matching data are rewritten together so that the intersection data does not overlap (step 7), and the address n having the matching intersection data is written.
When the comparison of the contents of the memory block having a larger address than the contents of the memory block is completed (step 10), the contents of the memory block at the address n are collected and sequentially packed into the memory block of the connection information memory means 52. Stored (step 11), and then the contents of the memory block at address n are cleared to zero (step 1).
2). Here, all storage blocks of the planned connection information storage means 52 are compared (step 14), and the grouping process is ended.

Both the number of storage blocks in the old connection information storage means 55 and the number of storage blocks in the connection command information storage means 51 correspond to the number of horizontal lines (buses), and in the example of the sixth illustration, 16 in each case.
However, in the case of additional processing, the connection command information storage means 51
For, only the connections to be added to the number of old connections are entered, so
The number of storage blocks in the planned connection information storage means 52 will be 16 pieces.

In addition, in the case of the update processing, it is not necessary to execute the processing of the grouping processing step, but by performing the grouping processing step, it is possible to check the duplication of the intersection point data to be turned on in the connection command information.

FIG. 4C is an explanatory diagram used for explaining the bus determination processing step.

It is assumed that Fig. 4C (a) shows the collective connection information,
It is assumed that the figure (b) shows the old connection information. It should be noted that the summary connection information is composed only of the terminal designation information, and the old connection information is composed of the terminal designation information and the horizontal line information corresponding thereto.

The bus determination process compares the collective connection information with the old connection information, maintains the old connection information as much as possible, and assigns the horizontal line as a bus to the pin specification information that makes up the collective connection information to create the final connection information. As described above, the processing is performed. The final connection information created in this way is
It is shown in Figure 4C (c).

Comparing Fig. 4C (a) and Fig. 4C (b), the first line "3, 4, 6" of the summary connection information is "B2,
It can be seen that there is an overlap with "3, 4, 7". Therefore, in the form of saving "B2,3,4,7" on the second line of the old connection information as much as possible,
If "3,4,6" in the first line of the summary connection information is to be realized, it is better to assign a horizontal line B2 to this and set it to "B2,3,4,6". And that becomes the final connection information (Fig. 4C (c)).

"5,11" on the 3rd line of Figure 4C (B) (collective connection information)
Overlaps with "B4,5,11" in Figure 4C (b) (old connection information). Therefore, if you want to realize "5,11" in the third line of the collective connection information by saving the old connection information "B4,5,11", assign a horizontal line B4 to this and add "B4,5,11". I find it better to say And that is the final connection information (No.
4C (C)).

This process is a process useful for avoiding the occurrence of the temporary disconnection process as much as possible (see the above description performed with reference to FIG. 5B).

By generalizing the processing of the above bus determination processing step,
It will be described below with reference to the flow chart of the bus determination processing in FIG. 9C.

First, with reference to the stored contents (old intersection data) of the old connection information storage means 55, the old intersection data of this storage means 55,
The stored contents (intersection data) of the collective connection information storage unit 53 are sequentially compared (steps 1 to 5), and the collective connection information storage unit has intersection data that partially matches the old intersection data.
The contents of the storage block of 53 are stored in the storage block of the final connection information storage means 54 to which the same address (bus address) as the address of the block of the storage means 55 having the coincident intersection data is given, and then the storage means. The contents of the memory block 53 are cleared to zero (step 6). After this processing is performed for all the stored contents of the storage means 53, only the intersection data remaining in the storage means 53 does not match the old intersection data at all. The data is stored in the connection information storage means 55 (steps 12 to 15), and the bus determination processing step is ended.

FIG. 4D is an explanatory diagram used for explaining the relay control processing step.

It is assumed that FIG. 4D (a) shows the old connection information and FIG. 4D (b) shows the final connection information.

The relay control process compares the final connection information with the old connection information, and if there is terminal specification information that overlaps with the final connection information in the old connection information, leaves the terminal specification information and the corresponding horizontal line information, and To make it free, then
It is a process that determines the matrix intersection points that should actually be turned on and off and makes it executable by selecting and allocating the required horizontal lines for the pin specification information that does not overlap with the old connection information of the final connection information. Said earlier.

Therefore, comparing Figure 4D (a) and Figure 4D (b),
Since the second line "B2,3,4,7" in Figure (a) and the second line "B2,3,4,6" in Fig. 4D (b) have an overlapping part, the overlapping part ""B2,3,4" is left as shown in Fig. 4D (c), and the fourth line "B4,5,11" in Fig. 4D (a) and the fourth line "B4 in Fig. 4D (b)" , 5,11 ”are duplicated,
Leave it as shown in Fig. 4D, and erase the remaining part of Fig. 4D to make it empty as shown in Fig. 4D.

Then, the remaining part of Fig. 4D (b) is executed.

This process is a process that helps avoid the occurrence of a temporary short-circuit (short-circuit) state (see the above description performed with reference to FIG. 5C).

Generalizing the above relay control processing steps,
The flow chart of the relay control process and the data transfer process of FIG. 9D will be described below.

The storage content of the old connection information storage means 55 and the storage content of the final connection information storage means 54 (the address of the storage block of the storage means 55 and the address of the storage block of the storage means 54 correspond one to one, and the address of the storage block is Horizontal lines (bus addresses) are sequentially compared for each same address in both storage means 54 and 55 (steps 1 to 3), and the contents of both storage means (intersection data and old intersection data) do not match. In this case, the intersection which has been on and which is on the bus designated by the address and designated by the old intersection data indicating the mismatch is turned off (step 4). After all the processes up to this point have been performed (step 6), the intersection data of the final connection information storage means 54 is searched for the intersection data that should be turned on except the intersection that was turned on by the old connection, and that intersection is turned on. (Steps 9 and 10). Through this process, if the intersection data and the old intersection data match, the intersection remains on.

It should be noted that steps 13 and 14 correspond to the processing steps of transferring the stored contents (intersection data) of the final connection information storage means 54 to the old connection information storage means 55 and rewriting the old connection information storage means 55, and the final connection information storage Memory contents of means 54 (intersection data)
Is transferred to the old connection information storage means 55, the old connection information storage means 55 is rewritten with the transferred intersection data, and the final connection information storage means 54 is cleared to zero to prepare for the next connection switching.

〔The invention's effect〕

As described above, according to the present invention, in the selective connection method in the relay matrix, if only the terminal of the vertical line to be connected is specified as the data for instructing the desired connection, the horizontal line (bus) need not be specified. However, there is an advantage that a desired connection can be realized.

Further, at that time, there is an advantage that the horizontal line (bus) can be effectively used by the grouping process, the temporary disconnection can be avoided by the bus determination process, and the temporary short circuit can be avoided by the relay control process.

[Brief description of drawings]

FIG. 1 is a flow chart showing an embodiment of the present invention,
FIG. 3 is a functional block diagram showing an embodiment of the present invention, FIG. 3 is an explanatory view showing a memory configuration of a storage means used in the embodiment of FIG. 2, FIG. 3A is an explanatory view showing a display example of stored contents,
FIG. 4A is an explanatory diagram for explaining the combining process, FIG. 4B is an explanatory diagram for explaining the grouping process, FIG. 4C is an explanatory diagram for explaining the bus determination process, and FIG. 4D is a relay control process. 5A to 5C are explanatory diagrams for explaining the features of the selective connection method according to the present invention, FIG. 6 is a circuit diagram showing a relay matrix, and FIG. 7 is a sixth diagram. FIG. 8 is a block diagram showing a relay control circuit corresponding to the figure, and FIG. 8 is an explanatory diagram showing a relation between connection command data and a connection state,
FIG. 9A is a flowchart of the combining process, FIG. 9B is a flowchart of the grouping process, a flowchart of the bus determination process of FIG. 9C, and a flowchart of the relay control and data transfer process of FIG. 9D. Explanation of reference numerals 1 ... Data processing device, 11 ... Central processing unit (CPU), 12
...... Memory section, 13 ...... Digital output section (DO), 2 ......
Address bus, 3 ... Data bus, 4 ... Control signal line,
51 to 55 ...... Memory means, 56 ...... Relay control circuit

Claims (1)

[Claims] 1. A plurality of parallel lines extending in one direction (hereinafter, each line is referred to as a horizontal line) and a plurality of parallel lines extending in a direction intersecting with the one direction (hereinafter, each line is referred to as a vertical line). ) And are arranged in a matrix and the intersections of the vertical lines and the horizontal lines are turned on, so that between any desired at least two terminals among terminals belonging to each of the plurality of vertical lines,
When one circuit is formed by connecting it through its own horizontal line, if one or more sets of terminal designating information designating the required terminals that configure one circuit are given, the corresponding horizontal line is determined. Then, in the selective connection method of turning on the intersection point to form one or a plurality of circuits, the first memory (51) which stores the terminal designation information when newly given, and which is established at that time A second memory for storing the terminal designation information and horizontal line information corresponding to the existing circuit that is associated with each circuit and stored as the old connection information, and the new terminal designation read from the first memory is provided. The information and the terminal specification information in the old connection information read from the second memory are combined to create terminal specification information to be realized, and the terminal specification information to be realized overlaps. When the child designation information is included, the grouping processing step of gathering them together and the terminal designation information to be realized after the grouping processing are compared with the old connection information (terminal designation information and horizontal line information), A bus that stores the old connection information as much as possible and allocates the required horizontal lines as a bus to the pin designation information to be realized after the grouping process, and creates the final connection information (pin designation information and horizontal line information to be realized). Determination processing step, comparing the final connection information and the old connection information, in the old connection information, if there is terminal designation information that overlaps the final connection information, leave the terminal designation information and the horizontal line information corresponding thereto, It is actually turned on by erasing the others to make it empty, and then selecting and assigning the required horizontal line to the pin specification information that does not overlap with the old connection information of the final connection information.
A selective connection method comprising: a relay control step of determining and executing a matrix intersection point to be turned off; and a step of storing the final connection information in the second memory.