JPS63153670U - - Google Patents
Info
- Publication number
- JPS63153670U JPS63153670U JP4855287U JP4855287U JPS63153670U JP S63153670 U JPS63153670 U JP S63153670U JP 4855287 U JP4855287 U JP 4855287U JP 4855287 U JP4855287 U JP 4855287U JP S63153670 U JPS63153670 U JP S63153670U
- Authority
- JP
- Japan
- Prior art keywords
- pair
- input terminals
- resistors
- transistor
- midpoint
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
Description
第１図は本考案の一例の構成図、第２図はその
説明のための図である。
１ａ，１ｂは入力端子、２は電源端子、３，４
，５，６１，６２は抵抗器、６３はトランジスタ
、７はコンデンサ、８は論理回路、９ａ，９ｂは
ダイオードである。
FIG. 1 is a block diagram of an example of the present invention, and FIG. 2 is a diagram for explaining the same. 1a, 1b are input terminals, 2 is power supply terminal, 3, 4
, 5, 61, and 62 are resistors, 63 is a transistor, 7 is a capacitor, 8 is a logic circuit, and 9a, 9b are diodes.
Claims (1)
対の入力端子間に所定の電位差が与えられたとき
に負荷を動作状態に制御する入力回路において、 上記所定の電位差より低い電圧の供給される電
源端子と上記一対の入力端子の一方との間に少く
とも第１〜第４の分圧用抵抗器が直列に接続され
、 上記第１、第２の抵抗器の接続中点から出力端
子が導出され、 上記第２、第３の抵抗器の接続中点に上記一対
の入力端子の他方が接続され、 上記第３、第４の抵抗器の接続中点がトランジ
スタのベースに接続されこのトランジスタのエミ
ツタが上記一対の入力端子の一方に接続されると
共に、このトランジスタのコレクタが上記出力端
子に接続されてなり、 上記出力端子に低電位動作の上記負荷の制御信
号が取出されるようにした入力回路。[Claims for Utility Model Registration] An input circuit that is provided with a pair of input terminals and controls the load to an operating state when a short circuit is applied between the pair of input terminals or when a predetermined potential difference is applied between the pair of input terminals. At least first to fourth voltage dividing resistors are connected in series between a power supply terminal to which a voltage lower than the predetermined potential difference is supplied and one of the pair of input terminals; An output terminal is derived from the connection midpoint of the second and third resistors, the other of the pair of input terminals is connected to the connection midpoint of the second and third resistors, and the third and fourth resistors are connected to each other. The midpoint of the connection is connected to the base of the transistor, the emitter of this transistor is connected to one of the pair of input terminals, and the collector of this transistor is connected to the output terminal. An input circuit from which the control signal for the load mentioned above is taken out.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4855287U JPS63153670U (en) | 1987-03-30 | 1987-03-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4855287U JPS63153670U (en) | 1987-03-30 | 1987-03-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63153670U true JPS63153670U (en) | 1988-10-07 |
Family
ID=30870190
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4855287U Pending JPS63153670U (en) | 1987-03-30 | 1987-03-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63153670U (en) |
-
1987
- 1987-03-30 JP JP4855287U patent/JPS63153670U/ja active Pending
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