JPS63151068A - Coms semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To prevent the breakdown of elements due to latch-up and to improve the reduction in chip size and the yield rate, by forming MOS transistors having different conductivities of channel regions in a plurality of single crystal islands, which are insulated with a dielectric film, and forming one of them by a self-aligning method so as to have a doublediffusion structure. CONSTITUTION:Two P-type conductive diffused layer having the different polarity with respect to single crystal islands are formed in one of a plurality of single-crystal islands 13, and a P-channel type MOS transistor 18 is formed. Then, P-type conductive diffused layers 19 having the different polarity with respect to single-crystal islands are formed in one of other single crystal islands 13, and an N-channel type MOS transistor 24 is formed. The transistor 24 is formed by double diffusions in self-aligning manner. Then, gate terminals 17, 22 and 23 and drain terminals 15 and 21 of the transistors 18 and 24 are short-circuited by wiring layers. A source terminal 20 of the transistor 24 is connected to the side of a negative potential with a wiring layer. A source terminal 16 of the transistor 18 is connected to the side of a high potential with a wiring layer. In the CMOS semiconductor integrated device obtained in this way, each MOS is formed in the insulated and isolated island. Therefore a punch- through current is not generated from the high-potential side to the low potential side due to a parasitic transistor.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to the structure of a CMOS semiconductor integrated circuit device using a dielectric isolation method.

[Prior art] CMOS semiconductor integrated circuit equipped with a conventional N-channel MOS transistor and a P-channel MOS transistorv
The position c will be explained with reference to FIG.

The CMOS semiconductor integrated circuit device 30 has a P-type well 32 formed in an N-type substrate 31, and a P-type drain terminal 33 and a P-type source terminal 34 outside the P-type well 32.
A P-channel MOS transistor 36 having a gate terminal 35 is formed between the train terminal 33 and the source terminal 34 via an insulating film (not shown). Furthermore, an N-type drain terminal 37 and a source terminal 38 are provided in the P-type well 32, and a gate terminal 39 is provided between the train terminal 37 and the source terminal 38 via an insulating film (not shown). A type MOSt-transistor 40 is formed. These two MOS transistors have their gate terminals 35.39 and drain terminals 33.37 connected to each other in a wiring layer (not shown), and are N-channel type MOS transistors.
The source terminal 38 of the OSI transistor 40 is connected to the negative potential side, and the source terminal 38 of the P-channel MOS transistor 36 is connected to the negative potential side.
4 are connected to the high potential side through wiring layers.

[Problems to be Solved by the Invention] The CMOS semiconductor integrated circuit device with the conventional structure described above uses an odd transistor (a PNPN switch composed of a lateral PNP transistor and a vertical NPN transistor).
As a result, a through current flows from the high potential side to the low potential side (this operation is generally called latch up), which inevitably leads to destruction of the CMOS semiconductor integrated circuit device. type MOS transistor and N
This has disadvantages such as an increase in chip size due to the necessity of geometrically separating the channel type MOS transistors.

SUMMARY OF THE INVENTION An object of the present invention is to provide a CMOS semiconductor integrated circuit device that eliminates element destruction due to latch-up and reduces chip size.

[Means for Solving the Problems] The present invention provides a semiconductor integrated circuit device using a dielectric isolation method, which has a plurality of single crystal islands insulated from each other by a dielectric film, and has a conductive channel region within the islands. different MO of
This is a CMOS semiconductor integrated circuit device characterized in that S transistors are formed, and at least one of them is formed in a double diffusion MOSI structure using self-alignment.

[Example] Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view of a CMOS semiconductor integrated circuit device showing one embodiment of the present invention. In FIG. 1, a dielectric isolation substrate 10 manufactured using a known technique includes a plurality of monocrystalline islands 13 of the same conductivity separated by a dielectric film 12 such as 5i02 in a polycrystalline silicon layer 11. The single crystal near the dielectric film 12 has a high temperature buried layer 14 having the same conductivity as the single crystal island.

Here, for ease of explanation, a case will be described in which a single crystal island has N-type conductivity and a different type of conductivity has P-type conductivity.

Two diffusion layers of P-type charging property, which have polarities different from those of the single crystal islands, are formed on one of the plurality of single crystal islands 13, and one of the diffusion layers is connected to the drain terminal 15, and the other one is connected to the drain terminal 15. one source terminal 1
6, a gate terminal 17 is provided between the drain terminal 15 and the source terminal 16 via an insulating film (not shown),
A P-channel MOS transistor 18 is formed.

Next, a P-type conductive diffusion layer 19 having a polarity different from that of the single crystal island is formed on one of the other single crystal islands 13, and then,
Inside the diffusion layer 19, an N-type conductive diffusion layer having a polarity different from that of the diffusion layer 19, that is, having the same conductivity as the single crystal island, is formed as a source terminal 20, and a dielectric film is formed. 12
The N high concentration buried layer 14 near the drain terminal 21 is assumed to be the drain terminal 21.

Roughly, gate terminals 22 and 23 are provided in the region of the diffusion layer 19 between the source terminal 20 and the drain terminal 21 where P-type conductivity is first diffused via an insulating film (not shown), and the N
A channel type MOS transistor 24 is formed.

The method for forming this N-channel type MOS transistor 24 is a known technique, and is generally a self-aligned double diffusion MOS (D
MOS: Double Diffused MOS
) is called.

Next, the gate terminals 17, 22, 23 and drain terminals 15, 21 of the two MOS transistors 18, 24 are each short-circuited by a wiring layer (not shown), and the N-channel type MO
The source terminal 20 of the S transistor 24 is connected to the negative potential side,
The source terminals 16 of the channel type MOS transistors 18 are connected to the high potential side through wiring layers (not shown), and the CMOS
A semiconductor integrated circuit device 25 is formed.

Here, the description has been given of N-type conductivity as a single crystal island and P-type conductivity as a different type of conductivity, but it goes without saying that this conductivity may be reversed.

In the CMOS semiconductor integrated circuit device jqed in this way, each MOS is formed in an isolated island, so that no through current occurs from the high potential side to the low potential side due to the odd transistor.

[Effects of the Invention] As explained above, the present invention provides MOS transistors whose channel regions have different conductivities within an island insulated and isolated by a dielectric film, and at least one of them is connected to a DMO8 (Double
ble [) fused MOS> structure, it is possible to prevent the formation of odd transistors, eliminate element destruction due to latch-up, and have the effect of reducing chip size and improving yield.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a CMOS semiconductor integrated circuit device showing an embodiment of the present invention, and FIG. 2 is a sectional view of a conventional CMOS semiconductor integrated circuit device. 10... Dielectric isolation substrate 11... Polycrystalline silicon layer 12... Dielectric film 13... Single crystal island 14... High concentration buried layer 15, 21.33.37... Drain terminals 16, 20
．． 34.38...Source terminal 17, 22.23.35
．． 39... Gate terminal 18, 36... P channel type MOS transistor 19... Diffusion layer 24, 40... N channel type MOS transistor 25
, 30...CMOS semiconductor integrated circuit device 31...N
Type board 32...P type twelf Figure 1

Claims (1)

[Claims] (1) A semiconductor integrated circuit device using a dielectric isolation method has a plurality of single-crystal islands insulated from each other by a dielectric film, and MOSs with channel regions of different conductivity are arranged in the islands.
A CMOS semiconductor integrated circuit device comprising transistors, at least one of which is formed in a self-aligned double diffusion MOS structure.