JPS63150968A - Manufacture of mos semiconductor device - Google Patents

Abstract

PURPOSE:To accelerate the operation of an element by forming a P-type impurity layer (P-pocket layer) for preventing a punch through in a self-aligning manner with respect to a gate in a desired small region, thereby reducing the bonding capacities of a source, a drain and a substrate. CONSTITUTION:After a gate oxide film 2 is formed on a P-type semiconductor substrate 1 and a gate electrode 3 is further formed on the film 2, an oxide film 4 is deposited on the whole surface. The film 4 is roughly bonded at a corner region 5 in contact with the electrode 3 and the substrate 1. Thus, an etching is advanced faster than the other region, and a thin oxide film 4a is formed on the region 5. Then, an ion implanted layer for preventing a punch through is implanted to the substrate 1. The film 4a is removed by etching to form by ion implanting source, drain regions 8, 9. Thus, a P-pocket layer 7 for preventing a punch-through is formed in a self-aligning manner with respect to the gate 3 and in the source, the drain and an intrinsic transistor region.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a method of manufacturing a MOS type semiconductor device having a bunch-through prevention layer.

(Prior Art) With the recent increase in the degree of integration of MOS integrated circuits, the miniaturization of elements has become remarkable, but as this miniaturization progresses, problems arise in the characteristics of MOS devices. For example, there is a punch-through phenomenon between the source and drain caused by the drain voltage applied to a short channel MOS transistor. This phenomenon causes deterioration of drain current-gate voltage characteristics in the subthreshold region. In other words, in a short channel MOS transistor, a bunch through current easily flows, and the drain current does not completely deplete.
exhibiting unusual characteristics.

For example, in a MOS dynamic RAM, this causes a problem in that one charge stored as information leaks.

Usually, to prevent this punch-through phenomenon, the source,
A highly doped ion-implanted layer of a conductivity type opposite to that of the drain is formed deep inside the channel region. However, such an ion implantation layer is formed over the entire surface of the substrate.

Applying a substrate bias causes a depletion layer to extend from the substrate surface to the implanted layer below the channel region, resulting in a dependence of the threshold voltage on the substrate bias. Therefore, since the ion implantation layer has a high concentration, its presence has a large influence on the substrate bias.

In order to prevent this, a MOS type semiconductor device having a structure called a P-pocket has been proposed in which an ion implantation layer for punch-through prevention is not formed in the region below the channel.

That is, as shown in FIG. 4(a), first a P-type substrate (
After forming an oxide film I to serve as a gate on IG and further forming an electrode station made of polycrystalline silicon on it, the oxide film 4'D and the gate electrode (6) are patterned. Next, using the patterned electrode ρ as a mask, P-type impurity +i! is added to prevent punch-through. ! (P-blur)/
1) Form an IJ in the deep part of the substrate &l□ by implanting ions →, and then implant n-type impurity ions 47) into the source and drain regions 4L1G using the gate electrode → as a mask, as shown in FIG. 4(b). and is formed near the surface of the substrate 40. Thereafter, as shown in FIG. 4C, the entire surface is covered with an insulating film tet by CVD, and then a contact hole/field is formed and an electrode ω is buried therein. Here, although not shown, an electrode is similarly formed on the gate →. In the MOS type semiconductor device formed in this way, since the P-type impurity layer 4 for preventing punch-through is not present in the channel region 61), the dependence of the threshold voltage on the substrate bias can be weakened.

However, in the above-mentioned P pocket structure MOS type semiconductor device, the P type impurity layer 4 is in contact with the source and drain regions (formerly, (a)) over a wide range below the source and drain regions. Another problem is that the capacitance between the source, drain, and substrate cannot be reduced due to the junction capacitance, and the circuit operation cannot be increased in speed.

(Problems to be Solved by the Invention) The present invention solves the problem of the MOS type semiconductor device having the above structure, which is that the Pn junction capacitance between the north, -drain and the substrate is not reduced, making it impossible to achieve high-speed devices. solve,
It is an object of the present invention to provide a method for manufacturing a MOSF'ET capable of high-speed operation by effectively suppressing the punch-through phenomenon between the source and drain, and reducing the Pn junction capacitance between the source and drain and the substrate.

[Structure of the invention]

(Means for Solving the Problems) In order to achieve the above object, in the present invention, an impurity layer for preventing bunch-through is formed in a limited region in contact with the source, drain, and channel regions in a self-aligned manner with respect to the gate. The junction capacitance is reduced by forming only
It is designed to enable high-speed operation.

(Function) The Pn junction capacitance can be reduced by reducing the length of the high concentration junction.

In the present invention, the capacitance is reduced and the operation speed is increased by forming a highly concentrated punch-through prevention layer in a small region in self-alignment with the gate.

(Example) Hereinafter, details of the present invention will be explained using the drawings.

First Embodiment FIG. 1 is a sectional view showing the manufacturing process of a first embodiment of the present invention.

First, as shown in FIG. 1(a), a P-type semiconductor substrate (1
) on the gate oxide film (41
is deposited to a thickness of, for example, 0.5 μm.

Next, when chemical etching is performed using, for example, ammonium fluoride, the oxide film is etched into corner regions (5) in contact with the gate electrode (3) and the substrate (1), as shown in FIG. 1(b). Since the bond is loose in this case, in order to form an ion-implanted layer to prevent punch-through, for example, boron β) ions (6) are accelerated at 120 K.
eV, dose 2X10”151”T:! Substrate (1
). As a result, as shown in FIG. 1(C), P-type impurity 4 (P pocket layer )(7) can be formed.

After that, as shown in FIG. 1(d), the oxide film (4a
) is removed by etching to form source and drain regions +81
．． +91 is formed by ion implantation of arsenic (As) or phosphorus (P).

Thereafter, as shown in FIG. 1(e), an oxide film u1 is formed on the entire surface by CVD or the like according to a normal process, and then the source, drain +81. Contact holes α1) and Q3 connected to +91 are formed, and an electrode material such as tungsten is buried to form an electrode α3°rs to form a MOSFET.

The MOSFET manufactured in this way is
In addition to reducing the dependence of the threshold voltage on the substrate bias, which is an advantage of MOS FET, the impurity layer (7)
In other words, the P pocket layer is self-aligned with the gate,
And source, drain +81. Since the P pocket layer can be formed only in the +91 region where the electric field is high, the junction capacitance between the substrate and the source and drain can be reduced, making it possible to reduce the MOSFET
The speed can be increased.

Here, the position of the P pocket layer +71 does not need to be in contact with the source or drain as long as it is not directly under the gate within the intrinsic transistor region αυ.

Embodiment @2 Figure 2 shows the P of the LDD structure showing the second embodiment of the present invention.
FIG. 3 is a cross-sectional view showing the manufacturing process of a pocket MOSFET.

The same parts as in FIG. 1 are indicated with the symbol 閤-.

First, as shown in FIG. 2(a), a P-type semiconductor substrate 11)
A gate oxide film (2) and a gate electrode (3) are formed thereon according to a normal process. Next, after forming low concentration n- impurity regions ■ and @ by ion implantation, l
An oxide film @ containing phosphorus (Q)/m' or more is deposited to a thickness of 0.5 μm over the entire surface by plasma CVD.

Next, when the oxide film @ is etched with ammonium fluoride, the gate electrode +3) and the substrate (
Since the bonding is loose in the corner region (5) that is in contact with the corner region (5), etching progresses more than in other regions, and the thin oxide film (22a) in the corner region (5) becomes ) Accelerate ion (6) with energy 120KeV1
Ion implantation is performed at a dose of 2×10 7 cm. The P-type impurity layer (7) formed by this ion implantation is self-aligned with the gate (3) and has a high concentration of n, which will be described later.
+It can be effectively formed in the end regions of the source and drain regions.

After that, heat treatment lt+/ for 30 minutes in a thermal atmosphere of 950°C
S (22b). Next, this electrified membrane (22b
) is etched by RIE or the like, as shown in FIG. 2(e), the gate electrode (3) above the P-type impurity layer (7) is removed.
An oxide film (22C) is left on the side wall.

After that, as shown in FIG. 2(f), the gate electrode (3)
Using the oxide film (22C) on the side wall of this gate electrode (3) as a mask, a high concentration of arsenic (As) or phosphorus (p) is applied.
Perform ion (III) implantation to form n+ source and drain regions.

form).

Hereinafter, similarly to the first embodiment, after coating the entire surface with oxide M IIG'' using a DVD or the like, the contact hole Q1
1. Q3 has an electrode (13, α4 embedded, MOSFhi
Form a T. Here, the formation of the oxide film uG is
It is of course possible to perform this after completely removing the oxide film (22C) on one wall.

With the MOS type semiconductor device formed according to this embodiment, in addition to the effects obtained in the first embodiment, relaxation of the special electric field of the LDD structure can also be achieved.

In addition, in this embodiment, the oxide film (22a) was transformed into an oxide film by heat treatment in the dJ process shown in FIG. 6), for example, phosphorus is injected onto the oxide film (22a) at I x 10
After covering the entire surface with an oxide film containing ``/15'' by CVD method or the like.

An oxide film is left on the side walls of the gate (3) by reactive ion etching. Thereafter, highly doped source and drain regions are formed in exactly the same manner as in the second embodiment, and CV
After forming the D oxide film, the electrodes are formed.

Third Example Next, a third example, which is a modification of the second example, will be described.
This will be explained using figures. Components that are the same as those in FIG. 2 are designated by the same reference numerals, and detailed description thereof will be omitted.

First, a gate (3) made of polycrystalline silicon is formed as shown in FIG. A thin oxide film in the region +51 (
22a). After that, high concentration P-type ions (6) such as poron (B) are accelerated with an energy of 120Ke.
V, ion implantation at a dose of 2x10/1S,
Similar to the 4@2 embodiment, a P-type impurity layer (7) is formed inside the substrate (1) in a self-aligned manner with respect to the gate.

In this embodiment, as shown in FIG. 3(b), after removing the oxide film (22a), the polycrystalline silicon gate (3) is oxidized by heat treatment, so that at least the side walls of the gate (3) are oxidized. Form a film. Next, using this oxide film as a mask, arsenic (As) or phosphorus (P) is applied.
) ions e3 are implanted to form high concentration n source and drain regions (to) and (to).

Thereafter, MOSFgT is manufactured using the same steps as in the second embodiment. Here, the oxide film (2) formed on the gate (3) may be removed, or an insulating film may be covered from above until then.

By forming a MOS type semiconductor device as described above, a P-type impurity layer for preventing punch-through can be formed in a small region inside the substrate in self-alignment with respect to the gate without misalignment. Further, in the MOS type semiconductor device formed in this manner, the junction capacitance between the source, drain and substrate can be reduced, and the speed can be increased.

The present invention is not limited to the above-mentioned embodiments to the third embodiment, and may be modified as appropriate without departing from the gist of the invention.

For example, as the etchant for the oxide film that is entirely covered after the gate is formed, any etchant that etches through a chemical reaction, such as hydrofluoric acid, may be used as long as it etches the portions where the bonds are loose.

If the substrate is an n-star substrate, a P-type punch-through prevention layer of the same conductivity type as the substrate may be formed.

〔Effect of the invention〕

As described above, according to the present invention, the P pocket layer for preventing punch-through is formed in a self-aligned manner with respect to the gate.
It can be formed in a desired small area, reduces the junction capacitance between the source/drain and the substrate, and increases the speed of the device.

[Brief explanation of the drawing]

Figure ag1 is a process sectional view showing the first embodiment of the present invention,
FIG. 2 is a process sectional view showing a second embodiment of the present invention, FIG. 3 is a process sectional view showing a third embodiment of the invention, and FIG.
The figure is a process sectional view for explaining a conventional example. l...Substrate 2...Gate insulating film 3...Gate electrode 4.4a...
- Oxide film 7...P pocket layer 8.9. ...
...source, drain 22a, 22b, 22C・
....Oxide films 24, 25 with impurity addition...
Source, Drain Representative Patent Attorney Yudo Nori Chika Kikuo Takehana Figure 1 ￥ 2 - Figure 2 72θ 2f7 Figure 2 Figure 3

Claims (15)

[Claims] (1) A step of forming a gate portion on a semiconductor substrate, a step of coating the gate portion and the entire surface of the substrate with an oxide film, and a step in which the thickness of the oxide film covering the gate sidewall portion is greater than that of other oxide films. a step of etching the film to be thinner than the thickness of the oxide film, and implanting ions of high concentration impurities of the same conductivity type as the substrate into the deep part of the substrate from the thinly formed oxide film part;
A MOS comprising a step of forming a punch-through prevention layer, and a step of removing at least an oxide film formed on the substrate on both sides of the gate, and then forming a source and a drain on the substrate surface on both sides using the gate part as a mask. A method for manufacturing a type semiconductor device. (2) The MO according to claim 1, wherein the gate portion is formed from a gate oxide film formed on a semiconductor substrate and a gate electrode formed on this oxide film.
A method for manufacturing an S-type semiconductor device. (3) The method for manufacturing a MOS type semiconductor device according to claim 1, wherein the oxide film covering the gate sidewall portion is an oxide film at a corner portion formed by the gate sidewall and the substrate. (4) The method for manufacturing a MOS type semiconductor device according to claim 1, wherein the punch-through prevention layer is formed so as to be in contact with the end portions of the source and drain under the gate. (5) The method for manufacturing a MOS type semiconductor device according to claim 1, wherein the etching of the oxide film is performed using ammonium fluoride. (6) A claim that includes a step of forming a low concentration impurity layer of a conductivity type opposite to that of the substrate on the substrate surface using the gate portion as a mask between the step of forming the gate portion and the step of covering the oxide film. 2. A method for manufacturing a MOS semiconductor device according to item 1. (7) The method of manufacturing a MOS type semiconductor device according to claim 6, wherein the source and drain are formed by ion implantation deeper than the low concentration impurity layer. (8) The method according to claims 1 and 2, further comprising a step of etching away the oxide film after forming the punch-through layer and before forming the source and drain, and covering the gate electrode with the oxide film. A method for manufacturing a semiconductor device. (9) A step of forming a gate portion on a semiconductor substrate, a step of coating the gate portion and the entire surface of the substrate with an oxide film containing impurities, and a step of forming the oxide film covering the gate sidewall portion in a different thickness. A process of etching the oxide film so that it is thinner than the thickness of the oxide film, and implanting ions of highly concentrated impurities of the same conductivity type as the substrate deep into the substrate from the thinly formed oxide film to form a punch-through prevention layer. a step of forming the oxide film, a step of thickening at least the thinly formed portion of the oxide film, and then etching it to leave the oxide film on the gate sidewall; and a step of ion implantation using the oxide film of the gate portion and the gate sidewall as a mask. A method for manufacturing a MOS type semiconductor device, comprising a step of forming a source and a drain. (10) The MOS according to claim 9, wherein after forming the gate portion and before coating the oxide film, a low concentration impurity layer of a conductivity type opposite to that of the substrate is formed on the substrate surface using the gate portion as a mask. A method for manufacturing a type semiconductor device. (11) The method of manufacturing a MOS type semiconductor device according to claim 10, wherein the source and drain are formed by ion implantation deeper than the low concentration impurity layer. (12) The method for manufacturing a MOS type semiconductor device according to claim 9, wherein the first etching is performed using ammonium fluoride. (13) The impurity-containing oxide film has a size of 1×10^2
The method of manufacturing a MOS type semiconductor device according to claim 9, which contains phosphorus of ^0 cm^-^3 or more. (14) The MOS according to claim 9, wherein the oxide film is thickened by heat-treating the oxide film.
A method for manufacturing a type semiconductor device. (15) The method of manufacturing a MOS type semiconductor device according to claim 9, wherein the oxide film is thickened by coating a new oxide film on the oxide film.