JPS63148494A - Pseudo static memory - Google Patents

Abstract

PURPOSE:To easily vary a refresh period by using an external address input signal which comes to an idle state during an antomatic refresh period, and selecting the combination of a capacity for adjusting a timer period. CONSTITUTION:Capacities CST1 and CST2 are connected in parallel with a capacity CST for adjusting the period of a timer circuit through transfer gate transistors Q1 and Q2. Buffer outputs 3 and 4 of the external address input terminal 1 and 2 are inputted to the gates of the transistors Q1 and Q2. If the level of the external address input terminal 1 becomes high, the transistor Q1 is turned ON, the capacity CST1 is connected with the capacity CST in parallel, and the refresh period is prolonged. The refresh period similarly changes even if the level of the external address input terminal 2 becomes high. With the combination of the high level and the low level of two external address input, four types of the combination of the capacities for adjustment is attained, whereby four types of refresh periods can be obtained. With selecting the optimum combination, the period of the timer circuit can be set.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a pseudo-static memory, and more particularly to a pseudo-static memory in which the refresh period of an automatic refresh island can be externally changed.

[Conventional technology]

Pseudo-static memory that uses dynamic memory cells and has a built-in refresh function has expanded its market in recent years due to its large capacity and ease of use, but one of its major features is its low current consumption during automatic refresh. It is one. The current consumption during automatic refrigeration depends on the period of the timer circuit constituting the S7 resetting start signal generation circuit, and the longer the period, the smaller the current consumption. On the other hand, it is necessary to complete the refresh island within the hold time of the memory cell 69, and this determines the upper limit of the period of the timer circuit. That’s it!]
As is obvious, the period of the timer circuit needs to be set with high precision, and conventionally this has been done, for example, by the method shown below. Namely, automatic refresh island activation in the conventional pseudo-static memory shown in the second factor. In the signal generation circuit, the MO which can be controlled by the end signal 5
8 transistor Q21. MOS transistor Q22 with its gate grounded, M (JS) transistor Q23 with a grounded diode, oscillator output 6' and MOS) transistor Q
23 Capacitor CT1 for coupling and Capacitor C8 for timer cycle adjustment? It consists of a timer circuit consisting of a timer circuit, and an inverter that inverts and amplifies the output of the timer circuit, and outputs the output of the inverter as an automatic refresh activation signal.

In the above configuration, the capacity C at the end of automatic refresher
The period T of the timer circuit when the precharge potential of the power supply is set to the level T of the power supply ■cc. It is well known that , is expressed by the following equation.

VT: MOS) transistor threshold voltage Therefore, it is possible to design the optimum period of the timer circuit based on Equation 11.

[Problem that the invention seeks to solve]

However, in reality, it is difficult to obtain one cycle of glue threshing as designed due to variations in manufacturing.Therefore, we focused on the capacitance C1, and carried out actual manufacturing until the desired glue fresh island cycle was obtained. Cs? The method used was to repeatedly recreate the mask, or to prepare several types of masks for diffusion manufacturing with different values of capacitance CST from the beginning.

Alternatively, in recent years, CSTs of several sizes are connected in parallel with
There was a drawback that the optimum C8T was determined while measuring Y-.

Therefore, an object of the present invention is to provide a pseudo-static memory that can trim the period of a timer circuit by capacitance, which can be done economically and in a short construction period.

[Means for solving problems]

The pseudo-static memory of the present invention is controlled in accordance with a combination of an automatic refresh start signal generation circuit including a plurality of capacitors for adjusting the timer cycle, which are charged by a refresh island end signal and discharged by an output signal of an oscillator, and an address input. A switch circuit is provided to select part or all of the adjustment capacitance.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram showing one embodiment of the present invention.

Capacity jL-c for period adjustment of the timer circuit compared to the conventional example,
? Transfer gate transistor Qo in parallel with.

It is long since the capacitor CC via Q3 is connected.
The gates of the WkT2 transistors Qx and Qs are configured such that the outputs 3 and 4 of the external address input terminal 1.2 are input. In this configuration, it is clear that the refresh island period can be changed by varying the capacitances of Cs and r by using the external address input terminals which are normally in an idle state during automatic refresh. That is, when external address input terminal 1 becomes high level, transistor Q1 turns on.
The capacitor C3T□ is connected in parallel with the capacitor C3a. Therefore, as is clear from equation (1), the refresh island period becomes longer. The refresh island period changes similarly when the external address input terminal 2 reaches the /1 level. As described above, by combining the high level and low level of the two external address inputs, four combinations of i11 adjustment capacitances are possible, and four reflex Z& cycles are obtained. The cycle of the timer circuit can be set by selecting the optimal combination among these.

The number of refresh island cycles that can be realized by using more external address terminals is the set of 2 to the 1 power of the number of external address terminals n (26), and it is clear that even narrower settings are possible. . Therefore, the capacitance CsT that determines one cycle of the desired threshold can be set economically in a short manufacturing period by combining external addresses.

〔Effect of the invention〕

As explained above, the present invention uses an external address input signal that is in an idle state during the automatic refresh period and selects a combination of capacitors for adjusting the timer cycle.
This has the effect of easily varying the refresh island cycle.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing one embodiment of the present invention, and FIG. 2 is a circuit diagram of a conventional example. 1.2... External address long sword terminal, 3.4...
... Address buffer output signal, 5. Mountain... Refresh end signal, 6... Oscillator output signal. Figure 1

Claims (1)

[Claims] an automatic refresh start signal generation circuit including a plurality of capacitors for timer period adjustment that are charged by a refresh end signal and discharged by an output signal of an oscillator; and a part or all of the adjustment capacitors are selected by being controlled according to a combination of an address input. Pseudo-static memory with a switching circuit.