JP2580222B2 - Semiconductor integrated circuit device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, for example, a pseudo-static type random access memory (PSRAM) having a built-in refresh timer circuit.
emory), etc., which are particularly effective technologies.

[Conventional technology]

A pseudo-static RAM having a memory array of dynamic memory cells and having input / output conditions compatible with a normal static RAM is disclosed in, for example, 1987.
March 1989, "Hitachi IC Memory Data Book" published by Hitachi, Ltd., pp. 229-234.

[Problems to be solved by the invention]

In the pseudo static RAM as described above, the dynamic memory cells constituting the memory array have a predetermined information holding time, and require a refresh operation of the stored data within the information holding time. Therefore, the pseudo-static RAM is provided with a self-refresh mode in which a refresh operation is autonomously executed at a cycle for compensating the minimum value of the information holding time of the memory cell, and a refresh control circuit for the self-refresh mode is provided. The refresh control circuit includes a refresh timer circuit that forms a start signal for the predetermined periodic refresh operation.

FIG. 5 shows a refresh timer circuit of a refresh control circuit developed by the present inventors prior to the present invention.
A circuit diagram of the RTM is shown. In the figure, a refresh timer circuit RTM comprises a P-channel MOSFET Q15 and an N-channel MOSFET Q15.
The basic configuration is a ring oscillator including an inverter circuit N6 including a channel MOSFET Q35 and inverter circuits N7 and N8. An N-channel MOSFET Q34 is provided between the MOSFET Q35 forming the inverter circuit N6 and the ground potential of the circuit. The MOSFET Q34 functions as a constant current source circuit when a predetermined voltage formed by a voltage dividing circuit including P-channel MOSFETs Q12 to Q14 and N-channel MOSFETs Q32 to Q33 is supplied to the gate. When the output signal of inverter circuit N8 is at a low level, capacitor C3 is charged via P-channel MOSFET Q15. When the output signal of the inverter circuit N8 is at a high level, the charge of the capacitor C3 is
Is gradually discharged via. Thus, the cycle of the activation timing signal φtm output from the refresh timer circuit RTM, that is, the cycle of the refresh operation in the self-refresh mode is determined substantially according to the discharge current via the MOSFET Q34, in other words, the gate voltage of the MOSFET Q34.

By the way, as is well known, the information retention time of the dynamic memory cells forming the memory array changes according to the power supply voltage of the circuit and the ambient temperature. Similarly, the cycle of the start timing signal φtm output from the refresh timer circuit RTM is the same as that of the MOSFET constituting the timer circuit.
In accordance with the process variation, the power supply voltage of the circuit, the ambient temperature, and the like. Therefore, the refresh timer circuit
Each circuit element constituting the RTM receives the timing signal φtm
The constants are designed so that the period of the information memory cell of the dynamic memory cell and the period of the timing signal φtm vary in the most unfavorable direction so that malfunction does not occur. Is done. This results in that the refresh operation of the pseudo-static RAM is performed at an unnecessarily short cycle at a normal power supply voltage and an ambient temperature, and the pseudo-static RAM is refreshed.
Causes an increase in power consumption during standby.

SUMMARY OF THE INVENTION An object of the present invention is to provide a timer circuit that suppresses periodic fluctuations due to a power supply voltage of a circuit, a process variation of a circuit element, an ambient temperature, and the like. Another object of the present invention is to reduce the power consumption of a pseudo static RAM or the like including a timer circuit.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for solving the problem]

The outline of a typical invention disclosed in the present application will be briefly described as follows. That is,
A charge current or a discharge current of a capacitor that determines the oscillation cycle of the timer circuit is formed by applying a predetermined voltage to both ends of the resistance means, and the current is transmitted through a current mirror circuit to charge the capacitor. Alternatively, discharge is performed, and the level amplitude of the capacitor is designed to have a substantially fixed ratio relation to the voltage applied to both ends of the resistance means.

(Operation)

According to the above-described means, the time required for charging or discharging the capacitor, that is, the oscillation cycle of the timer circuit, is substantially a function of the resistance value of the resistance means and the capacitance value of the capacitor, and the power supply voltage and the ambient temperature of the circuit And the influence of process variations of circuit elements can be suppressed. As a result, pseudo-static RA
The refresh cycle such as M can be shortened, and the power consumption can be reduced.

〔Example〕

FIG. 4 shows a circuit block diagram of an embodiment of a pseudo static RAM (PSRAM) to which the present invention is applied. The circuit elements that make up each block in FIG.
It is formed on one semiconductor substrate such as single crystal silicon by CMOS (complementary MOS) manufacturing technology. In the following figures, MOSFETs with an arrow added to the channel (back gate) portion are of the P-channel type, and are distinguished from N-channel MOSFETs without the arrow.

In the pseudo-static RAM of this embodiment, the memory array is composed of so-called one-element type dynamic memory cells, so that high integration and low power consumption of the circuit are achieved. Further, X address signals AX0 to AXi and Y
Address signals AY0 to AYj are input via separate external terminals, respectively, and a chip enable signal
By providing ▼, write enable signal ▲ ▼, and output enable signal ▲ ▼, input / output interface conditions compatible with ordinary static RAMs are provided. The pseudo-static RAM further includes a refresh control circuit RFC, and has a function of autonomously executing a refresh operation unique to a dynamic memory cell. As a result, the pseudo-static RAM of this embodiment can be used in place of the relatively expensive bipolar RAM or CMOS static RAM as long as the access time does not matter.

In the pseudo-static RAM of this embodiment, the refresh control circuit RFC includes a refresh address counter RCTR and a refresh timer circuit as described later.
Including RTM. The refresh control circuit RFC has an external terminal ▲
Refresh control signal ▲ ▼ via ▼
Is supplied. This refresh control signal ▲ ▼
Is repeatedly changed from a high level to a low level in a predetermined cycle, the pseudo-static RAM is set to an auto-refresh cycle. In this auto-refresh cycle, the refresh control circuit RFC advances the refresh address counter RCTR one by one according to the refresh control signal ▲, and executes a refresh operation for each word line. On the other hand, when the refresh control signal ▼ is continuously at the low level for a predetermined period or longer, the pseudo static RAM is in a self-refresh cycle. In this self-refresh cycle, the refresh control circuit RFC periodically executes a series of refresh operations on all the word lines according to a start timing signal supplied from the refresh timer circuit RTM.

In FIG. 4, although not particularly limited, the memory array M-ARY is a two-intersection (returned bit line) system,
The (n + 1) sets of complementary data lines D0 arranged in the horizontal direction in FIG.
・ ▲ ▼ ~ Dn ・ ▲ ▼ and m arranged vertically
(N + 1) × (m +) arranged in a grid at the intersections of +1 word lines W0 to Wm and their complementary data lines and work lines
1) memory cells.

Each memory cell of the memory array M-ARY has a so-called 1
It is an element type dynamic memory cell, and is composed of an information storage capacitor Cs and an address selection MOSFET Qm. Address selection MOSFETs of m + 1 memory cells arranged in the same column of memory array M-ARY
The drain of Qm is connected to the corresponding complementary data line D0
It is alternately coupled to the non-inverting signal line or the inverting signal line of Dn • ▲ with a predetermined regularity. Further, the memory array M
The gate of the address selection MOSFET Qm of the (n + 1) memory cells arranged in the same row of -ARY is connected to the corresponding word line
Commonly coupled to W0 to Wm, respectively. A predetermined cell plate voltage is commonly supplied to the other electrode of the information storage capacitor Cs of each memory cell, that is, the cell plate.

Word lines W0 to Wm constituting the memory array M-ARY are:
It is coupled to the row address decoder RDCR, and is alternatively selected.

The row address decoder RDCR receives, from a row address buffer RADB to be described later, i + 1-bit complementary internal address signals a x0 to a xi (here, for example, a non-inverted internal address signal).
ax0 and the inverted internal address signal ▼ are combined and represented as a complementary internal address signal ax0. The same applies hereinafter), and the timing signal φ is supplied from the timing generation circuit TG.
x is supplied. The timing signal φx is normally set to a low level, and is set to a high level at a predetermined timing when the pseudo static RAM is selected in a normal operation mode or a refresh mode.

The row address decoder RDCR outputs the timing signal φ
When x is set to a high level, it is selectively activated. In this operation state, the row address decoder RD
CR decodes the complementary internal address signals a x0~ a xi, the corresponding one word line to a selected state of alternatively high level.

The row address buffer RADB receives and holds a row address signal transmitted from the address multiplexer AMX. The complementary internal address signals a x0 to a xi are formed based on these row address signals.

To one input terminal of the address multiplexer AMX,
I + 1-bit X input through external terminals AX0 to AXi
Address signals AX0 to AXi are supplied. The other input terminal of the address multiplexer AMX is not particularly limited, but a refresh control circuit RFC (described later) outputs i + 1
Bit refresh address signals rx0 to rxi are supplied. The address multiplexer AMX is further supplied with a timing signal φref from the timing generation circuit TG. The timing signal φref is at a low level when the pseudo-static RAM is in a normal write or read operation mode, and is at a high level when the auto-refresh or self-refresh mode is set.

The address multiplexer AMX selects the X address signals AX0 to AXi supplied via the external terminals A0 to Ai in a normal memory access in which the timing signal φref is at a low level, and selects the row address buffer RADB as a row address signal. To communicate. In each refresh mode in which the timing signal φref is at a high level, the refresh address circuits rx0 to rxi supplied from the refresh control circuit RFC are selected and transmitted to the row address buffer RADB as row address signals.

On the other hand, the complementary data lines D constituting the memory array M-ARY
On the other hand, 0 • ▲ ▼ to Dn • ▲ ▼ are coupled to the corresponding unit amplifier circuit USA of the sense amplifier SA.

The sense amplifier SA includes n + 1 unit amplifier circuits USA. Each unit amplifier circuit of sense amplifier SA USA
Is a P-channel MO, as exemplarily shown in FIG.
CM consisting of SFET Q10, Q11 and N-channel MOSFET Q30, Q31
An OS latch circuit has a basic configuration. The input / output nodes of these latch circuits are connected to the corresponding complementary data lines D0.
It is coupled to the non-inverting signal line and the inverting signal line of Dn. The unit circuit of the sense amplifier SA is not particularly limited, but may be a P-channel type drive MOSFET.
The power supply voltage Vcc of the circuit is supplied via Q9, and the ground potential of the circuit is supplied via an N-channel drive MOSFET Q29.

The gate of the drive MOSFET Q29 has a timing generator TG
Supplies a timing signal φpa. Also, drive MO
The gate of the SFET Q9 is supplied with an inverted signal of the timing signal φpa by the inverter circuit N5. The timing signal φpa is normally set to the low level, and when the pseudo static RAM is set to the selected state and the minute read signal output from the memory cell coupled to the selected word line is established to the corresponding complementary data line. , High level. When the timing signal φpa is set to the high level, the drive MOSFETs Q9 and Q29 are both turned on, and the (n + 1) unit amplifier circuits USA of the sense amplifier SA are simultaneously operated.

In the operation state, each unit amplifier circuit USA of the sense amplifier SA operates from the (n + 1) memory cells coupled to the selected word line to the corresponding complementary data line D0.
The small readout signal output via Dn • ▲ ▼ is amplified respectively to be a high level or low level binary readout signal. These binary read signals are rewritten to the corresponding memory cells when the pseudo-static RAM is set to the read mode or each refresh cycle, and the stored data is refreshed. In other words, the refresh operation of the dynamic memory cell can be realized by alternately setting the word lines W0 to Wm to the high-level selected state and simultaneously operating the unit amplifier circuits USA of the sense amplifier SA. it can.

Complementary data lines D0 and ▲ constituting the memory array M-ARY
▼ to Dn • ▲ ▼ are coupled on the other side to the corresponding switch MOSFETs of the column switch CSW. The column switch CSW is connected to the complementary data lines D0
N + 1 pairs of switch MOSFs provided corresponding to ▲ ▼
It is composed of ETQ36 and Q37 to Q38 to Q39. One of these switch MOSFETs is coupled to a corresponding complementary data line, and the other is a non-inverted signal line CD of a complementary common data line.
And the inverted signal line ▲ ▼. The gates of each pair of switch MOSFETs are connected in common,
The corresponding data line selection signals Y0 to Yn are supplied from the column address decoder CDCR. As a result, each pair of switch MOSFETs constituting the column switch CSW is turned on when the corresponding data line selection signal Y0 to Yn is alternatively set to a high level, and a set of designated complementary data Line and the common complementary data line CD • ▲ ▼ are selectively connected.

The column address decoder CDCR is supplied with complementary internal address signals a y0 to a yj of j + 1 bits from a column address buffer CADB described later.
The timing signal φy is supplied from the TG. The timing signal φy is normally at a low level,
When the RAM is set to the selected state and the amplification operation by the sense amplifier SA ends, the level is set to the high level.

The column address decoder CDCR is selectively turned on when the timing signal φy is set to a high level. In this operating state, the column address decoder CDCR decodes the complementary internal address signals a y0 to a yj and selectively sets the corresponding data line selection signals Y 0 to Yn to a high level.

The column address buffer CADB is provided with j + 1-bit Y address signals AY0 to AY0 supplied via external terminals AY0 to AYj.
Capture and hold Yj. Further, based on these Y address signals AY0 to AYj, the complementary internal address signals a y0 to a y
form yj.

The complementary common data line CD
Input terminals are connected and the data input buffer
DIB output terminals are coupled. The output terminal of the main amplifier MA is further coupled to the input terminal of the data output buffer DOB, and the output terminal of the data output buffer DOB is coupled to the data input terminal DIO. The input terminals of the data input buffer DIB are commonly coupled to the data input / output terminal DIO.

Main amplifier MA is selectively activated according to timing signal φma supplied from timing generation circuit TG. In this operation state, the main amplifier MA further amplifies the binary read signal output from the selected memory cell of the memory array M-ARY via the corresponding complementary data line and complementary common data line CD • ▲ ▼. , To the data output buffer DOB.

When the dynamic RAM is set to the read operation mode, the data output buffer DOB is selectively activated according to the timing signal φr supplied from the timing generation circuit TG. In this operation state, the data output buffer DOB sends a read signal of the memory cell transmitted from the main amplifier MA to an external device via the data input / output terminal DIO.

When the dynamic RAM is set to the write operation mode, the data input buffer DIB is selectively activated according to the timing signal φw supplied from the timing generation circuit TG. In this operation state, the data input buffer DIB uses the write data supplied via the data input / output terminal DIO as a complementary write signal and supplies it to the complementary common data line CD.

The refresh control circuit RFC includes a refresh timer circuit RTM, a refresh address counter RCTR, and a refresh timing generation circuit RTG, as described later. The refresh control circuit RFC, as described later,
An auto-refresh cycle or a self-refresh cycle is selectively executed according to a refresh control signal supplied through an external terminal.

In each refresh cycle, the refresh control circuit RFC supplies the timing signal φrs for starting the refresh operation to the timing generation circuit TG. The timing generation circuit TG forms various timing signals necessary for the refresh operation in accordance with the timing signal φrs, and is supplied to each circuit. Each time a refresh operation for one word line is completed, a timing signal φre is supplied to the refresh control circuit RFC. The timing signal φre is a count pulse for incrementing the refresh address counter RCTR.

The specific configuration and operation of the refresh control circuit RFC will be described later in detail.

The timing generation circuit TG outputs the chip enable signal ▲
Based on ▼, write enable signal ▲, and output enable signal ▲ ▼, the above various timing signals are formed and supplied to each circuit. Further, according to the timing signal φrs supplied from the refresh control circuit RFC, various timing signals necessary for the refresh operation are formed and supplied to each circuit. Further, when the refresh operation for one word line is completed, the timing generation circuit TG forms a timing signal φre and supplies it to the refresh control circuit RFC.

FIG. 1 is a circuit block diagram of an embodiment of the refresh control circuit RFC of the pseudo-static RAM shown in FIG.

In FIG. 1, a refresh control circuit RFC is not particularly limited, but a refresh timer circuit RTM to which the present invention is applied and a refresh address counter RCTR.
And a refresh timing generation circuit RTG.

Refresh timer circuit RTM includes a capacitor C1 having a predetermined capacitance. Although not particularly limited, the capacitor C1 is configured by the gate capacitance of an N-channel MOSFET. One electrode of the capacitor C1 is coupled to the circuit ground potential (second power supply voltage), and the other electrode is connected to the P-channel MOSFET Q4 (the seventh MO
SFET), and further coupled to the gate of N-channel MOSFET Q22 (fifth MOSFET). A P-channel MOSFET Q3 (sixth MO) is connected between the source of MOSFET Q4 and the power supply voltage Vcc (first power supply voltage) of the circuit.
SFET) is provided. MOSFETs Q3 and Q4 are connected to capacitor C1
A reset circuit for. Between the commonly coupled gate and drain of MOSFET Q4 and the ground potential of the circuit,
An N-channel MOSFET Q23 (third MOSFET) is provided. The gate of MOSFET Q23 is coupled to the gate and drain of N-channel MOSFET Q21 (second MOSFET).

The source of MOSFET Q21 is coupled to the ground potential of the circuit. A resistor R1 (resistance means) and a P-channel MOSFET Q1 (first MOSFET) are provided in series between the commonly coupled gate and drain of the MOSFET Q21 and the power supply voltage Vcc of the circuit. The gate of MOSFET Q1 is coupled to its drain and is further commonly coupled to the gate of P-channel MOSFET Q2 (fourth MOSFET). The source of MOSFET Q2 is coupled to the power supply voltage V _CC of the circuit, and its drain is coupled to the drain of MOSFET Q22 as node n2.

The commonly coupled drain of MOSFETs Q2 and Q22, or node n2, is connected via delay circuit DL1 to inverter circuit N1.
To the input terminal. The output terminal of the inverter circuit N1 is coupled as a node n3 to the input terminal of the inverter circuit N2 and to the gate of the MOSFET Q3. The output signal of the inverter circuit N2 is a timing signal φ
tm, a refresh timing generator described later
Supplied to RTG. MOSFETs Q2 and Q22 form a level determination circuit for node n1.

In this embodiment, the MOSFETs Q1 and Q2 and the MOSFET
Q21 and Q23 are the ratio W / L of the gate width W to the gate length L.
Are designed to be the same, and have substantially similar electrical characteristics. The delay circuit DL1 has an action of delaying and transmitting only the falling change of the node n2, and its delay time Tdl is set to be sufficiently smaller than the oscillation cycle of the refresh timer circuit RTM.

FIG. 2 is a timing chart of one embodiment of the refresh timer circuit RTM of the refresh control circuit RFC shown in FIG. Prior to proceeding with the description of the circuit block diagram of FIG. 1, an outline of the operation of the refresh timer circuit RTM of this embodiment will be described with reference to FIGS.

When the node n3, that is, the output signal of the inverter circuit N1 is set to the high level and the MOSFET Q3 is turned off, the capacitor C1 is gradually discharged via the MOSFET Q23. As mentioned earlier, MOSFET Q23 has its gate
When coupled to the gate and drain of 21, MOSFET Q2
1 and current mirror configuration. Therefore, the discharge current of capacitor C1 flowing through MOSFET Q23 is substantially equal to current I1 flowing through MOSFET Q21.

Here, assuming that the voltage applied to both ends of the resistor R1 is Vr and the resistance value of the current I1 is R1, I1 = Vr / R1 (1). Since both MOSFETs Q1 and Q21 are in diode form, this voltage Vr is equal to the threshold voltage V _THP of the P-channel MOSFET and the threshold voltage V _{THN of the} N-channel MOSFET from the power supply voltage Vcc and the ground potential of the circuit, respectively. The shifted value, that is, Vr = Vcc−V _THP −V _THN (2) By substituting the equation (2) into the equation (1), the discharge current of the capacitor C1, that is, the current I1 is given by I1 = (Vcc− _VTHP − _VTHN ) / R1 (3)

When the capacitor C1 is gradually discharged through the MOSFET Q23 and the level of the node n1 reaches a predetermined voltage,
MOSFET Q22 is turned off. As described above, MOSFET Q2 forming the level determination circuit is designed to have the same electrical characteristics as MOSFET Q1. Also, the gate is
When coupled to the gate and drain of MOSFET Q1, MO
SFET Q1 and current mirror form. Therefore, MOSFET Q2
The current I1 flows through the level determination circuit including the MOSFET Q21 and the MOSFET Q22, and the MOSFET Q22 has the same threshold voltage as the MOSFET Q21. Therefore, the logic threshold of the level determination circuit including the MOSFETs Q2 and Q22 is equal to the threshold voltage V _{THN of the} MOSFET Q21.

When the level of the node n1 becomes lower than the theoretical threshold V _THN and the MOSFET Q22 is turned off, the node n2 is set to a high level like the power supply voltage Vcc of the circuit. As described above, the delay circuit DL1 has an operation of delaying and transmitting only the falling change of the node n. Therefore, the node
By setting n2 to the high level, the output signal of the inverter circuit N1, that is, the node n3 is immediately set to the low level, and
SFETQ3 is turned on. Thereby, the capacitor C1
Is rapidly charged through MOSFETs Q3 and Q4. At this time, since the MOSFET Q4 is in a diode form,
Potential V of capacitor C1 after charging, that is, node n1
_H is as follows: V _H = Vcc−V _THP (4)

When the capacitor C1 is charged and the level of the node n1 exceeds the logic threshold level V _THN , the MOSFET Q2
2 is turned on, and the node n2 goes low. As described above, the low level of the node n2 is delayed by the delay time Tdl by the delay circuit DL1. Therefore,
The node n3 is set to the high level with a delay of the delay time Tdl from the fall of the node n2. This gives M
OSFET Q3 is turned off, and the discharge operation of capacitor C1 is restarted.

By the way, the minimum level of the node n1 is almost equal to the logic threshold of the level judgment circuit including the MOSFETs Q2 and Q22, that is, V _THN . Therefore, the level amplitude Δ of the node n1
Vn1 is a _{ΔVn1 = V H -V THN = Vcc} -V THP -V THN ...... (5). Therefore, the time Tdc from when the MOSFET Q3 is turned off and the discharge of the capacitor C1 is started to when the level of the node n1 reaches the logic threshold of the level determination circuit is Tdc = ΔQ / I1 (6) Here, the movement amount of charge Delta] Q, when the capacitance of the capacitor C1 and C1, is ΔQ = ΔVn1 × C1 = (Vcc -V THP -V THN) · C1 ...... (7). Further, the current I1 is set to I1 = (Vcc− _VTHP − _VTHN ) / R1 from the above equation (3). Therefore, the above equation (6) is as follows: Tdc = C1 · R1 (8) That is, the discharge time Td of the capacitor C1
c is a function of only the resistance value of the resistor R1 and the capacitance of the capacitor C1, and does not include a term relating to the power supply voltage Vcc of the circuit or the threshold voltage of the MOSFET.

The oscillation cycle of the refresh timer circuit RTM of this embodiment, that is, the cycle Tfc of the timing signal φtm is substantially Tfc = Tdc + Tdl. As described above, the delay time Tdl of the delay circuit DL1 is
The value is set to a value sufficiently smaller than the period Tfc. For this reason,
The cycle Tfc becomes Tfc ≒ Tdc, and similarly does not include a term relating to the power supply voltage Vcc of the circuit or the threshold voltage of the MOSFET.

That is, in this embodiment, the discharge current of the capacitor C1 is determined according to the voltage applied across the resistor R1 and its resistance value. The level amplitude of the capacitor C1, that is, the node n1 is designed to have a fixed ratio of one to one with the voltage applied across the resistor R1.
For this reason, the oscillation cycle of the refresh timer circuit RTM, that is, the cycle Tfc of the timing signal φtm has a stable value that is hardly affected by the power supply voltage of the circuit, process variations, and ambient temperature.

In FIG. 1, the timing signal φtm formed by the refresh timer circuit RTM is supplied to a refresh timing generation circuit RTG. The refresh control circuit RFC is further supplied with a refresh control signal ▼ via an external terminal ▼.

The refresh timing generation circuit RTG receives the refresh control signal ▼ and the timing signal φtm.
, A predetermined refresh mode is started. That is, as described above, the refresh control signal ▲
When ▼ is temporarily set to the low level, the timing generation circuit TG determines that the mode is the auto refresh mode, and performs the refresh operation for one word line specified by the refresh address counter RCTR. When the refresh control signal ▼ is continuously at the low level, the timing generation circuit TG determines the self-refresh mode, and performs a series of refresh operations on all the word lines while increasing the refresh address counter RCTR. . At this time, the refresh timing generation circuit RTG is repeatedly started according to the timing signal φtm supplied from the refresh timer circuit RTM, and performs a series of refresh operations for all the word lines while the refresh control signal ▲ ▼ is at the low level. It is repeatedly executed in the above cycle Tfc.

In each refresh cycle, the refresh timing generation circuit RTG first temporarily sets the timing signal φrs for activating the refresh operation to a high level. Thus, the timing generation circuit TG starts the refresh operation, and returns the timing signal φre to the refresh timing generation circuit RTG when the refresh operation for one word line is completed. When the timing signal φre is returned, the refresh timing generation circuit RTG forms the timing signal φrc and supplies it to the refresh address counter RCTR.

The refresh address counter RCTR performs a step operation in accordance with a timing signal φrc supplied from the refresh timing generator RTG. The count value of the refresh address counter RCTR, that is, the refresh address signals rx0 to rxi are supplied to the row address decoder RDCR via the address multiplexer AMX, as described above.
Thereby, a word line to be refreshed is specified.
When the count value of the refresh address counter RCTR reaches the final value, that is, "m", the refresh address counter RCTR supplies a high-level internal control signal ctf to the refresh timing generation circuit RTG.

The internal control signal ctf is set to a high level, and in this state,
When the refresh operation for the last word line Wm is completed and the timing signal φre is returned from the timing generation circuit TG, the refresh timing generation circuit RTG stops the step operation of the refresh address counter RCTR,
Suspend the refresh operation. As a result, the refresh control circuit RFC enters a standby state waiting for the timing signal φtm supplied from the refresh timer circuit RTM.

When the oscillation cycle Tfc of the refresh timer circuit RTM has elapsed since the start of the self-refresh mode, the timing signal φtm temporarily goes high. As a result, the refresh timing generation circuit RTG
First, the refresh address counter RCTR is cleared to an initial state, and its count value is set to “0”. Next, a high-level timing signal φrs is supplied to the timing generation circuit TG to restart the refresh operation for the word line W0.
Thereafter, the refresh operation for the word lines W0 to Wm is repeated as described above. When the refresh operation for all word lines is completed, the refresh control circuit RF
C waits for the timing signal φtm again and enters a standby state.

Hereinafter, the refresh timing generation circuit RTG outputs the timing signal φt from the refresh timer circuit RTM.
The refresh operation is started each time m is supplied, and the operation of entering the standby state is repeated when the refresh operation for all the word lines W0 to Wm is completed.

When the refresh control signal ▲ ▼ is returned to the high level, the refresh timing generation circuit RTG
Stop the refresh operation. Thereby, the pseudo static RAM is prepared for the next selected state.

By the way, when the refresh control signal ▼ is repeatedly changed from the high level to the low level at a predetermined cycle, the pseudo static RAM is set to the auto refresh cycle. At this time, the refresh timing generation circuit RTG spontaneously forms the timing signal φrs and supplies it to the timing generation circuit TG. On the other hand, the timing generation circuit TG performs a refresh operation for one word line, and when the refresh operation ends,
The timing signal φre is returned. As a result, the timing generator for refresh RTG outputs the timing signal φrc
Is supplied to the refresh address counter RCTR, and the refresh address counter RCTR is incremented by one.

In the auto refresh cycle, the refresh control signal ▼ is returned to a high level before the timing signal φre is returned. Therefore, the refresh timing generation circuit RTG interrupts the subsequent operation only by incrementing the refresh address counter RCTR. That is, the refresh operation in the auto-refresh cycle is performed for one word line each time the refresh control signal ▼ changes from the high level to the low level.

As described above, the pseudo-static RAM of this embodiment
Is provided with a refresh control circuit RFC for autonomously executing a memory cell refresh operation. The refresh control circuit RFC is used for the refresh timer circuit RTM.
including. The refresh timer circuit RTM forms the timing signal φtm at a predetermined cycle Tfc when the pseudo static RAM is set to the self refresh mode.
As a result, the refresh control circuit RFC repeatedly executes a series of refresh operations on all the word lines at a cycle that can sufficiently compensate for the information retention time of the memory cells. In this embodiment, the refresh timer circuit RTM includes:
Includes a capacitor C1 that is periodically charged and discharged. Capacitor
The discharge current of C1 is determined according to the voltage applied across the resistor R1 and its resistance value. Also, the capacitor C1
Is made to have a fixed ratio relationship with the voltage applied across the resistor R1. Therefore, the discharge time of the capacitor C1, which determines the oscillation cycle of the refresh timer circuit RTM, is determined by the resistance value of the resistor R1 and the capacitance of the capacitor C1, and the power supply voltage of the circuit and the process variation of the MOSFET and the like. And a stable value that is hardly affected by the ambient temperature and the like. As a result, the oscillation cycle of the refresh timer circuit RTM, that is, the repetition cycle of the refresh operation is set to a relatively large value that sufficiently compensates for the information holding time of the memory cell and suppresses the safety coefficient. As a result, the number of refresh operations per unit time is reduced, and power consumption during standby of the pseudo-static RAM is reduced.

As shown in the above embodiment, the present invention relates to a pseudo-static RAM incorporating a refresh timer circuit.
And the like, the following effects can be obtained. That is, (1) a charging current or a discharging current of a capacitor which determines an oscillation cycle of a timer circuit is formed by applying a predetermined voltage to both ends of a resistance means, and this current is transmitted through a current mirror circuit; By designing the level amplitude of the capacitor so as to have a substantially fixed ratio relation to the voltage applied to both ends of the resistance means, the oscillation cycle of the timer circuit is changed to the resistance value of the resistor and the resistance of the capacitor. As a function of the capacitance, it is possible to obtain a stable value that is not affected by the power supply voltage of the circuit, the process variation of the circuit element, the ambient temperature, and the like.

(2) The above item (1) has an effect that the refresh operation cycle in the self-refresh mode can be set to a relatively large value that sufficiently compensates for the information holding time of the dynamic memory cell and suppresses the safety coefficient. can get.

(3) According to the above items (1) and (2), it is possible to reduce the power consumption during standby of a pseudo-static type RAM or the like including a refresh timer circuit, thereby achieving the effect of reducing the power consumption. .

Although the invention made by the inventor has been specifically described based on the embodiments, the invention is not limited to the above-described embodiments, and various changes can be made without departing from the gist of the invention. Nor. For example, in this embodiment, the oscillation cycle of the refresh timer circuit RTM is determined by controlling the discharge current of the capacitor C1, but the charge current of the capacitor C1 is formed by a similar resistor and current mirror circuit. By determining the charge level by the threshold voltage V _THP of the P-channel MOSFET, the oscillation cycle of the refresh timer circuit RTM may be determined by the charge time of the capacitor C1. Further, as shown in FIG. 3, the P-channel MOSFET Q8 forming the level determination circuit and the P-channel MOSFET Q6 formed in the current mirror form may be separated from the P-channel MOSFET Q5 formed in series with the resistor R2. In the case of FIG. 3, since the gate of the MOSFET Q5 is coupled to the ground potential of the circuit, the discharge current I2 of the capacitor C2 becomes I2 = (Vcc−V _THN ) / R2, and the level amplitude Δ of the capacitor C2, that is, the node n4.
Vn4 also, the ΔVn4 = Vcc-V _THN. In the case of the embodiment shown in FIG. 3, the MOSFET LQ for charging is used.
When 7 is turned on, MOSFET Q27 is turned off, so that the discharge current is stopped.

In the circuit block diagram of FIG. 1, the capacitor C1 is
It can be replaced by a plurality of similar capacitors selectively coupled by fuse means or the like. Further, the level amplitude ΔVn1 of the capacitor C1, that is, the node n1 may be, for example, an integer multiple or an integral multiple of the voltage applied across the resistor R1. In FIG. 1, the circuit configuration of the refresh timer circuit RTM can adopt various embodiments as long as necessary logical conditions are satisfied.

In the circuit block diagram of FIG.
ARY may be composed of a plurality of memory mats. In this case, a refresh operation for a plurality of word lines may be performed simultaneously by setting one word line in each memory mat to a selected state. Further, the pseudo-static RAM may be capable of simultaneously inputting and outputting a plurality of bits of storage data,
Each address decoder may be shared by the plurality of memory mats. Various embodiments, such as a block configuration of a pseudo-static RAM and a combination of a control signal and an address signal, can be adopted.

In the above description, the case where the invention made by the inventor is mainly applied to a pseudo-static RAM as a background of application has been described. However, the present invention is not limited thereto.
The present invention is also applicable to various semiconductor memory devices of M and various digital integrated circuit devices having similar timer circuits. The present invention can be widely applied to at least a semiconductor integrated circuit device having a built-in timer circuit using charging and discharging of a capacitor.

〔The invention's effect〕

The effects obtained by the representative inventions among the inventions disclosed in the present application will be briefly described as follows. That is, a charge current or a discharge current of the capacitor that determines the oscillation cycle of the timer circuit is formed by applying a predetermined voltage to both ends of the resistance means, and the level amplitude of the capacitor is given to both ends of the resistance means. By designing to have an almost fixed ratio relationship with the voltage, the oscillation cycle of the timer circuit can be
A stable value that is not affected by the power supply voltage of the circuit, the process variation of the circuit element, the ambient temperature, and the like can be obtained.
Accordingly, the refresh cycle in the self-refresh mode of the pseudo-static RAM or the like can be set to a relatively large value that sufficiently compensates for the information holding time of the dynamic memory cell and suppresses the safety coefficient. Including pseudo-static RAM
It is possible to reduce the power consumption during the standby state.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram showing one embodiment of a refresh control circuit including a refresh timer circuit to which the present invention is applied, FIG. 2 is a timing chart showing one embodiment of a first refresh control circuit, FIG. 3 is a circuit diagram showing another embodiment of a refresh timer circuit to which the present invention is applied. FIG. 4 is a circuit block diagram showing one embodiment of a pseudo static RAM including a first refresh control circuit. FIG. 5 is a circuit diagram of a refresh timer circuit of a pseudo static RAM developed by the present inventors prior to the present invention. RFC: Refresh control circuit, RTM: Refresh timer circuit, RTG: Refresh timing generation circuit, RCTR: Refresh address counter, DL1 to DL3
…… Delay circuit, N1-N9 …… CMOS inverter circuit, Q1-Q1
5 ... P-channel MOSFET, Q21-Q35 ... N-channel M
OSFET ~ R1 ~ R2 ... resistance, C1, C3 ... ... capacitor. PSRAM: pseudo-static RAM, M-ARY: memory array, SA: sense amplifier circuit, U
SA: sense amplifier unit amplifier circuit, CSW: column switch, RDCR: row address decoder, CDCR: column address decoder, RADB: address buffer, AMX
... address multiplexer, CADB ... column address buffer, MA ... main up, DOB ... data output buffer, DIB ... data input buffer, TG ... timing generation circuit. Cs: Capacitor for storing information, Qm: MO for address selection
SFET.

Claims (2)

(57) [Claims] A first P-channel diode-type first transistor provided between one end of a resistance element and a first power supply terminal.
A second N-channel MOSFET in the form of a diode provided between the other end of the resistor and a second power supply voltage; and a second MOSFET in the form of a current mirror with the second MOSFET. A third N-channel MOSFET sized the same as the second MOSFET, and a seventh P-channel MOSFET connected in series with the third MOSFET and configured as a diode.
And a P-channel type sixth MOSF provided between the source of the seventh MOSFET and the first power supply terminal.
ET, the first MOSFET and the first MOSFET in current mirror form.
A fourth P-channel type sized the same as the MOSFET
A MOSFET, an N-channel type fifth MOSFET provided between the drain of the fourth MOSFET and the second power supply terminal and having substantially the same size as the second MOSFET, and a gate of the fifth MOSFET; And the source, the sixth
And a capacitor to which a charge-up current is supplied through the seventh MOSFET, a delay circuit for performing a delay operation with respect to a fall of the drain output of the fifth MOSFET, and a sixth circuit which receives an output signal of the delay circuit. And a timer circuit comprising an inverter circuit for forming a feedback signal supplied to the gate of the MOSFET. 2. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor memory device includes a dynamic memory cell as a storage element, and a time constant including a resistance value of a resistor of the timer circuit and a capacitance value of a capacitor is: 2. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is set in accordance with a refresh cycle of said dynamic memory cell and is used for an automatic refresh operation thereof.