JPH02156498A - Refresh function incorporating dynamic type semiconductor memory device - Google Patents

Abstract

PURPOSE:To reduce unrequired power consumption in a substrate bias means by activating the substrate bias means only for prescribed partial time between refresh operating cycles in a self-refresh mode. CONSTITUTION:An intermittent operation control circuit 99 outputs an activation signal phiC with prescribed time width replying to a signal phiS from a self-refresh mode detection circuit 91 and a refresh request signal phiR from a timer 93. A substrate bias generation circuit 100 performs an outgoing only for around 0.5mus from the leading edge of the signal phiR by the signal phiC, and a substrate bias voltage is generated only for that period. In such a manner, the circuit 100 can be operated only in the period before and after the period when a word line is selected and a refresh operation is performed, which prevents the substrate bias voltage from fluctuating, and also, reduces the power consumption.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention generally relates to a dynamic semiconductor memory device with a built-in refresh function, and more particularly to a structure for further reducing power consumption of the dynamic semiconductor memory device. More specifically, the present invention relates to a configuration of a substrate bias voltage generation circuit that can generate a substrate bias voltage with less power consumption during a refresh operation.

[Background Art] In recent years, personal computers have become extremely popular and are used in various fields. Among such personal computers, demand for portable personal computers in particular has been increasing recently. As a storage device used in this portable personal computer, a storage device with low power consumption that can hold a battery (battery backup) is required.

As such a memory device, a dynamic semiconductor memory device (DRAM) or a static semiconductor memory device (SRAM) is usually used. Of these, DRA
M utilizes the principle of accumulating information charges in a MOS capacitor (a capacitor that uses a metal layer as one electrode, a semiconductor region as the other electrode, and an insulating film between them as a dielectric). However, in such a MOS capacitor, the stored charge is gradually lost due to leakage in the junction formed between the semiconductor region that serves as the other electrode and the semiconductor substrate, so the stored information is rewritten at regular intervals. It is necessary to include Such a rewrite operation is called a refresh operation. When a DRAM is used as a storage device in a portable personal computer, it is necessary to refresh the data at regular intervals even during battery backup.

Normal refresh modes for DRAM include RAS only refresh and CAS before RAS refresh. RAS-only refresh gives a row address for refresh (refresh address) from the outside,
Drop the row address strobe signal RAS to
This is a refresh mode that is performed by selecting the . In this RAS-only refresh, column address strobe signal CAS is at H' level.

CAS-before-RAS refresh mode uses signal RA
In this mode, before S is set to the "L" level, the signal σXS is first set to the "L" level to provide a refresh instruction signal, and refresh is automatically performed in accordance with this signal state. In these normal refresh modes, the signal RA
Refreshing is controlled cycle by cycle by an external clock signal such as S, CAS, etc. Therefore, using such a normal refresh mode during battery backup requires complicated control, which is not preferable.

Therefore, in order to easily refresh the battery even during battery backup, Yamada et al.
lf Refresh function built-in 64Kbit MO
S Dynamic RAM”, Transactions of the Institute of Electronics and Communication Engineers, 198
As explained in January 2003, Volume 166-0, Issue 1, Pages 62 to 69, an address counter that generates refresh addresses and a timer circuit that provides refresh timing for each row. A DRAM with a built-in self-refresh mode that automatically performs a refresh operation has been devised and put into practical use.

This self-refresh operation is explained in detail in the above-mentioned literature, but will be briefly explained below with reference to the drawings.

Figure 26 shows a conventional 6
FIG. 4 is a block diagram showing an example of the configuration of a bit DRAM. In the configuration of FIG. 26, only portions related to refresh operations are shown.

In FIG. 26, the DRAM has 256 rows (28) 256
a memory array 97 comprising memory cells arranged in rows and columns in columns (28); an address buffer 96 that receives and temporarily holds address signals from the address switching circuit 95 and generates internal address signals; and a row decoder 98 that selects a corresponding row from memory array 97 in response to an internal row address signal from address buffer 96.

Address buffer 96 supplies 7-bit internal address signals RAO-RA6 to row decoder 8. Although not explicitly shown, each memory array 97 has 128 rows 256
It is divided into two blocks in a column, and one column is read from each block by 7-bit lower address signals RAO to RA6.
Book word line.

That is, two word lines are selected at the same time. The most significant address signal RA7 from address buffer 96 is used as an address signal for block selection.

Address switching circuit 95 receives externally applied row address signals AO to A7 and refresh addresses QO to Q6 generated from refresh address counter 94, and selects one of them as an address under the control of refresh control circuit 92. It is transmitted to buffer 96. As address signals AO to A7 applied from the outside, a row address signal and a column address signal are time-division multiplexed and applied.

To specify DRAM self-refresh operation,
A self-refresh mode detection circuit 91 receives a signal REF applied through an input terminal 1 and detects whether a self-refresh mode is instructed, and responds to a self-refresh mode detection signal φS from the self-refresh mode detection circuit 91. address switching circuit 95
, refresh address counter 94 and timer 93
and a refresh control circuit 92 that generates a signal to control the operation of the refresh control circuit 92 . Address switching circuit 95 provides refresh addresses QO-Q6 from refresh address counter 94 to address buffer 96 in response to a refresh instruction signal from refresh control circuit 92.

Timer 93 outputs refresh request signal φ at predetermined intervals in response to refresh instruction signal φ from refresh control circuit 92 . The refresh address counter 94 has its count value incremented in response to the refresh request signal φ from the timer 93, and refresh addresses QO to Q corresponding to the count value are incremented.
6 is applied to the address switching circuit 95. Next, the operation will be briefly explained.

By keeping the signal RAS applied to the input terminal 2 at the "H" level (standby state) and lowering the external refresh signal REF applied to the input terminal 1 to the "L" level, the self-refresh mode detection circuit 91 detects the refresh state. It detects the instruction and outputs a refresh instruction signal φ.In response to this refresh instruction signal φ, the address switching circuit 95 selects the refresh addresses QO to Q6 from the refresh address counter 94.
is given to the address buffer 96. Address buffer 9
6 generates internal refresh addresses RAO-RA6 from the applied refresh addresses QO-Q6 and supplies them to row decoder 98.

Row decoder 98 decodes this 7-bit refresh address QO-Q6 (RAO-RA6) and selects one of the 128 rows in each block of memory array 97. Subsequently, a circuit (not shown) refreshes the data of the memory cells connected to the selected row.

Next, when this external refresh signal REF continues to be held at the "L" level for a predetermined set time (maximum 16 μs) or longer, self-refresh mode detection circuit 91 detects the designation of self-refresh mode.

In response to the detection of this self-refresh mode designation, refresh control circuit 92 raises signal φT and activates timer 93. In response to the activation signal φd, the timer outputs a refresh request signal φ and supplies it to the refresh control circuit 92 when a predetermined set time (maximum 16 μs) has elapsed. Refresh control circuit 92 increments the count value of refresh address counter 94 in response to refresh request signal φ. In response, the refresh address counter 94 sends a refresh address QO to Q6 different from the refresh address output in the previous refresh cycle to the address switching circuit 94.
give to Similarly to the previous refresh operation, one row corresponding to this refresh address QO-06 is selected in memory array 97, and the data of the memory cells selected in this selected one row is refreshed. The refresh request signal φ from the timer 93 is repeatedly generated at a predetermined period as long as the external refresh signal REF is at the "L" level and the signal AS is at the "H" level. In each block in the memory array 97, 128 word lines are sequentially selected in this self-refresh mode, and data in memory cells connected to the selected word lines is refreshed.
For RAM, all memory cells in memory array 97 will be refreshed every 16μ5×128 to approximately 2ms. During battery backup when the main power supply is turned off, the above-described self-refresh operation is automatically performed.

Normally, in the RAM as described above, this DRAM
A substrate bias voltage generation circuit is provided in order to reduce parasitic capacitance between the circuit elements constituting the DRAM and the semiconductor substrate on which the DRAM is formed, and to ensure high-speed and stable operation of the DRAM. That is, in a DRAM, normally, reduction of the junction capacitance between the semiconductor substrate and the impurity region, stabilization of the threshold voltage of the MOS transistor formed on the surface of the semiconductor substrate, signal wiring layer on the field insulating film, etc. If the semiconductor substrate is of P type, the semiconductor substrate is biased to a negative potential V[1[1] for the purpose of suppressing the generation of a parasitic MOS transistor consisting of an impurity region formed on the surface of the semiconductor substrate.

FIG. 27 shows a D with conventional self-refresh mode.
FIG. 3 is a diagram showing an example of a substrate bias voltage generation circuit of a RAM. Referring to FIG. 27, substrate bias voltage generation circuit 4
1 is provided between a ring oscillator 411 that outputs an oscillation signal φCP of a predetermined frequency, a charge pump capacitor C that receives an oscillation signal from the ring oscillator 411, a node N, and a ground potential; An n-channel M that clamps the potential of M to its threshold voltage level.
OS transistor Ql, node Na and output terminal 412
and an n-channel transistor Q2 which is provided between the transistor Q2 and clamps the node Na to a potential determined by the difference between its threshold voltage and the semiconductor substrate potential.

FIG. 28 is a signal waveform diagram for explaining the operation of the substrate bias voltage generation circuit shown in FIG. 27.

The operation of the substrate bias voltage generation circuit will be briefly described below with reference to FIGS. 27 and 28.

Oscillation signal φcP from ring oscillator 411 is “H”
When the level rises, the potential of node NB becomes capacitor C.
The power supply potential VCC tries to rise to the "H" level due to capacitive coupling. At this time, MOS transistor Q1 becomes conductive in response to the rise of the potential at node Na, and the potential at node N becomes MOS). Ransistor Q1
is clamped to the threshold voltage level Vd, . on the other hand,
MOS) transistor Q2 is in a non-conducting state.

Next, when the oscillation signals φ and P fall to the "L2 level," the potential of the node Na also decreases due to the capacitive coupling of the capacitor C.
OS transistor Ql is turned off, MOS transistor Q2 is turned on, and positive charges flow from the semiconductor substrate to node N111. When the potential of this node NB reaches a value equal to the difference between the semiconductor substrate potential VaB and the threshold voltage VT2 of the MOS transistor Q2, the MOS transistor Q2 becomes non-conductive and the movement of charges stops. This one rise and fall of the oscillation signal φCP causes the potential of the semiconductor substrate to decrease slightly. As such cycles continue several times, the voltage V of the semiconductor substrate
BB gradually decreases to a predetermined negative potential. Now, assuming that the operating power supply voltage is Vcc, the bias voltage VBB of this semiconductor substrate is V7, +V72-Vcc in an ideal case, and normally has a value of about -3V.

[Problems to be Solved by the Invention] A conventional dynamic semiconductor memory device is configured as described above, and the substrate bias voltage generation circuit operates in both the normal mode and the self-refresh mode. consumes the same amount of electricity.

However, in the self-refresh mode, other operations other than the refresh operation, such as data writing/reading and column selection operations, are not performed, so the substrate leakage current flowing into the semiconductor substrate is less than in the normal mode. , and the amount of leakage is also predictable. Therefore, although it is necessary to reduce power consumption as much as possible in self-refresh mode, that is, during battery backup, the substrate bias voltage generation circuit consumes the same amount of power as in normal operation mode, resulting in unnecessary power consumption. There was a problem that

Furthermore, Japanese Patent Application Laid-Open No. 61-59688 discloses a configuration in which two substrate bias voltage generation circuits having different bias capacities are provided and the substrate bias generation circuit with the larger bias capacity is operated during the self-refresh mode. However, even in this configuration, there is a problem in that the substrate bias voltage generation circuit with a large bias ability operates continuously during the self-refresh mode, consuming unnecessary power.

Therefore, an object of the present invention is to provide a dynamic semiconductor memory device that eliminates the drawbacks of the conventional dynamic semiconductor memory device described above and further reduces power consumption in self-refresh mode, that is, during battery backup. .

Another object of the present invention is to provide a dynamic semiconductor memory device with a built-in self-refresh function that is equipped with an improved substrate bias voltage generation circuit that generates a substrate bias voltage with lower power consumption in a self-refresh mode. .

Still another object of the present invention is to provide a substrate bias potential generation circuit built into a dynamic semiconductor memory device that can accurately respond to a semiconductor substrate potential and generate a substrate bias voltage with low power consumption during a self-refresh mode. It is to be.

[Means for Solving the Problems] A dynamic semiconductor memory device with a built-in refresh function according to the present invention includes means for generating an internal refresh instruction signal in response to an external refresh instruction signal;
means for refreshing memory cell data; and generating a signal for activating the refresh means periodically at predetermined intervals while the internal refresh instruction signal is in an active state in response to the internal refresh instruction signal. means for biasing the semiconductor substrate to a predetermined potential; and activating the biasing means for a time shorter than the time during which the activation signal becomes active in response to the internal refresh instruction signal and the activation signal. and means to do so.

[Function] In the dynamic semiconductor memory device of the present invention, in the self-refresh mode, the substrate bias means is activated only during a predetermined part of the time during the refresh operation cycle, so that unnecessary power consumption can be reduced.

[Embodiment of the Invention] FIG. 1 is a block diagram schematically showing the configuration of a dynamic semiconductor memory device that is an embodiment of the invention. 1st
In the figure, the structure of a refresh system and a substrate bias voltage generation system of a 4M (22.220) bit DRAM is shown as an example.

Referring to FIG. 1, a dynamic semiconductor memory device which is an embodiment of the present invention has 204g (2'1) rows 204
The memory array 97 includes eight (2") columns of memory cells arranged in rows and columns.

Memory array 97 is divided into two blocks with respect to word lines. Each block has 1024 rows and 2048 columns of memory cells. In order to select one row from the memory array 97, an address switching circuit 95 selectively passes either the external address signals AO to A10 or the refresh addresses QO to Q9 from the refresh address counter 94, and an address switching circuit. 95 receives the address signal from address buffer 96 which generates internal row address signals RAO to RAIO, decodes the 10-bit internal address signals RAO to RA9 from address buffer 96, and selects a corresponding row from memory array 97. A row decoder 98 is provided. One word line from each block, a total of two word lines, is simultaneously selected by the 9-bit lower address signals RAO-RA9. The most significant row address signal RAIO from address buffer 96 is used as a block selection address signal.

In order to refresh the semiconductor memory device, it is detected whether or not self-refresh is instructed in response to external refresh signal REF and row address strobe signal RAS applied to input terminals 1 and 2, respectively. A self-refresh mode detection circuit 91 outputs an internal self-refresh instruction signal φ when instructed, and an internal self-refresh detection signal φ from the self-refresh mode detection circuit 91.
The refresh control circuit 92 includes a refresh control circuit 92 that starts a timer 93 and a refresh address counter 94 in response to an activation signal φT from the refresh control circuit 92, and a timer 93 that is activated in response to an activation signal φT from the refresh control circuit 92 and outputs a refresh request signal at predetermined intervals. The timer 93 is activated in response to a refresh instruction signal (activation signal) φT from the refresh control circuit 92, and outputs a refresh request signal φ every predetermined set time (maximum 16 μs) while the signal φT is in an active state. It is applied to refresh control circuit 92 and intermittent operation control circuit 99. Signal φT is activated when signal φ is activated for a predetermined period of time or longer.

Refresh address counter 94 increments its count value under the control of refresh control circuit 92 in response to refresh request signal φ8 from timer 93. Further, refresh control circuit 92 causes address switching circuit 95 to select refresh address signals QO-Q9 from refresh address counter 94 in response to internal self-refresh detection signal φ from self-refresh mode detection circuit 91.

In order to apply a predetermined bias potential to the semiconductor substrate, activation is performed for a predetermined time width in response to the internal self-refresh detection signal φ from the self-refresh mode detection circuit 91 and the refresh request signal φ from the timer 93. is activated in response to an intermittent operation control circuit 99 outputting a signal φ, and a control signal φC from the intermittent operation control circuit 99;
A substrate bias voltage generation circuit 100 is provided to apply a predetermined bias voltage to a semiconductor substrate.

In the above configuration, each time the refresh request signal φ is generated, the refresh address counter 94 increments its count value and outputs the refresh address signal QO.
~Q9 is output according to the count value. These refresh address signals QO to Q9 are supplied to the address switching circuit 95.
and is applied to row decoder 98 via address buffer 96. The row decoder 98 receives these 10-bit refresh address signals QO to Q9 (internal/internal address signal R).
When AO to RA9 are given as complementary data, 20
bit) to select a corresponding row within each block of memory array 97. Thereafter, the data in the memory connected to this selected word line is refreshed. Therefore, in the self-refresh mode, data in all memory cells in memory array 97 is refreshed every 16μ5×1024 to approximately 16m5. In this self-refresh mode, the DR
The signal RAS, which defines the AM standby state and operating state, is at "H" level, and the internal refresh signal REF is
While Q is at the "L#" level, word lines in memory array 97 are sequentially selected according to refresh address signals QO-Q9, and memory data is refreshed.

FIG. 2 is a diagram showing an example of the configuration of the timer shown in FIG. 1. Referring to FIG. 2, a timer 93 includes a ring oscillator 93-1 which is activated in response to a signal φT from a refresh control circuit 92 and performs an oscillation operation, and a waveform shaping of the oscillation signal from the ring oscillator 93-1. and a counter circuit 93-3 that counts pulse signals from the buffer circuit 93-2 and outputs a refresh request signal φ every predetermined count value.

The ring oscillator 93-1 includes six stages of cascade-connected inverters 11 to I6, and a NAND gate N1, one of which receives the output of the inverter I6 manually, and the other input of which receives the activation signal φT from the refresh control circuit 92. . The output of the NAND gate N1 is given to the buffer circuit 93-2, and is also fed back to the input section of the first stage inverter 11.

Buffer circuit 93-2 includes four stages of cascade-connected inverters 7-110. The buffer circuit 93-2 corrects the roundness of the waveform of the oscillation signal output from the ring oscillator 93-1, and the inverter 110 outputs the oscillation signal φ, and the inverter 12 output is inverted by the inverter 111 to produce an inverted output signal φ. These mutually complementary oscillation signals φr and ar are applied to a counter circuit 93-3.The counter circuit 93-3 has four
It is provided with binary counters BCI to BC4. Each of the binary counters BCI-BC4 has an input section 1. The frequency of the signal applied to I is divided into half and output. Next, the operation will be explained.

First, the operation of the ring oscillator 93-1 will be explained with reference to FIG. 3A, which is an operation waveform diagram. When the activation signal φT from the refresh control circuit 92 is at the L' level and the self-refresh mode is not specified, the output of the NAND gate N1 remains at a constant "H" level.
level, and ring oscillator 93-1 does not perform oscillation operation.

Next, the signal φS becomes “H” level for a predetermined period of time or longer, the self-refresh mode is detected, and the activation signal φT becomes “H” level.
``When the level rises, the NAND gate N1 operates as an inverter. Therefore, the inverters 11 to !6 and the NAND gate N1 become equivalent to a seven-stage inverter, and the ring oscillator 93-1 starts oscillating operation. The oscillation signal from 93-1 is applied to a buffer circuit 93-2, where the waveform is shaped. The waveform-shaped oscillation signals φ' and φr, which are complementary to each other, are applied to a counter circuit 93-3.

Binary counter BCI- included in counter circuit 93-3
BC3 performs a counting operation as shown in FIG. 3B.

That is, the binary counter BCI derives the output signal 01 which rises to the "H" level every time the oscillation signal φ" is applied twice. Therefore, when the signal φr has a period of 1 μs, the output signal 01 of the binary counter BCI has a duty cycle. 50 cycles 2
A μs signal is output. Similarly, output signal 02 with duty 50 and period of 4 μs is derived from binary counter BC2, and output signal 02 with period of 8 μs is derived from binary counter BC3.
, an output signal 03 of the duty 50 is derived. As a result, the refresh request signal φ is output from the binary counter BC4.
, a signal with a duty of 50° and a period of 16 μs is output. When this refresh request signal φ reaches the "H" level, a refresh operation is performed.

Note that a reset signal RESET is applied to each of the binary counters BCI to BC4, so that the count output can be reset to a predetermined value as necessary.

FIG. 4 is a diagram showing an example of the configuration of the intermittent operation control circuit shown in FIG. 1. With reference to FIG. 4, the intermittent operation control circuit 99
are a one-shot pulse generation circuit 99-1 that outputs a one-shot pulse signal φT in response to a refresh request signal φ from the timer 93, and a one-shot pulse signal φT from the one-shot pulse generation circuit 99-1. ,
and a flip-flop 99-- which outputs a signal φ (for controlling the operation of the substrate bias generation circuit 100) in response to the self-refresh instruction signal φ from the refresh mode detection circuit 91 and the inverted oscillation signal φr from the timer 93.
2.

The one-shot pulse generation circuit 99-1 includes three stages of cascade-connected inverters 1 that receive a refresh request signal φ.
20 to 22, and a NAND gate N10 which receives the output of the inverter 122 at one input and receives the refresh request signal φ at the other input. Inverter I20~
122 inverts and delays the refresh request signal φ, and applies it to one input of the NAND gate NIO.

The SR flip-flop 99-2 receives the one-shot pulse signal φ, the self-refresh mode detection signal φ, and the output of the NAND gate N12, and receives the output of the NAND gate Nil at one input thereof, and the other inputs. A two-man power NAND gate N12 receives an inverted oscillation signal φ' from a ring oscillator 93-1 and a buffer circuit 93-2 included in the timer 93 at one input.
including. A signal φC for controlling the operation of substrate bias generation circuit 100 is output from NAND gate Nil. Next, the operation of the intermittent operation control circuit 99 will be explained.

First, the DRAM is in a state other than the self-refresh mode, and the self-refresh mode detection signal φS is “L”.
The operation when the NAND gate Nil is at the “level” will be explained with reference to FIG. 5A. In this case, the NAND gate Nil output is
Regardless of the state of the AND gate N12 output and the signal φd, it is always at the "H" level. As will be described later, when this signal φC is at "Ho", the substrate bias voltage generation circuit 100 is activated and supplies a bias potential to the semiconductor substrate.

Next, consider a case where the signal REF goes to the "L" level and the DRAM enters the self-refresh mode after a predetermined period of time has elapsed. In this case, in response to the transition of the signal REF to the "Ho" level, the self-refresh mode detection signal φ becomes "H level" as shown in FIG. 5B. The predetermined time has not passed and the self-refresh request signal φ is
When L° level is reached, one-shot pulse generation circuit 9
The output signal φT of 9-1 is at the "Ho level." Next, when a predetermined period of time elapses and the refresh request signal φ rises to "H", the signal φT5 changes to a predetermined level in response to the rise of the signal φ. (this is determined by the delay time of inverters 110 to 112) falls to the 'L2 level. As a result, the NAND gate Nl1 output goes to "H".
Rubel stands up. The rise of the output signal φC of the NAND gate N11 is synchronized with the rise of the inverted signal φr, and while the inverted signal φr is at H'' level, the signal φ is maintained.

becomes "Ho" level.Next, when the inverted signal φT shifts to "L° level", all the input signals of the three-power NAND gate Nil become "H" level, and the output signal φ becomes "
The time width in which this signal φ becomes active is 0.5 μs when the period of the oscillation signal φ” from the timer 93 is 1 μs.

FIG. 6 shows the substrate bias voltage generation circuit 100 shown in FIG.
FIG. 2 is a diagram showing an example of a specific configuration. In the configuration shown in FIG. 6, the substrate bias potential generation circuit 100 includes a charge pump capacitor C1, potential clamping MOS transistors Ql and Q2, and an oscillation signal φ(
and a ring oscillator 511 that outputs F. The ring oscillator 511 receives a control signal φ from the intermittent operation control circuit 99. Its operation is controlled by FIG. 7 shows an example of a specific configuration of the ring oscillator 511 shown in FIG. 6.

Referring to FIG. 7, ring oscillator 511 receives at one input the output of inverter I36 from six stages of inverters 130 to 136 connected in cascade, and receives control signal φ. a NAND gate N30 receiving at its other input;
It consists of two stages of cascade-connected inverters 137 and 138 that receive the output of NAND gate N30. NAND
Gate N30 receives control signal φ. When the control signal φ is at the “Ho” level, it operates as an inverter, and when the control signal φ is at the “L° level, a signal at the “H°” level is output regardless of the output state of the inverter 136. Therefore, the control signal φ.
In the case of “H”, inverters 130 to 136 and NAND
Gate N30 forms a seven-stage ring oscillator. N
The output of the AND gate N30 is connected to a charge pump capacitor C via waveform shaping inverters 137 and 138.
It is output as an oscillation signal φcP that defines the charge pump operation.

As is clear from comparing the configuration of the ring oscillator shown in FIG. 7 with the conventional configuration shown in FIG. 27, the conventional ring oscillator shown in FIG. 27 always oscillates regardless of the operating state of the DRAM. However, the ring oscillator 511 according to the present invention shown in FIG. 7 receives the control signal φ. It oscillates only when the control signal φC is "L", and does not oscillate when the control signal φC is "L", and its output signal maintains the "H# level". This control signal φC is as shown in FIG. 5B.
A refresh request signal φ, which is an output from the timer 93,
The level is set to H'' only for a predetermined period of time.

On the other hand, as described above, the refresh address counter 94 is activated via the refresh control circuit 92 in response to the refresh request signal φ, and the word line at the address corresponding to the value of the output refresh address signals QO to Q9 is activated. Data in memory cells selected from memory array 97 and connected to the selected word line is refreshed. Focusing on the temporal relationship between the activation timing of the refresh request signal φ, the word line selection timing, and the ring oscillator oscillation signal timing, the case of the conventional device and the case of the embodiment according to the present invention are compared. What is shown is the timing operation waveform diagram shown in FIGS. 8A and 8B. Here, FIG. 8A shows the relationship among the refresh request signal, word line selection state, and charge pump oscillation signal φcP in a conventional DRAM, and FIG. 8B shows the relationship among these signals in an embodiment of the present invention.

As shown in FIG. 8A, the refresh request signal φ is 1
When the word line reaches the "H0 level" every 6 μs, the word lines are sequentially selected in response to the refresh address signal from the refresh address counter 94, and the potential WL of the selected word line becomes the "H# level." For example, as shown in FIG. 8A, the nth word line is activated at time t (n), and the (n+1)th word line is activated at time t (n+1) 16 μs after that time t (n). be done. In this case, in the configuration of the conventional substrate bias voltage generation circuit, the ring oscillator 4 included therein
The output signal φCP of No. 11 oscillates continuously regardless of the generation timing of these word line selection and refresh request signals φ.

However, as shown in FIG. 8B, in the substrate bias potential generation circuit according to one embodiment of the present invention, the oscillation signal φcP from the ring oscillator 511 oscillates only for about 0°5 μs from the rise of the refresh request signal φ. The substrate bias voltage is generated only during this period. With this configuration, as is clear from FIG. 8B, the substrate bias generation circuit can be operated only before and after the period (usually about 100 to 200 ns) during which a word line is selected and a refresh operation is performed. becomes possible.

Generally, the substrate bias voltage decreases in absolute value due to leakage current such as that generated between the source and drain regions of the MOS transistor and the semiconductor substrate. here,
Leakage current to a semiconductor substrate is not necessarily constant and is influenced by its circuit operation. This substrate leakage current is MO
It is relatively small when the switch state of the S transistor is fixed or static, but increases accordingly when the circuit of the storage device is in an active state and the switch state of the MOS transistor changes. Therefore, since the substrate bias voltage may change mainly when the word line is activated and memory refresh operation is performed, it is possible to change the substrate bias voltage by operating the substrate bias voltage generation circuit only during this time. , it is possible to prevent fluctuations in the substrate bias voltage and also to reduce power consumption in the substrate bias voltage generation circuit.

FIG. 9 is a diagram showing an example of a specific configuration of the self-refresh mode detection circuit 91. Referring to FIG. 9, detection circuit 91 includes an inverter 911 that receives external refresh signal REF applied to input terminal 1. Referring to FIG. Input terminal 1
A high resistance pull-up resistor R5 is provided between the input section of the inverter 911 and the input section of the inverter 911. In this configuration, when the external refresh signal REF enters the 'H level or oven state, the input of the inverter 911 is pulled up to the power supply potential level Vcc by the high-resistance pull-up resistor Rs, so the output of the inverter 911 φ , is “L
When the external refresh signal REF goes low, the inverter 911 outputs an output signal φ at the high # level. With this configuration, the internal refresh signal REF that instructs the self-refresh mode in response to the external refresh signal A refresh instruction signal φ can be output. When the signal φ remains at the "H" level for a predetermined period of time or more, the self-refresh mode is detected and the signal φ rises.

FIG. 10 shows a row address strobe signal RAS from the outside, which is normally used in DRAMs, rather than a dedicated control signal input terminal for instructing refresh.
FIG. 12 is a diagram showing a configuration when instructing a self-refresh mode using a column address strobe signal CAS and a column address strobe signal CAS. In the configuration shown in FIG. 10, the self-refresh mode detection circuit 91 includes a flip-flop which receives a set power S which receives a signal RAS applied through an input terminal 2 and a reset power R which receives a signal CAS applied through an input terminal 3. flip-flop 921 and flip-flop 921
Comparison circuit 922 receiving signal cbR from output terminal Q of
and a timer 923 that is activated in response to an activation signal from comparison circuit 922 and counts a predetermined set time. Timer 923 is activated via comparison circuit 922 in response to the transition of signal CbR to the active state. Comparison enclosure 9
22 outputs a signal Cb in response to clock information from the timer 923.
When R is in the "H" level active state for a predetermined period of time or more, internal refresh instruction signal φ.

launch. Next, the operation of self-refresh mode detection circuit 91 shown in FIG. 10 will be explained with reference to FIG. 11, which is an operation waveform diagram of self-refresh mode detection circuit 91 shown in FIG.

In this configuration, the self-refresh instruction is given by setting the signal CAS to "L" while the signal RAS is at the "H" level.
This is done by lowering the

In this CAS-before-RAS refresh state, flip-flop 921 is set and its output signal CbR becomes "H" level. Timer 923 is activated via comparison 7 circuit 922 in response to the transition of signal CbR to the "H" level, and counts a predetermined set time T. If the signal CbR is continuously at the "H" level when the timer 923 counts a predetermined count value (predetermined set time), the comparison circuit 922 outputs "H".
A level signal φ is output. The "H" level state of the signal CbR is maintained while the signal CAS is at the "L" level, during which time the "H" level signal φ is output.
When AS becomes H level, the flip-flop 921 is reset, its output signal CbR becomes an "L" level, and the signal φ from the comparator circuit 922 accordingly becomes an "L" level. This completes the self-refresh operation.

FIG. 12 is a block diagram schematically showing the structure of a substrate bias voltage generating circuit according to another embodiment of the present invention. The substrate bias voltage generation circuit shown in FIG. 12 has a main bias circuit 110 with large bias capability (current supply capability)
and sub-bias circuit 1 with relatively small bias capacity.
20.

In this configuration, the switching circuit 6 responds to the substrate potential detection signal φ0 from the substrate potential detection circuit 610 to either the main bias circuit 110 or the sub bias circuit 120.
A configuration is adopted in which the oscillation signal φcP from the ring oscillator 511 is transmitted under the control of the ring oscillator 511.

The main bias circuit 110 includes a charge pump capacitor Cr+ receiving an oscillation signal φcPM from a switching circuit 600, and potential clamping MOS transistors Q+n and Q2m.
Equipped with

The sub-bias circuit 120 includes a charge pump capacitor C8 receiving the oscillation signal φcps from the switching circuit 600;
It includes MOS transistors Q+s and Qzs for potential clamping.

Normally, the bias ability (current supply ability) of a bias potential generation circuit that uses the charge pump action of a capacitor is
The amount of charge injection per time and the number of charge injections per unit time are determined by the capacitance value of the charge pump capacitor, the oscillation frequency of the ring oscillator, and the driving ability of the potential clamping MOS transistor.

Therefore, the capacitance value of capacitor Cn is changed to capacitor C8.
is larger than the capacitance value of MOS transistor 02.
By making the drive capability (transistor size) of M larger than that of the MOS transistor Q2S, the bias capability of the raw bias circuit 110 can be made larger than the bias capability of the sub bias circuit 120.

Next, the operation will be briefly explained. Consider a state in which the ring oscillator 511 is oscillating. Substrate potential detection circuit 610 detects the potential level of substrate bias voltage VBB. For example, if the detected value is smaller in absolute value than a predetermined potential level, the switching circuit 600 is controlled to activate the main bias circuit 110 and rapidly reduce the substrate bias potential Vaa to a predetermined level. let After the substrate bias potential VaS reaches this predetermined value, the switching circuit 600 activates the sub-bias circuit 120 in response to the detection signal φ0 from the substrate bias potential detection circuit 610. In this way, in the oscillation state of the ring oscillator 511, by adjusting the bias ability of the substrate bias voltage generation circuit according to the potential level of the substrate bias voltage V[1[1, only a single bias ability as shown in the sixth factor can be generated. It is possible to further reduce power consumption than when using a substrate bias generation circuit having the following structure.

The thirteenth factor is a diagram showing an example of a specific configuration of the substrate bias potential detection circuit shown in FIG. 12.

Referring to FIG. 13, a substrate potential detection circuit 610 includes a p-channel MOS transistor Q3, an n-channel MOS transistor 4, and an n-channel MOS transistor connected in series between a power supply potential Vcc and a semiconductor substrate bias potential Vaa.
) includes transistor Q5. One conductive terminal of MOS transistor Q3 is connected to power supply potential Vcc, its gate is connected to ground potential GND, and the other conductive terminal is connected to node N1. n channel MOS transistor ro 4
has its gate connected to ground potential, its - conduction terminal connected to node N1, and its other conduction terminal connected to node N1.
Connected to 2. The gate and one conduction terminal of n-channel MOS transistor RO5 are connected to node N2, and the other conduction terminal is coupled to substrate bias potential V[1fl. The output potential level of node N1 is applied to switching circuit 600 as substrate potential detection signal φ0 via two stages of inverters 150 and 151 for waveform shaping.

Next, the operation of this circuit will be explained.

MOS) transistor Q3 has its gate connected to the ground electron GN.
Since it is connected to D, it is always in a conductive state. now,
Consider a state where the substrate bias voltage Vaa is small in absolute value and the substrate bias is shallow. Now, hypothetically, substrate bias potential V
When [1[1 is Ov, the potential of node N2 has a value equal to the threshold voltage level of transistor Q5. Since the gate of the n-channel MOS transistor Ro4 is connected to the ground potential and the potential of the node N2 is higher than Ov, the MO
S transistor Q4 is in an off state. Therefore, the potential of node N2 is charged to a high level via MOS transistor Q3. Therefore, in this case, the substrate potential detection signal φ0 becomes "H" level.

Now, the substrate bias potential Vaa is -(Vv s+vT4)
Let us consider a case where the absolute value becomes larger.

Here, V, , V□4 are transistors Q5 and Q, respectively.
The threshold voltage is 4. In this case, the potential level of node N2 becomes greater than -VT4 in absolute value. As a result, MOS transistor Q4 is turned on, and MOS transistor Q4. Both Q5 become conductive. At this time, by appropriately selecting the ratio of the conductances of the MOS) transistor Q3 and the MOS) transistor Q4, the node N1
can be set as the “L” level for the inverter 150. Therefore, if the substrate bias is deep,
Signal φD becomes "L" level. After that, the substrate bias voltage Vaa decreases to -(VT
When s + VT 4 ) becomes smaller in terms of absolute fa, MOS) transistor Q4 becomes non-conductive, the potential of node N1 becomes "H° level, and control signal φ0 becomes "" again.
It becomes H'' level.

Here, MOS transistor Q4. When Q5 are both turned on, current flows from the power supply potential Vcc to the substrate, changing the substrate bias voltage. The current flowing into the semiconductor substrate from this power supply potential Vcc reduces the substrate bias voltage Vaa in absolute value. MOS
The conductance of transistor Q3 is set to a value as small as possible, that is, a high resistance.

FIG. 14 is a diagram showing an example of a specific configuration of the switching circuit 600 shown in FIG. 12. With reference to FIG. 14, the switching circuit 6
00 is an AN that receives the oscillation signal φcP from the ring oscillator 511 and the detection signal φ0 from the substrate potential detection circuit 10.
D gate AD1, oscillation signal φCF and control signal φ0
and a two-man powered NOR gate NR1. A signal φ (Pfi) that controls the operation of the first main bias circuit 110 is output from the AND gate AD1.NOR gate NR1
A signal φ for controlling the operation of the sub-bias circuit 120. P
, is transmitted. Next, the operation of the switching circuit 600 shown in FIG. 14 will be explained with reference to FIG. 15, which is an operational waveform diagram.

First, when the substrate bias is shallow, the detection signal φ from the substrate potential detection circuit 610 is detected. Consider the case where is at the 'Hm level. In this case, the NOR gate NR1 outputs the signal φcps at the "L2 level" regardless of the state of the oscillation signal φcP.

On the other hand, AND gate AD1 receives oscillation signal φ. Let P pass through as is. Therefore, when this signal φ0 is "H", the signal φ.

Po performs an oscillation operation similar to that of the oscillation signal φ(r, the charge pump operation in the main bias circuit 110 is activated, and the bias voltage Vaa is applied to the semiconductor substrate via the main bias circuit 110.

Next, consider a case where the substrate bias becomes deep and the control signal φD becomes "L" level. In this case, contrary to the above case, the AND gate ADI output signal φcP,, is fixed at "L° level," while the NOR gate NR1 functions as an inverter, and the output signal φ.P is a signal obtained by inverting the oscillation signal φcr. As a result, main bias circuit 1
10 does not operate, and the sub-bias circuit 120 with small bias capacity starts charge pump operation, and the substrate voltage V[l
[1 is applied to the semiconductor substrate.

FIG. 16 is a block diagram showing the configuration of a substrate bias voltage generation circuit 100 according to another embodiment of the present invention. 1st
The substrate bias voltage generation circuit 100 shown in FIG. 6 includes a control circuit 700 for selectively operating either the main bias circuit 110 or the sub-bias circuit 120. The control circuit 700 includes a reference potential generation circuit 720 that generates a predetermined negative reference potential, and a substrate potential detection circuit that has a high input impedance and detects the potential of the semiconductor substrate via an input section with this high input impedance. 730, the reference potential from the reference potential generation circuit 720 and the substrate potential detection circuit 73
A comparison circuit 740 that compares the detected potential from 0 to 0 and a comparison circuit 740 that outputs an oscillation signal φcr from the ring oscillator 511 to either the main bias circuit 110 or the sub-bias circuit 120 in response to a signal indicating the comparison result from the comparison circuit 740. and a switching circuit 710 for selectively transmitting the signal to the.

This configuration of detecting the substrate potential through high human power impedance has the following advantages. For example, in the configuration of the substrate potential detection circuit shown in FIG.
．． When both Q5 become conductive, a current flows from the type R potential Vcc to the substrate bias potential Vaa.

In this case, even if the conductance of transistor Q3 is made as small as possible in order to minimize the amount of leakage current, it is not possible to prevent the current from flowing into the substrate. This current flowing into the substrate reduces the substrate bias potential Vaa in absolute value, making the substrate bias shallow. When the substrate bias becomes shallow, the substrate bias circuit 110 with a large bias ability operates. Therefore, the main bias circuit 110 is operated by the leakage current of the substrate potential detection circuit itself, and the substrate bias potential detection circuit itself is functioning in the direction of shallowing the substrate bias.
10 is activated.

However, in the configuration shown in FIG. 16, since the substrate potential is detected through an input section having a high input impedance, it is possible to accurately detect the substrate potential while eliminating the influence on the substrate potential. This substrate potential is compared with a predetermined negative potential generated internally, and based on the comparison result, the main bias circuit 110 and the sub bias circuit 12
0 is activated. As a result, bias circuits having different bias capacities can be operated appropriately in response to the substrate potential more accurately, and a substrate bias potential generation circuit with lower power consumption can be realized.

FIG. 17 is a diagram showing an example of a specific configuration of the selection control circuit 700 shown in FIG. 16. Referring to No. 17, the reference potential generating circuit 720 that generates the reference potential V' reaching a predetermined negative potential level (when the semiconductor substrate is P-type) and the output potential V' of the reference potential generating circuit 720 are detected. A p-channel MOS transistor QIG that detects the substrate potential v8[1, a p-channel MOS transistor 02G that detects the substrate potential v8[1, and a main bias circuit 110 and a sub-bias circuit 120 in response to the detection outputs of these MOS transistors QIG and 02G.
MOS) transistors Q7G and Q8G that generate a signal that inactivates one of the bias circuits and activates the other bias circuit.
, QIIG, and Q12G. Transistor Q7G, Q
8G, QIIG.

Q12G constitutes a flip-flop type differential amplifier with a CMOS configuration, and output nodes PI and P2 have MO for potential detection.
S) Generate a signal according to the output of transistors QIG and 02G. Oscillation signals φCr$+φcPM are output from nodes PI and P2 to be applied to main bias circuit 110 and sub bias circuit 120, respectively. M for potential detection
O8) Transistors QIG, Q2G and output nodes Pi, P
2, a p-channel MOS) transistor Q3 between each
G, 04G are provided. These MOS transistors 03G and 04G have a cutoff function to prevent a through current from flowing from the power supply potential Vcc to the output nodes P1 and P2 when the potential detection MOS transistors QIC and Q2C become conductive, respectively. It has the function of a transistor.

MOS transistors 07G and 08 are used to precharge output nodes PI and P2 to predetermined potential levels, respectively.
p channel MOS) transistor Q5G, 06 in parallel with G
G is provided. MOS) The oscillation signal φc from the ring oscillator 511 is sent to the gates of transistors Q5G and Q6G.
P is applied. Therefore, MOS transistor Q5
G and Q10 are turned on when the oscillation signal φ(r goes to the L level), and precharge the nodes Pi and P2 to the power supply potential Vcc level, respectively.

In order to activate the flip-flop type differential amplifier (MOS differential amplifier circuit consisting of transistors Q7G, Q8G, QIIG, and Q12G), an n-channel MOS
) An oscillation signal φcP via an inverter 11 is applied to one conduction terminal (source) of the transistors QIIG and 012G.

Furthermore, a MOS that functions as a cut-off transistor
Internal control signals φ and / are applied to the gates of transistors Q3G and 04G. These internal control signals φ, / are generated by passing the oscillation signal φ(P) from the ring oscillator 511 through inverters 120, 120.The internal control signal φcP' is generated by inverter 12G and It has a predetermined delay time.

The reference potential generation circuit 720 that generates the reference potential Vr has a configuration as shown in FIG.

Referring to FIG. 18, reference potential generation circuit 720 includes a charge pump capacitor CIG and a p-channel MOS transistor that cooperates with the charge pump operation of capacitor CIG to clamp the potential of node B1 to a predetermined potential. It has Q9G, QlOG, and a parasitic capacitance jlc2G. p channel MOS) transistor Q9G is node B
1 and the ground potential, and clamps the node B1 potential to its threshold voltage level. p-channel MOS transistor QIOG is connected to node B1
and the output node B2, and clamps the potential of the node B2 to a value determined by its threshold voltage and the reference potential V'.The p-channel MOS transistor QIOG is also diode-connected.

This reference potential generation circuit 720 has a capacitor and a p-channel MOS transistor as its constituent elements.
As shown in FIG. 9, it is formed in an n-type well region 160 formed on the surface of a p-type semiconductor substrate 150. Parasitic capacity J
IC2G is connected to p where this reference potential generation circuit 720 is formed.
It includes a junction capacitance formed between a type impurity region (not clearly shown) and the n-well 160, and the like. The output V'' from this reference potential generation circuit 720 is applied to a small volume p+ type impurity region 170 formed in the n type well 160, and biases this p+ type impurity region 170 to a predetermined negative potential level. Oscillation signal φCF for operating base $ potential generation circuit 720 is applied via inverter IIG.

FIG. 20 is a signal waveform diagram showing the operation of the substrate bias potential generation circuit shown in FIG. 17. The operation of a substrate bias generation circuit according to another embodiment of the present invention will be described below with reference to FIGS. 17 to 20.

First, although not directly related to the self-refresh mode, in order to better understand the operation of the selection control circuit 700, the transient operation immediately after power is turned on to the storage device will be described.

In an initial state such as when power is applied to the semiconductor memory device, the reference potential V' and the substrate bias potential Vaa are both at the ground potential level of Ov.In response to this power application, the ring oscillator 511 shown in FIG. It is necessary to start the oscillation operation of the ring oscillator 511 and rapidly lower the substrate bias potential to a predetermined potential.
As shown in FIG. 4, the configuration is such that it operates even in the normal operation mode. The configuration in which the ring oscillator 511 is operated even during normal operation is that the signal φ is an open signal φ at the "L" level, as shown in FIG. but"
H” level, and the substrate bias voltage generation circuit 100
This is realized by a configuration in which the

When the iS power is turned on, the ring oscillator 511
When the reference potential generation circuit 720 operates, the reference potential Vr, which is the output of the reference potential generation circuit 720, quickly reaches a predetermined level -■. However, on the other hand, the substrate bias potential VBa applied to the semiconductor substrate 150 reaches the predetermined bias level more slowly than the fall of the reference potential Vr. The time difference in the potential drop between the reference potential V' and the substrate bias potential Vaa occurs due to the following reason. In other words, the reference potential generation circuit 720 is formed in, for example, the n-type well region 160, and generates the reference potential Vr. In order to achieve this, it is sufficient to lower the potential of the small volume p + type impurity region 170 formed in the n type well region 160, so that the predetermined bias potential -Vr can be quickly achieved.On the other hand, In order to lower the potential of the semiconductor substrate 150 to a predetermined level, it is necessary to lower the potential of the entire semiconductor substrate 150, and considering the capacitance ratio (approximately several thousand times) between the p+ type impurity region 170 and the semiconductor substrate 150, This is because it takes a relatively long time (approximately several hundred microseconds) for the potential of the semiconductor substrate 150 to decrease.

In such an initial state, when the reference potential ■ is larger in absolute value than the substrate bias potential VB[1, that is, when the substrate bias is shallow, the potential detection MOS)
In transistors QIG and Q2G, the impedance of MOS transistor QIG is the same as that of MOS transistor 02.
It will be smaller than that of G.

When the oscillation signal φeP goes to the "L" level, the precharge MOS transistors Q5G and Q10 turn on, and the output nodes Pi and P2 go to the "H" level of the power supply potential Vcc level.
Precharged to level 2. At this time, since the output signal φCF from the inverter IIG is at the "H° level," the MOS transistors Q7G-Q10.QIIG, Q1
Flip-flops consisting of 2G do not work.

Next, the oscillation signal φ. When P goes to "H" level, precharging MOS transistors Q5G and Q10 turn off, stopping the precharging operation of output nodes Pi and P2.At this time, cutoff MOS transistor 0
Since the oscillation signal φCP is transmitted to the gates of 3G and 04G via inverters 120 and 121, the signal φ
, / are transmitted to the oscillation signal after being delayed by the delay time of these two stages of inverters 11G and 12G with respect to φcP.

Therefore, the transition of MOS transistors Q3G and Q10 to the off state is caused by the precharging transistors Q5G and Q
The transition to the OFF state of No. 10 is delayed by this delay time. In this state, when the output signal φ(r of the inverter IIG reaches the 'L° level, since the cutoff MOS transistors Q3G and 04G are still in the on state at this time, a potential difference is generated between the output nodes PI and P2, and the M
OS transistors Q7G, Q10. QIIG, Q12G
operates, the potential level of the output node P1 becomes 'H level, and the output level of the output node P2 becomes the "L° level."Next, when the oscillation signal φcP falls to the "L" level, the output node Pi , P2 are precharged to a predetermined power supply potential Vcc level in the same manner as described above. As a result, in response to the oscillation signal φcP, if the reference potential V'' is larger in absolute value than the substrate bias potential VllB, the output signal φcp from the output node P1 is
, is at “L” level, and the output signal φ(
Ffi becomes an oscillation signal corresponding to the oscillation signal φcP. As a result, the main 7 bias circuit 110 shown in FIG. 12 performs a charge pump operation to lower the substrate potential at high speed.

In the waveform diagram shown in FIG. 20, the signal φ is used to simplify the drawing. Although P and the signals φ, / are shown as having in-phase waveforms, in reality, this signal φ
, / is inverter IIG.

The signal φ(P changes with a delay from the signal φ(P) by the delay time of 12G.

In addition, in the above operation, immediately after the power is turned on, the ring oscillator 5
11 is in operation.

However, when the ring oscillator 511 is activated in response to the control signal φ in the self-refresh mode, the absolute value of the substrate bias potential V[1 & It can be applied as is when the substrate bias is small, that is, when the substrate bias is shallower, and the ring oscillator 51
1 is operating in oscillation, the substrate bias can be rapidly lowered to a predetermined level in response to a detection signal from the substrate potential detection circuit 730, and a more stable substrate bias can be supplied.

Next, the ring oscillator 511 receives the control signal φ.

We will explain the operation when the substrate bias potential Vaa is larger in absolute value than the reference potential V'' when the oscillation operation is started under the control of the The oscillation signal corresponds to the oscillation signal φcP, and the signal φCFffl becomes an "H" level signal.As a result, the semiconductor substrate bias potential becomes the predetermined reference potential -■.

When the absolute value becomes larger than (-Vr), only the sub-bias circuit 120 with a small bias ability operates, and the substrate bias continues to be stably supplied with low power consumption.

With the above configuration, during the oscillation operation of the ring oscillator 511, it is possible to selectively operate only one of the bias circuits having different bias capacities depending on the substrate potential, and the substrate bias potential generation circuit It is possible to achieve lower power consumption.

Furthermore, in the above configuration, the gate electrode of the MOS transistor Q2G is coupled to the semiconductor substrate as the configuration for detecting the semiconductor substrate potential Vaa.
The substrate potential detection circuit detects the substrate potential through an input needle with high input impedance, and since no current flows to the semiconductor substrate through the substrate potential detection circuit itself, the detection operation is performed on the semiconductor substrate. It becomes possible to accurately detect the semiconductor substrate potential without adversely affecting the potential.

FIG. 21 is a diagram showing another example of the configuration of the selection control circuit shown in FIG. 17. In FIG. 21, parts corresponding to those in FIG. 17 are given the same reference numerals.

In the configuration shown in FIG. 21, the cutoff MOS
Control signal φ that controls the operation of transistors 03G and Q10
, / is replaced with the inverter 12G shown in FIG.
Generated by flip-flop 750. Flip-flop 750 receives signals φ and P from inverter IIG and signal φapt + φ from buffer circuit 760.
,, # is received. Buffer circuit 760 receives signal φ from comparison detection circuit 700'. In response to PrI' and φCF5', the operation control signals φ, . . .
J and φcps' as well as the main bias circuit 110
and an operation control signal φ for the sub-bias circuit 120. F
Output rlr φcps.

The comparison detection circuit 700' compares the reference potential Vr from the reference potential generation circuit 720 and the substrate potential V[1[1, and generates signals φ, , r and φeFs' according to the comparison result.
are output from output nodes PI and P2, respectively. An example of a specific configuration of the flip-flop 750 is shown in FIG.

Referring to FIG. 22, flip-flop 750 includes two NOR gates N70. Contains N71. NOR gate N7
0 receives the signal φcP from the inverter IIG and the output of the NOR gate N71. NOR gate N71 receives two control signals φ from buffer circuit 760. , j and φCPM' and the output of NOR gate N70.

A signal φ(P'
is output. In this flip-flop 750, when the signal φcP is at “H”m level, the output signal φ
, / are reset to "L" level.

FIG. 23 is a diagram showing an example of a specific configuration of the buffer circuit 760 shown in FIG. 21. Referring to FIG. 23, buffer circuit 760 receives signal φ that controls the operation of main bias circuit 120. Fi output path and sub bias circuit 11
and a path for outputting a signal φcP that controls the operation of 0. The path for outputting the signal φ (Fyl) includes two stages of cascade-connected inverters 180 and 181 that receive the signal φeFM' from the output node P2 of the comparison detection circuit 700'.The inverter 180 controls the operation of the flip-flop 750. A signal φCFM' for controlling the main bias circuit 110 is outputted, and a signal φCP+1 for controlling the operation of the main bias circuit 110 is outputted from the inverter I81.

The path for outputting the signal φCPS is the comparison detection circuit 700'
It includes two stages of cascade-connected inverters 182 and 183 that convert the signal φCP5 from the output node P1 of the circuit. Inverter 182 outputs signal φCFS' that controls the operation of flip-flop 750, and inverter 183 outputs signal φePs that controls the operation of sub-bias circuit 120. Next, the operation of a bias circuit switching selection control circuit according to another embodiment of the present invention will be described with reference to FIGS. 21 to 23.

Now, the ring oscillator 511 receives the control signal φ. Consider the case where the oscillation operation is performed later, the oscillation signal φcP repeats the oscillation state, and the output signal φcP of the inverter IIG is at the "H0 level. In this case, the flip-flop 75
0 is a reset state. That is, NOR gate N7
Since an H” level signal is input to one input of 0,
Control signal φ. Regardless of the state of "PM+φCPg", a signal of "Lm level" is output from NOR gate N70. In response, the cutoff MO
3) Both transistors Q3G and Q4G are in a conductive state.

Next, when the output signal φcP from the inverter IIG shifts to the "L" level, the transistors Q7G, Q8G
, QIIG, and Q12G is activated and starts comparing the reference potential "■" from the reference potential generation circuit 720 with the substrate bias potential VB[1. has an output node PI
, P2 are precharged to the level of a predetermined power supply potential via MOS transistors Q5G and Q10, respectively, so that the output signals φca1 from output nodes PI and P2
1' + φCPS' are both at "H" level, and accordingly, the output signal φC' M from the buffer circuit 760
Both r φCPS' are at "L" m level. Therefore, in the initial state of activation of this CM OS JM flip-flop type differential amplifier (state in which the potential difference between the base potential Vr and the substrate bias potential Vaa is not expanded), the flip-flop 750 is in the reset state. The output signals φ and / remain at the "L" level. Therefore, even if the CMOS-configured flip-flop differential amplifier is activated, both cutoff MOS transistors 03G and 04G are still in the on state.

Next, due to the operation of the differential amplifier, output nodes P1 and P2
The potential level of the reference potential Vr and the substrate bias potential Vaa
When the "H" level and "L" level are determined based on the comparison result, the output signal φCP rl from the buffer circuit 760
Either one of rφl:F1' becomes H" level. As a result, flip-flop 750 is set, and the output signal φ, / becomes H" level. That is, in flip-flop 750, when one input of NOR gate N71 becomes "H" level, the output of NOR gate N71 becomes "L" level. As a result, NOR
Since both inputs of gate N70 are at "L" level, its output signal φeF is at H' level. this'
In response to the Hm level signal φcP', the cutoff MO
5) Both transistors Q3G and 04G are turned off,
The path through which the through current flows from the potential detection MOS transistors QIG and Q10 to the output nodes PI and P2 is cut off.

On the other hand, the potential level of the output nodes PI and P2 is set to the control signal φl:pH from the buffer circuit 760.

It is output as φcts and transmitted to the main bias circuit 110° and the sub bias circuit 120, respectively. Next, the oscillation signal φ is generated again. ? falls to “L” level, inverter IIG
When the output signal φcP from PI rises to "H" level, the flip-flop 750 is reset and the output node PI,
P2 are each precharged to the "H" level of the power supply potential Vcc level.

In the case of the configuration shown in FIG. 17, the base III potential generation circuit 72
When the reference potential V from 0 is very close to the value of the substrate bias potential VaB, C
Depending on the detection sensitivity of the MOS flip-flop type differential amplifier, it is possible that the cutoff MOS transistors Q3G and Q4G are turned off before the difference between the reference potential Vr and the substrate bias potential Vaa is detected. This is MO3) transistor Q for this cutoff.
Operation control of 3G and 04G is simply done by inverters IIG and 12.
Since the configuration was performed using the delay time of G,
Detection operation in the differential amplifier, that is, the output node Pi,
This is because the cutoff MOS transistors 03G and 04G are turned off at a predetermined timing regardless of the output level of P2.

Before such a difference between the substrate potential V[IB and the reference potential V'' is detected, the cutoff MOS transistor 03
When G, 04G turns off, the output node PI, P2
There is a risk that the potential levels of both become intermediate levels, and that a through current continues to flow from the power supply potential Vcc to the ground potential level through the CMOS flip-flop differential amplifier while the oscillation signal φ(P is at the "H° level". However, as shown in FIG.
By using 0 in place of the inverter for generating the cutoff signal, the CMOS flip-flop differential amplifier is activated and the potential levels of the output nodes PI and P2 are reliably kept between the reference potential V' and the substrate bias potential Vaa. After the difference is established at a differentially amplified level, the cutoff MOS transistors Q3G and 04G can be turned off.

As a result, the time during which the potential levels of the output nodes PL and P2 reach an intermediate level can be minimized, and the period during which a through current flows through the CMO5-configured flip-flop differential amplifier can be minimized. , it becomes possible to further reduce current consumption, and it is also possible to reliably detect the difference between the reference potential V' and the substrate bias potential VB[1.

FIG. 24 is a diagram showing another example of the configuration of the reference potential generation circuit. Referring to FIG. 24, reference potential generation circuit 720 sets charge pump capacitor CIG receiving inverted oscillation signal φcP and node B5 potential to a value corresponding to the difference between reference potential V' and its own threshold voltage Vt. a p-channel MOS transistor QIOG for clamping the node B5 potential to the ground potential level, a p-channel MOS transistor 09G for clamping the node B5 potential to the ground potential level, and a capacitor and p-channel MOS transistor for controlling the clamping operation of the MOS transistor 09G.
OS transistor Ql 1G and MOS transistor Q
Parasitic capacitance f formed between one conduction region (impurity region) of the IOG and the semiconductor substrate (n-type well region in this example)
including f1c2G. A charge pump capacitor C3G receiving an oscillation signal φcP is coupled to the gate of the MOS transistor 09G. A diode-connected p-channel MOS transistor QIIG is provided between node B6 and the ground potential.

In the configuration of the reference potential generation circuit shown in FIG. 18, the potential of the generated reference potential Vr is -(Vcc-Vt
(9G)-Vt (10G)) (7) level. Here, Vt (9G) and Vt (IOC) are MOS transistor 09G, respectively.

This is the absolute value of the QIOG threshold voltage. therefore,
In the configuration shown in FIG. 18, the potential reached by the reference potential Vr cannot be made smaller than this value, that is, it cannot be made larger in absolute value. However, in the configuration shown in FIG. 24, the value of the reference potential Vr can be set to a lower potential. The operation of the reference potential generation circuit shown in FIG. 24 will be briefly explained below.

Oscillation signal φ. When e is at “H” level, capacitor C3
Due to the capacitive coupling of G, the potential of node B6 tries to rise to H'' level.However, due to the function of MOS transistor QIIG, the potential of node B6 is clamped to the ground potential level of 1Vt(QllG)l. .

Next is the oscillation signal φ.

r goes to "L" level, and the inverted oscillation signal φ (-P goes to °H)
When the level rises, the potential of the node B5 tries to rise to the "H" level, and the potential of the -10,000 node B6 decreases to a negative potential. At this time, the capacitance of the capacitor C3G and the MOS
By setting the respective threshold voltages of the transistors Q11G, the MOS transistor 09G is completely turned on, and the potential level of the node B5 is clamped to the ground potential level. Therefore, when the inverted oscillation signal φcP falls to the "L" level next time, the node 85m becomes -(Vr-
Vt (IOC)) level. When the potential of node B5 decreases, the inverted oscillation signal φcP falls to the "L" level, but at the same time, the oscillation signals φ and P rise to the "H" level, so that despite the clamping operation of the MOS transistor QIIG, Since the potential level of node B6 becomes the threshold voltage level of MOS transistor Q9G, MOS transistor 09G is turned off. Therefore, the potential level reached at node B5 is the above-mentioned value. Therefore, if these oscillation signals φ and P are continuously applied, the potential reached by the reference potential V' is -(Vcc-V
t (10G)).

Now, suppose that the absolute values of the threshold voltages of the MOS transistors Q9G and QIOG are each 1.5V, and the operating power supply voltage Vc.
If c is 5V, in the case of the configuration of the reference potential generation circuit shown in FIG. 18, the reached potential of the reference potential Vr is 12■, whereas in the case of the reference potential generation circuit configured as shown in FIG. In this case, the potential of the base l$ potential Vr can be set to -3.5V.

If the configuration of the reference potential generation circuit shown in FIG. 24 is applied to a substrate bias potential generation circuit, a bias circuit having the configuration shown in FIG. 25 can be obtained.

Referring to FIG. 25, a main bias circuit 110 with a large bias ability includes two stages of cascade-connected inverters 'I'l l + In 2 that receive an oscillation signal φCPM,
Charge pump capacitor C0 coupled to inverter I02 output, inverter I1. l, a charge pump capacitor C0P coupled to the output, and a p-channel MOS transistor Qlffl+Q for generating a reference potential.
2111 Includes Q311. MOS transistor Q,
The gate MOS transistors 09G, QIOG, and QIIG shown in FIG. 24 have the same function and the same connection configuration.

The sub-bias circuit 20 with a small bias capacity includes two stages of cascade-connected inverters IS that receive an oscillation signal φCFS.
l+ lS2, a capacitor C1F that performs a charge pump operation according to the output of the inverter 151, a capacitor C8 that performs a charge pump operation according to the output of the inverter 1g2, and a predetermined level bias in response to the charge pump operation of the capacitors C5 and C5F. P-channel MOS transistor Q+ S+ Qzs that generates potential
, Qs. MOS transistor Q+s+Qzs+
Q3S are MOS transistors Q9G and Q shown in FIG.
It has the same functions as IOG and QIIG, and has the same connection configuration. Therefore, in the case of the configuration of the bias circuit shown in FIG. 25, similarly to the reference potential generation circuit shown in FIG. 24, the substrate bias potential Vaa is set to -(Vcc
-Vt)I: It becomes possible to set. Here, the threshold voltage Vt is the p-channel MOS transistor Q2MIQ
This is the absolute value of the 2S threshold voltage. Therefore, by using this configuration, it becomes possible to bias the semiconductor substrate more deeply, reducing the parasitic capacitance of the semiconductor memory device, stabilizing the threshold voltage of the MOS transistor element, and improving the semiconductor memory device. Reliable and high-speed operation is possible.

Note that in the above embodiment, even if the conductivity type of the MOS transistor included in the substrate bias potential generation circuit is reversed, the same effect as in the above embodiment can be obtained.

Furthermore, in the above embodiment, a NAND gate and a NOR gate are used in the circuit for controlling the oscillation operation of the ring oscillator and switching between bias potential generation circuits with different bias capacities, but each of these gates is different from other gates. Even if a gate structure is used, the same effects as in the above embodiment can be obtained as long as the same logic is realized.

Furthermore, in the above embodiments, a 4M DRAM was shown as an example of the semiconductor memory device, but the capacity of the semiconductor memory device to which the present invention is applied is not limited to this, and the present invention can be applied to a semiconductor memory device of any capacity. Needless to say, it applies.

Furthermore, the refresh interval and the number of refresh cycles performed in self-refresh mode are the same as the standard values (for example, I
M-bit DRAM: 8m51512 cycles, 4MD
RAM: 16m5/1024 cycles, 16MDRA
32m5 / 1024 cycles, etc.), but these values can be set longer than normal values (for example, 4MDR) within the range that does not cause defects in memory cell data.
By setting the value to a value of 32 m s / 2048 cycles, 256 ms / 4096 cycles, etc. in AM, the power consumption during refresh operation can be further reduced. Such lengthening of the refresh interval and reduction of the number of refresh cycles can be achieved by increasing the maximum count value of the refresh address counter 94, or by setting a longer oscillation cycle of the timer 93 that derives the refresh request signal. It is possible.

In addition, in the above embodiment, a timer 923 for generating a refresh instruction signal (in the case of the CAS-before-RAS refresh mode configuration) is used separately from the timer 93 for deriving the refresh request signal, but this configuration uses, for example, a binary counter. It is also possible to share this by using a ring oscillator.

Furthermore, the number of stages of the ring oscillator that derives a signal having a desired oscillation frequency can be set to various appropriate values in order to obtain a predetermined oscillation period.

Further, the same applies to the number of inverter stages for waveform shaping the output signal of the ring oscillator, and these may be deleted depending on the case.

Furthermore, the number of stages of the binary counter used in the timer 93 for deriving the refresh request signal can be varied depending on the purpose.

Furthermore, in the configurations shown in FIGS. 2 to 4, the intermittent operation control signal φ of the substrate bias circuit. , timer 9
For example, the complementary output 01 of the first stage counter of the binary counter in the timer and the true output signal φ1 of the final stage are generated using the oscillation signals φr and φ in the timer. Or the complementary output 02 of the next stage and the output signal φ of the final stage.

If the control signal φC is generated using the following,
It becomes possible to set the pulse width of the control signal φC shown in FIG. 5B to a predetermined value twice or four times longer, respectively. The pulse width of can be appropriately set according to the power consumption and bias capability of the substrate bias potential generation circuit in the semiconductor memory device.

[Effects of the Invention] As described above, according to the present invention, the substrate bias voltage generation circuit is configured to operate only during the period when the semiconductor memory device is operating in each refresh operation cycle in the self-refresh mode. Therefore, unnecessary power consumption can be eliminated, and a dynamic semiconductor memory device with low power consumption can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a block diagram schematically showing the structure of a main part of a dynamic semiconductor memory device according to an embodiment of the present invention. FIG. 2 is a diagram showing an example of the configuration of timer 93 shown in FIG. 1. 3A and 3B are signal waveform diagrams showing the operation of the timer shown in FIG. 2. Figure 4 is the first
2 is a diagram showing an example of the configuration of an intermittent operation control circuit 99 shown in the figure. FIG. 5B is a signal waveform diagram showing the operation of the intermittent operation control circuit shown in FIG. 4. FIG. 6 is a diagram showing an example of the configuration of the substrate bias generation circuit shown in FIG. 1. 7th
This figure shows an example of the configuration of the ring oscillator shown in FIG. 6. FIGS. 8A and 8B show the timing relationship between the word line activation signal and the operation of the substrate via gap generation circuit during the self-refresh cycle.
No. 8 is a diagram showing the operational relationship of the conventional substrate bias voltage generation circuit, and FIG. 8B is a diagram showing the operation timing of the substrate bias voltage generation circuit according to the present invention. FIG. 9 is a diagram showing an example of the configuration of the self-refresh mode detection circuit shown in FIG. 1. FIG. 1O is a diagram showing another example of the configuration of the self-refresh mode detection circuit shown in FIG. 1. FIG. 11 is a signal waveform diagram showing the operation of the self-refresh mode detection circuit shown in FIG. 10. FIG. 12 is a diagram showing another example of the structure of the substrate bias voltage generation circuit shown in FIG. 1. FIG. 13 is a diagram showing an example of the configuration of the substrate bias potential detection circuit shown in FIG. 12. FIG. 14 is a diagram showing an example of the configuration of the switching circuit shown in FIG. 12. FIG. 15 is a signal waveform diagram showing the operation of the switching circuit shown in FIG. 14. FIG. 16 is a diagram showing still another configuration example of the substrate bias potential generation circuit shown in FIG. 1. FIG. 17 is a diagram showing an example of the configuration of the selection control circuit shown in FIG. 16. FIG. 18 is a diagram showing an example of the configuration of the reference potential generation circuit shown in FIG. 17. FIG. 19 is a diagram showing the relationship between the semiconductor substrate to which the reference potential of the reference potential generation circuit shown in FIG. 18 is applied and the substrate bias potential is applied. FIG. 20 is a signal waveform diagram showing the operation of the selection control circuit shown in FIG. 17. FIG. 21 is a diagram showing still another example of the configuration of the selection control circuit shown in FIG. 16. Figure 22 is the second
2 is a diagram showing an example of the configuration of a flip-flop shown in FIG. 1. FIG. FIG. 23 is a diagram showing an example of the configuration of the buffer circuit shown in FIG. 21. FIG. 24 is a diagram showing another example of the configuration of the reference potential generation circuit shown in FIGS. 17 and 21. FIG. 25 is a diagram showing still another configuration example of the bias circuit shown in FIGS. 12 and 16. FIG. 26 is a diagram schematically showing the configuration of the main parts of a conventional semiconductor memory device. FIG. 27 is a diagram showing a configuration example of a substrate bias voltage generation circuit used in the semiconductor memory device shown in FIG. 26. FIG. 28 is a signal waveform diagram showing the operation of the substrate bias voltage generation circuit shown in FIG. 27. In the figure, 91 is a self-refresh mode detection circuit, 92 is a refresh control circuit, 93 is a refresh request signal generation timer, 94 is a refresh address counter, 95 is an address switching circuit, 97 is a memory array,
99 is an intermittent operation control circuit, 100 is a substrate bias voltage generation circuit, 110 is a main bias circuit with a large bias capacity, 120 is a sub bias circuit with a relatively small bias capacity, 150 is a semiconductor substrate, and 511 is a substrate bias voltage generation circuit. The included ring onlator 600 is a switching circuit for switching bias circuits with different bias capacities, 6
10 is a substrate potential detection circuit; 700 is a selection control circuit for selectively activating bias circuits having different bias capacities; 700' is a circuit for generating a signal for selectively switching bias circuits having different bias capacities; 720 is a basic I$ potential generation circuit, 730 is a substrate potential detection circuit having high human power impedance, 740 is a comparison circuit, and 760 is a buffer circuit. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Scope of Claims] A semiconductor memory device having a function of automatically refreshing memory cell data in response to an external refresh instruction signal, the semiconductor memory device being formed on a semiconductor substrate, means for generating an internal refresh instruction signal in response to the external refresh instruction signal; means for refreshing the memory cell data; and generating a signal for activating the refresh means in response to the internal refresh instruction signal. means for generating the activation signal periodically at predetermined intervals while the internal refresh signal is in an active state to activate the refresh means and bias the semiconductor substrate to a predetermined potential; A dynamic semiconductor memory device with a built-in refresh function, comprising means for activating the bias means for a shorter time than the time that the activation signal is in an active state in response to a refresh instruction signal and the activation signal.