JPH0218783A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To reduce the average operating current of a substrate back bias voltage generating circuit by selectively causing the substrate back bias voltage generating circuit, whose operation is selectively stopped, to go to an operating condition according to the coupling of an activation control signal and specifying a period, during which the operation is stopped, as user specification. CONSTITUTION:In the prescribed coupling of the activation control signal, the operation of a built-in substrate back bias voltage generating circuit VBBG is selectively stopped and this circuit is caused to go to the operating condition according to the coupling of the activation control signal. Then, the period, during which the operation is stopped, is specified as the user specification. Accordingly, the operation of the built-in substrate back bias voltage generating circuit VBBG can be intentionally stopped in a range that a trouble is not generated in the operation of a dynamic type RAM. Thus, the average operating current of the substrate back bias voltage generating circuit can be reduced at a standby time.

Description

[Detailed description of the invention]

(Industrial Application Field) This invention relates to a semiconductor memory device, for example,
The present invention relates to a technique that is particularly effective for use in dynamic RAM (random access memory) and the like that incorporate a substrate back bias voltage generation circuit. [Prior Art] In a dynamic RAM, etc. whose basic configuration is a MOSFET (insulated gate field effect transistor), the voltage between the semiconductor substrate and each circuit element is improved by applying an appropriate substrate back bias voltage to the semiconductor substrate. There are known methods for controlling parasitic capacitance and stabilizing operation. In addition, a dynamic/retype RAM incorporating a substrate back bias voltage generation circuit for forming the substrate back bias voltage.
has already been developed. Regarding dynamic RAM with a built-in substrate back bias voltage generation circuit, for example, Japanese Patent Application Laid-Open No.
It is described in the No. 688 publication. [Problems to be Solved by the Invention] FIG. 4 shows a circuit diagram of a substrate back bias generation circuit developed by the inventors of the present invention prior to the present invention. In the same figure, the substrate back bias voltage generation circuit V
aIIG includes two voltage generation circuits VGI and VO2. Among these, the voltage generating circuit VGI is designed to maintain or temporarily recover the level when the dynamic RAM is selected or when the absolute value of the substrate back bias voltage VBB falls below a specified value. It is designed to have a relatively large current supply capacity. Then, it is selectively brought into operation according to the timing signal φr1 generated in the selected state of the dynamic RAM or the output signal n5 of the level detection circuit LVM that monitors the substrate back bias voltage van. On the other hand, the voltage generation circuit VG2 has a relatively small current supply capacity that can compensate for leakage current to the substrate and supply the operating current of the level detection circuit LVM when the dynamic RAM is in a non-selected state. Designed to be. The dynamic RAM is always kept in an operating state regardless of the selected state. In this way, by selectively activating the voltage generating circuit VGI, which requires a relatively large operating current, the average operating current of the substrate back bias generating circuit is suppressed, and the power consumption of the dynamic RAM is reduced. is planned. The inventors further provide a battery buffer. We have developed an ultra-low power consumption dynamic type RAM that can be used in applications such as electronic devices, and we have taken advantage of using a substrate back bias voltage generation circuit as shown in FIG. 4 in this ultra-low power consumption dynamic type RAM. However, in the substrate back bias voltage generation circuit, as described above, while the dynamic RAM is in the non-selected state, the level detection circuit LVM
is in a steady state of operation. For this reason, even though the leakage current to the board itself is extremely small, the level detection circuit! ,, Since it is necessary to supply the operating current of VM, the voltage generating circuit VG2 has to be in a steady operating state, and the substrate back bias voltage vea
When a drop in the level of VGI is detected, the voltage generating circuit VGI
This increases the operating current of the substrate back bias voltage generation circuit during standby, which is one factor that limits the reduction in power consumption of ultra-low power consumption dynamic RAM. becomes. An object of the present invention is to provide a dynamic type RA capable of selectively stopping the operation of a built-in substrate back bias voltage generation circuit.
Another object of the present invention is to provide a semiconductor memory device such as M, etc., which reduces the average operating current of the built-in substrate back bias voltage generation circuit, and has ultra-low power consumption that can be used for battery bank up, etc. The objective is to realize dynamic type RAM and the like. The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings. [Means for Solving the Problems] A brief overview of typical inventions disclosed in this application is as follows. That is, in a predetermined combination of activation control signals,
It is possible to selectively stop the operation of the built-in substrate back bias voltage generation circuit, and the period during which the substrate back bias voltage generation circuit is brought into operation according to the combination of the activation control signals and its operation is stopped can be set according to user specifications. It is stipulated as follows. [Function] According to the above-described means, the operation of the built-in substrate back bias voltage generation circuit can be intentionally stopped within a range that does not interfere with the operation of the dynamic RAM. As a result, it is possible to reduce the average operating current of the substrate back bias voltage generation circuit during standby, so that it is possible to realize an ultra-low power consumption dynamic RAM that can be used in battery baths, etc. [Example] Fig. 2 shows a dynamic type RA to which this invention is applied.
A block diagram of an embodiment of M is shown, and the circuit elements constituting each block in the figure are not particularly limited by known semiconductor integrated circuit manufacturing techniques, but are made of single crystal silicon such as single crystal silicon. Formed on a semiconductor substrate. The dynamic RAM of this embodiment includes a substrate back bias voltage generating circuit V B8 G that receives the power supply voltage of the circuit and forms a predetermined substrate back bias voltage VilB. Substrate back bias voltage generation circuit V B, G
As will be described later, in this embodiment, the voltage generation circuit VGI and VO2 include a voltage generation circuit VGI having a relatively large current supply capacity and a voltage generation circuit VG2 having a relatively small current supply capacity. Although not particularly limited, the row address supplied as the activation control signal is

[/
It is selectively activated according to the combination of the column address strobe signal pressure π and the column address strobe signal ■. That is, the electric field generation circuits VGI and VO2 are activated when the row address strobe signal ■ is set to low level, regardless of the level of the column address strobe signal ■, and when the row address strobe signal ■ is set to the low level and the column When the address strobe signal ■ is set to low level, its operation is stopped. Further, when both the row address strobe signal Rτ1 and the column address strobe signal ■ are set to a high level, the voltage generating circuit VG1 is selectively put into an operating state when the level of the substrate back bias voltage becomes below a specified value, Voltage generating circuit VG2 is brought into operation regardless of the level of the substrate back bias voltage. In other words, the substrate back bias voltage generation circuit uses the row address strobe signal RA.
By setting a predetermined combination of S and column address strobe signal ξX1, the operation is selectively stopped. In this embodiment, the period during which the substrate back bias voltage generation circuit is activated or deactivated is defined as a user specification based on test results of dynamic RAM. As a result, the dynamic type R
An AM user can stop the operation of the substrate back bias voltage generation circuit and manage and suppress its operating current within a range that does not interfere with the operation of the dynamic RAM. In Figure 82, the memory array MARY includes a plurality of word lines arranged in parallel in the vertical direction of the figure, a plurality of complementary data lines arranged in parallel in the horizontal direction of the figure, and these word lines. and a plurality of dynamic memory cells arranged in a grid pattern at the intersections of complementary data lines. The word lines constituting the memory array MARY are coupled to a row address decoder RAD and are selectively brought into a selected state. Although not particularly limited, the row address decoder RAD receives 1←1 bit complementary internal address signals axO to axi (here, for example, a non-inverted internal address signal axQ and an inverted internal address signal a) from the row address buffer RAB.
XO is also expressed as a complementary internal address signal aXO. The timing signal φX is supplied from the timing generation circuit TG. The row address decoder RAD is selectively put into an operating state at the above-mentioned timing (No. The row address decoder RAB supplies the row address signal transmitted from the address multiplexer AMX from the timing generation circuit TO. Also, based on these row address signals, the complementary internal address signals xO to xi are formed and fed to AD by the row address decoder 1.Address multiplexer Although not particularly limited, when the dynamic RAM is in the normal operation mode and the low-level timing signal φrsf is supplied from the timing generation circuit '1'G, AMX is supplied in a time-divisional manner via the external terminals AO to Ai. X address signal AXO~AX
i is selected and transmitted to the row address buffer RAB as the row address signal. In addition, dynamic RA
M is in refresh mode and the timing signal φr
When ef is set to high level, the refresh address signal arc-art@ supplied from the refresher address counter RFC is selected and transmitted to the row address buffer RADB as the row address signal. Although not particularly limited, the refresh address counter RFC performs an increment operation according to the timing signal φ'C supplied from the timing generation circuit TG when the dynamic RAM is in the refresh mode. . . The sense amplifier SA includes a plurality of unit amplifier circuits provided corresponding to each complementary data line of the memory array MARY, and these unit amplifier circuits include a timing generation circuit TG.
A timing signal φpa is commonly supplied from. Each unit amplifier circuit of the sense amplifier SA is selectively put into an operating state by setting the timing signal φpa to a high level. In this operating state, each unit amplifier circuit amplifies the minute read signal output from the plurality of memory cells coupled to the selected word line of the memory array MARY via the corresponding complementary data line, and amplifies the minute read signal to a high level or It is a low level binary read signal. The column switch C8W is a plurality of pairs of switches MO provided corresponding to each complementary data line of the memory array MARY.
One of these switches MO3FET, including S FET, is coupled to the corresponding complementary data line of the memory array MARY, respectively, as described above, and the other is connected to the non-inverting signal line CD and the inverting signal line of the complementary common data line. They are alternately commonly coupled to lines CD. The gates of each pair of switches MO3FET are commonly coupled, and the corresponding data line jM signal is supplied from the column address decoder CAD. The switch MO5FET of each pair of the column switch C3W is selectively turned on when the corresponding data line selection signal is selectively set to a high level. the result,
The corresponding complementary data line of the memory array MARY is connected to the complementary common data line CD. The column address decoder CAD is supplied with the complementary internal -7 address signal ayO-ayi of the l+1 pin from the column address buffer CAB, and is supplied with the timing signal φy from the timing generation circuit TG, although this is not particularly limited. The column address decoder CAD is selectively brought into operation by the timing signal φy being set high to low. In this operating state, the column address decoder CAD detects the complementary internal address (δ ayQ-
ayi is decoded and the corresponding data IJit selection signal is alternatively set to high level. These data line selection signals are each supplied to the corresponding switch MO5FET of the column switch C8W, as described above. Column address buffer CAB connects external terminals AO to Ai
Y address signal AYO- supplied in a time-division manner via
A'yl is taken in and held in accordance with the timing signal φac supplied from the timing generation circuit TG. Also, based on these Y address signals, the complementary internal address signals ayO to ayl are formed and supplied to the column address decoder CAI]. Complementary common data lines CD-CD are coupled to data input/output circuit I10, although not particularly limited thereto. The data input/output circuit 110 includes, but is not particularly limited to, a data manual buffer and a data output buffer. Among these, the input terminal of the data manual buffer is coupled to the data input terminal Din, and its output terminal is connected to the complementary common data!
Combined with JilCD-CD. The data manual buffer is supplied with a timing signal φW from the timing generation circuit TG. On the other hand, the input terminals of the data output buffers are commonly coupled to the complementary common data lines CD-CD, and the output terminals thereof are coupled to the data output terminal Dout. The data output buffer is supplied with a timing signal φr from the timing generation circuit TO. The data manual buffer of the data input/output circuit I10 is selectively brought into operation when the dynamic RAM is set to the synchronization mode and the timing signal φW is set to a high level. In this operating state, the data manual buffer forms a complementary write signal according to the write data supplied via the data input terminal Din, and transfers the complementary write signal to the memory array MA via the complementary common data InjCD-CD.
RY is supplied to the selected memory cell. Although not particularly limited, when the timing signal φW is set to a low level, the output of the data manual buffer is set to a high impedance state. The data output buffer of the data input/output circuit I10 is selectively brought into operation when the dynamic RAM is placed in the read mode and the timing signal φr is set to a high level. In this operating state, the data output buffer connects the selected memory cell of the memory array MARY to the corresponding complementary data line and complementary common data line CD-
The binary read signal outputted via τ is further amplified and sent from the data output terminal [) out. Although not particularly limited, when the timing signal φr is set to the l:l low level, the output of the data output buffer is placed in a high impedance state. As mentioned above, the dynamic RAM of this embodiment is
Built-in substrate back bias voltage generation circuit VASC. Although not particularly limited, the substrate back bias voltage generation circuit VBOG receives timing signals φ'1 and φC1 and an inverted internal control signal y from the timing generation circuit TG.
bt is supplied. Here, the timing signal φr1 is
Although not particularly limited, when the row address strobe signal (2) is set to a low level, it is selectively set to a high level. In addition, Taimini Puffer (No. 8-C1) is selectively set to a high level when the column address strobe signal (■) is set to a low level.Furthermore, the inverted internal control signal Vbt is normally set to a high level, although not particularly limited. The test control signal -f is set to low level and the dynamic type R
When AM is placed in the substrate back bias voltage test mode, it is selectively set to a low level. As described later, the substrate back bias voltage generation circuit V Be G forms a substrate back bias voltage VBill, which is a predetermined negative voltage, based on the power supply voltage of the circuit,
Supplied to the semiconductor substrate of dynamic RAM. As a result, the parasitic capacitance value existing between the semiconductor substrate and each circuit element is controlled by 9J, and the operation of the dynamic RAM is stabilized. In this embodiment, the substrate back bias voltage generation circuits VB, . These voltage generation circuits, including the timing signals φ'1 and φc
According to No. 1, predetermined combinations are selectively activated. Further, when the inverted internal control signal vbt is set to a low level, the operation is selectively stopped. This makes it possible to test the operating characteristics of the Dyna type RAM without supplying the substrate back bias voltage VBB.For the specific circuit configuration and operation of the substrate back bias voltage generation circuit VB8G , which will be explained in detail later.The timing generation circuit TG generates the above-mentioned signals based on the row address strobe signal qRAs, the column address strobe signal ■, the write enable signal WE, and the test control signal VBT, which are supplied as activation control signals from the outside. Forms various timing signals and internal control signals and supplies them to each circuit of the dynamic RAM. Fig. 81 is a circuit diagram of an embodiment of the substrate back bias voltage generation circuit V B8 G of the dynamic RAM shown in Fig. gJ12. In addition, FIG. 3 shows a timing diagram of an embodiment of the substrate back bias voltage generation circuit V an G of FIG. 1. According to these diagrams,
Substrate back bias voltage generation circuit van of this embodiment
An outline of the specific circuit configuration and operation of c. In addition, in Figure 81, the MOSFET whose channel (back gate) part is marked with an arrow is a P-channel type.
It is shown to distinguish it from an N-channel MO8FET without an arrow. Further, FIG. 3 exemplarily shows three memory cycles Cy,l to Cy,3 that are executed continuously, among which the dynamic RAM is
, x and cy, 2 are in refresh mode 11 before - cycle Cv. 3, the normal write mode or read mode is set. In the figure, the oscillation circuit control signal ocl and the pulse signal φ1 are indicated by dotted lines while the voltage generating circuit VGI of the substrate back bias voltage generating circuit is selectively activated according to the level of the substrate back bias voltage Vaa. In FIG. 1, the substrate back bias voltage generation circuit V
se, G are voltage generating circuits VGI (although not particularly limited) designed to have a relatively large current supply capability.
(first voltage generation circuit), an oscillation circuit 03CI and a level detection circuit LVM provided corresponding to the voltage generation circuit VGL. It also includes a voltage generation circuit VG2 (second voltage generation circuit) designed to have a relatively small li current supply capability, and a generator circuit 03C2 provided corresponding to this voltage generation circuit VG2. Although not particularly limited, the level detection circuit LVM is a P-channel MO3FETQ provided in series between the circuit power supply voltage and the substrate back bias voltage vita.
, L and N channel MOS FET Q
The above-mentioned timing signal - from the timing generation circuit TO is applied to the gate of MOSFET QI including MOSFET ll and Q12.
01 is supplied. Moreover, MOSFETQII has its gate coupled to the ground potential of the circuit, and MOSFETQII
2 is formed into a diode form by having its gate and drain commonly coupled, and the commonly coupled drains of MOSFETQI and Qll, that is, the node n1, is a P-channel MO3FETQ2.
and an input terminal of an inverter circuit consisting of an N-channel MO3FETQ13. The output terminal of this inverter circuit is coupled to the input terminal of the inverter circuit N1 and to the power supply voltage of the circuit via a P-channel MO3FETQ3. The output signal of the inverter circuit Nl is the output signal n2 of the level detection circuit L V M, and is supplied to one input terminal of the Nant gate circuit NAGI, and is also supplied to the gate of the MO3 FET Q3. As shown in FIG. 3, the row address strobe signal positive τ1 is set to a low level, thereby selectively bringing it into a selected state. timing signal φ
When the dynamic type RAM is in the selected state, the column address strobe signal στ1 is selectively set to a high level by the row address strobe signal
When the AM is in the normal operation mode, it is set to low level with a slight delay after the upper row address strobe signal ■, and when the dynamic RAM is set to the ■before ■ refresh mode, it is set to the low level before the row address strobe signal ■. be done. When the dynamic RAM is in a non-selected state, the column address strobe signal
Meat is intentionally kept at a high level or a low level for a predetermined period of time for reasons described later. The timing signal φ01 is selectively set to a high level when the column address strobe signal ① is set to a low level. The column address strobe signal ■ is set to high level,
When the timing signal φcl is set to low level, the first
In the level detection circuit LVM of the substrate back bias voltage generation circuit shown in the figure, MO3FETQ1 is turned on. Therefore, the level detection circuit LVM is brought into operation and performs a level determination operation of the substrate back bias voltage V8B. That is, the absolute value of the substrate back bias voltage vea is
These MOs become smaller than the composite threshold voltage of
3FET QI 1 and Q12 are turned off. Therefore, the potential of the node n1 becomes high level, almost like the power supply voltage of the circuit, and the MOS FETQ2 and Q
The output signal of the inverter circuit consisting of 13 is set to low level. As a result, the output signal of the inverter circuit Nl, that is, the output signal n2 of the level detection circuit LVM becomes high level. In addition, the output signal n of the level detection circuit LVM
2 is set to high level, MO3FETQ3 is turned off, and the logic threshold level of the inverter circuit made up of MO3FETQ2 and Q13 is slightly lowered. On the other hand, when the absolute value of the substrate back bias voltage Vee17) becomes larger than the combined threshold voltage of the MO3FETs QI1 and Q12, both of the MO3FETs QII and Q12 are turned on. Therefore, the potential of the node n1 becomes a predetermined low level determined by the ratio of the conductance of the MOS FETQl and the combined conductance of the MO3FETQI1 and Q12. Here, the low level of the node n1 is MOS FET
It is designed to be lower than the logic threshold level of the inverter circuit consisting of Q2 and Q13. Therefore, the output signal of the inverter circuit consisting of MO3FETQ2 and Q13 becomes high level. As a result, the output signal of the inverter circuit N1, that is, the output signal n2 of the level detection process LVM becomes low level. Further, by setting the output signal n2 of the level detection circuit LVM to a low level, the MO3FETQ3 is turned on, and the logic threshold level of the inverter circuit made up of the MO3FETQ2 and Q13 is slightly increased. When the column address strobe No. 5 (2) is set to a low level and the timing signal φ01 is set to a high level, the MO3FETQI of the level detection circuit LVM is turned off. As a result, the level detection circuit LVM is rendered inactive, and the detection current flowing into the substrate back bias voltage common point VI3B via the MO3FETs QII and Q12 is completely cut off. In other words, in the substrate back bias voltage generation circuit V B8 G of this embodiment, the level detection circuit LVM is selectively brought into the operating state by setting the column address strobe signal ■ to a high level and setting the timing signal φcl to a low level. be done. In this operating state, the level detection circuit LVM detects that the substrate back bias voltage Vse decreases due to leakage, etc., and its absolute value
and Q12, the output signal n2 is selectively set to a high level. In addition, in the level detection process of the level detection circuit LVM, the logic threshold level of the inverter circuit consisting of MO3FETQ2 and Q13 is determined by the level detection circuit LVM.
is selectively made low or high according to the output signal n2 of. Therefore, the level detection circuit LVM has a hysteretic level determination characteristic, and its operation is stabilized. The other input terminal of the Nant gate circuits NA and G1 is supplied with an inverted signal of the timing signal φci by the inverter circuit N2, that is, an inverted timing signal φcl. As a result, the output signal n3 of the Nant gate circuit NAG1 has a level when the inverted timing signal φcl is set to a high level, or in other words, when the timing signal φcl is set to a low level and the level detection circuit LVM is selectively activated. By setting the output signal n2 of the detection circuit LVM to a high level, the output signal n2 is selectively set to a low level. When the level detection circuit LVM is activated and its output signal n2 is brought to a low level, or when the level detection circuit LVM is deactivated, the output signal n3 of the Nant gate circuit NAG1 is brought to a high level. The output signal n3 of the Nant gate circuit NAG1 is supplied to one input terminal of the Nant gate circuit NAG2, although this is not particularly limited. This Nant gate circuit NAG2 (
The 11th input terminal is supplied with an inverted signal of the timing signal φr1 by the inverter circuit N3, that is, an inverted timing signal φrl. As a result, the output signal n4 of the Nant gate circuit NAG2 becomes the output signal n4 of the Nant gate circuit NAG2.
AGI output signal n3 or the above inverted timing signal φr
When any one of l is set to low level, it is selectively set to high level. Although not particularly limited, the output signal n4 of the Nant gate circuit NAG2 is supplied to one input terminal of the Nant gate circuit NAG3. The above-mentioned inverted internal control signal vbL is supplied to the other input terminal of this Nant gate circuit NAG3. The output signal of the Nant gate circuit NAG3 is inverted by the inverter circuit N4, and the output signal of the oscillation circuit control signal o is inverted by the inverter circuit N4.
cl is commonly supplied to the other input terminal of the Nant gate circuits NAG4 and NAG5 forming the oscillation circuit 05CI. As a result, the output (membrane circuit control signal ocl is
When the output signal n4 of the Nant gate circuit NAG2 is set to high level, that is, when the level detection circuit LVM is activated and its output signal n2 is set to high level, or when the dynamic RAM is set to the selected state and the timing signal When φrl is set to a high level, it is selectively set to a high level on the condition that the inverted internal control signal vbt is at a high level. In other words, as shown in FIG. 3, the oscillation circuit control signal oci (1) row address I/lobe signal ■ is set to low level, and the dynamic RAM is set to the selected state, so that the timing signal φrl is (2) When the column address strobe signal ■ is set to high level, the substrate back bias voltage generation circuit V,
When the 13G level detection circuit LVM is activated and the absolute value of the substrate back bias voltage VIIB becomes smaller than the specified value, that is, the composite threshold voltage of MO3FETQII and Q12, the inversion internal side a (δ signal Vbt is high) level.In other words, the oscillation circuit control signal ocl is selectively set to high level.
(110 When the row address strobe signal (■) is at high level and the column address strobe signal (■) is at low level, (2) When the row address strobe signal (RAS) and the column address strobe signal (■) are both at high level and the When the absolute value of the back bias voltage VBB is larger than the specified value, that is, the composite threshold voltage of MOS FET Q11 and Q12, (3) the dynamic RAM is put into the substrate back bias voltage test mode and the above-mentioned inverted internal control signal When vbt is set to a low level, it is fixed to a low level.The oscillation circuit osct includes, but is not particularly limited to, three inverter circuits N5 to n7 in series and two Nant gate circuits NAG4 and NAG5. The output terminal of the Nant gate circuit NAG5 is the inverter circuit N5.
is connected to the input terminal of Also, the Nant gate circuit NA
As described above, the oscillation circuit control signal ocl is supplied to the other input terminals of G4 and NAG5. This results in
Inverter circuits N5 to N7 and Nant gate circuit N
AG4 and NAG5 function as one ring oscillator on the condition that the oscillation circuit control signal ocl is at a high level. At this time, the oscillation frequency of the oscillation circuit 03CI is made relatively high, for example, 4M (mega) Hz. After the driving force of the output signal of the Nant gate circuit NAG4 is gradually increased by an even number of inverter circuits N8 to N9 connected in series, the output signal of the oscillator circuit O3CI, that is, the pulse signal φl, is sent to the voltage generating circuit VGI.
is supplied to The voltage generating circuit VGI has a basic configuration including a boost capacitor C1 designed to have a relatively large capacitance. The oscillation circuit 03C is connected to one bridge of the boost capacitor C1.
The pulse signal φ1 is supplied through the 1 to N channel MO3FETQIG. The gate of the MO5FET QI 6 is coupled to a predetermined constant voltage VL via N-channel MO3FETs Q14 and Q15, which are arranged in parallel, although this is not particularly limited. Gorera's MO3FETQ1
4 and Q] and 5 have their gates and drains commonly coupled so that they have diode characteristics in opposite directions. Therefore, the gate voltage V of MO3FETQ16
gffl is clamped in the range of VL-VtH14<Vg16<VL+VyH+s, where the threshold voltages of MO3FETQI4 and Q15 are VTold and VTHIs, respectively. As a result, it is possible to prevent the substrate back bias voltage van from reaching an abnormal level due to fluctuations in the power supply voltage of the circuit. Between the other electrode of the boost capacitor CI and the substrate back bias voltage supply point van, a diode-shaped N
A channel MO3FET Q17 is provided. Moreover, between the other electrode of this boost capacitor C1 and the ground potential of the circuit, there is an N-channel M which is also in the form of a diode.
O3FETQI8 is provided. Here, MO3FET
QI7 and Q18 are designed to have approximately the same threshold voltage VTH. MO5FETQI7 is selectively turned on when the potential of the other N pole of the boost capacitor C1 becomes lower than the substrate back bias voltage VBB by the threshold voltage, and MO3FETQ18 is turned on when the potential of the other N pole of the boost capacitor C1 becomes lower than the substrate back bias voltage VBB by the threshold voltage. When the potential becomes higher than the ground potential of the circuit by more than the threshold voltage, it is selectively turned on. The pulse signal φ1 is set to high level and the boost capacitor 9C
When one electrode of the boost capacitor NC1 is set to a high level, a high level is induced in the other aS of the boost capacitor NC1 due to its charge pump action. However, at this time, M.O.
Since 3FET QI 8 is turned on, its level is clamped to the threshold voltage VTH of MO3FET Q1B. On the other hand, when the pulse signal φ1 changes to low level, the potential of the other electrode of the boost capacitor 11c1 decreases by the circuit ii source voltage VCC and becomes -(Vcc-VTH). Therefore, the substrate back bias voltage VBB is a voltage higher than the potential of the other electrode of the boost capacitor C1 by the threshold voltage VTH of MO3FET Q17, that is, −(Vcc −
2X V rH). As described above, the boost capacitor 1icl provided in the voltage generating circuit VGI is designed to have a relatively large capacitance. Therefore, due to the charge pump action of the boost capacitor 1ic1, the substrate back bias voltage supply point v
The amount of charge transferred to BB is a relatively large value. As a result, voltage generating circuit VGI has a relatively large current supply capability. By the way, in the oscillator circuit osci, as mentioned above, when the oscillation circuit control signal ocl is set to high level, that is, when the column address strobe signal [100] is set to high level, the level detection circuit LVM is activated. When the absolute value of the substrate back bias voltage VUa becomes equal to or less than the specified value, or when the row address strobe signal (■) is set to low level, the Guinami-no-K type RAMA (selected state is selectively brought into operation state). Furthermore, as described above, the column address strobe signal (2) is selectively set to a high or low level according to a predetermined condition while the row address strobe signal (2) is set to a high level and the dynamic RAM is in a non-selected state. By increasing the current supply capability of the voltage generating circuit vGl, the level of the substrate back bias voltage vBB is quickly recovered, and in the selected state of the dynamic RAM where the level fluctuation is relatively large, the substrate back bias voltage The level of V813 is maintained stably.Furthermore, when the dynamic RAM is set to a non-selected state, the column address strobe signal ■ is selectively set to a low level, so that the voltage generating circuit VGI is selectively set to a low level. Its operation is stopped, and the operating current of the substrate back bias voltage generation circuit V Bfl G is suppressed. On the other hand, the oscillation circuit 05 provided corresponding to the voltage generation circuit VG2 of the substrate back bias voltage generation circuit V B8 G
Like the oscillation circuit 03CI, C2 includes 4 (11i1) inverter circuits NIL to N14 connected in series and one Nant gate circuit NAG 8.The output terminal of the inverter circuit 1i!8N14 is connected to the inverter circuit NIL.
is coupled to the input terminal of il. In addition, the other input terminal of the Nant gate circuit NAG8 is connected to an inverter circuit NIO.
The output (i.e., the oscillation circuit control signal oc2) is supplied. As a result, the inverter circuits Nll to N14 and the Nant gate circuit NAG8 are set to 1 on the condition that the oscillation circuit control signal oc2 is high L/bell. functions as a ring oscillator.At this time, the oscillation circuit 0
The oscillation frequency of 3C2 is made relatively low, for example I MHz. The input terminal of the inverter circuit NIO is coupled, although not particularly limited, to the output terminal of the Nandt gate circuit NAG7. One input terminal of this Nantes gate circuit NAG7 is supplied with the output signal of the Nantes gate circuit NAG6, and the other input terminal is supplied with the above-mentioned inverted internal control signal v.
bt is supplied. One input terminal of the Nant gate circuit NAG6 is supplied with the above-mentioned inverted timing signal φr1, and the other input terminal is supplied with the above-mentioned timing signal φC.
1 is supplied. From these facts, the output signal of the inverter circuit NIO, that is, the oscillation circuit control signal oc2, is the output signal of the Nandt gate circuit N.
When the output signal of AG6 is set to high level, that is, when either the inverted timing signal φr1 or the timing signal φC1 is set to low level, in other words, as shown in FIG.
When the fi No. TF 7゜go is set to low level, the dynamic RAM is put into the i selection state and the timing signal φr is set to the low level.
When 1 is set to high level, or when column address strobe signal τ11 is set to high level and timing signal φc1 is set to low level, on the condition that inverted internal control signal vbt is at high level, 1 is set to high level. It is considered to be a high level. As a result, the oscillation circuit 03C2 becomes
It is selectively activated according to these conditions. In other words, the operation of the Q type circuit 03C2 is selectively stopped when the row address strobe signal (2) is set to high level and the column address strobe signal (2) is set to low level. The output signal of the inverter circuit 113N14 is gradually increased in driving power by an even number of inverter circuits 815 to N16 connected in series, and then outputted to the voltage generation circuit V as the output signal of the oscillation circuit 03C2, that is, the pulse signal φ2.
Supplied to G2. Voltage generation circuit VG2 includes two charge pump circuits each having boost capacitances C2 and C3 as their basic configurations, although this is not particularly limited. Of these, the output signal of the NOR gate circuit N0G1, ie, the pulse signal φ3, is supplied to the charge pump circuit whose basic configuration is the booth 1 and the capacitor C2. noah gate episode 1
2! One input terminal of N0GI is connected to the above Q oscillation circuit ○S.
A pulse signal φ2 is supplied from C2, and the delay f! of the pulse No. 1J φ2 is supplied to the other input terminal. A delayed signal, ie, a pulse signal φ2d, by the l-path DL is supplied. On the other hand, the charge pump circuit whose basic configuration is the boost capacitor C3 is supplied with an inverted signal of the output signal of the NAND game circuit N and AG9 by the inverter circuit N21, that is, a pulse signal φ4. Nant gate circuit NAG9
The pulse signal φ2 is supplied to one input terminal of the 441 input terminal, and the pulse signal φ2 is supplied to the 441st input terminal of
d is supplied. Although the delay circuit DL is not particularly limited, the above-mentioned pulse tr
The circuit includes an inverter circuit N17 receiving the signal φ2, a capacitor C4 provided between the output terminal of the inverter circuit N17 and the ground potential of the circuit, and three inverter circuits N18 to N20 connected in series. As shown in FIG. 3, the NOR gate circuit N. The output signal of Gl, that is, the pulse (R number φ3) is selectively set to high level when the pulse signals φ2 and φ2d are both set to low level. Also, the output signal of the inverter circuit N21, that is, the pulse signal ψ4 is selectively set to high level when the pulse signals φ2 and φ2d are both set to high level.In other words, pulse signals φ3 and φ4 are complementary pulse signals that are not set to high level at the same time. The pulse signal φ3 is not limited to 'yI, but the pulse signal φ3 is
) through the MO3FET Q21
is supplied to one electrode of 2. The voltage generating circuit VGI is connected between the gate of MO3FE GoQ21 and the constant voltage VL.
According to the same article, N channel MO3l"ETQ19 and Q2
A clamp circuit consisting of 0 is provided. Boost capacity 31
The other electrode of c2 and the substrate back bias voltage supply point V8
An N-channel MO3FETQ22 is provided between the MO3FETQ22 and the MO3FETQ22. Further, between the other 1s pole of the boost capacitor lc2 and the ground potential of the circuit, there is an N-channel MO in the form of a diode.
A 3FETQ23 is provided. Similarly, pulse No. 14 φ4 is an N-channel MO3FE
It is supplied to one electrode of the boost capacitor C3 via TQ26. Between the gate of MO3FETQ26 and constant voltage VL, N-channel MO3FE'rQ24 and Q2
A clamp circuit consisting of 5 is provided. Boost capacity C
3 and the substrate back bias voltage supply point VI3
+3, an N-channel MOS FETQ27 in the form of a diode is provided. In addition, between the 4th electrode of the boost capacitor JiC3 and the ground potential point of the circuit, there is an N-channel MO3FE in the form of a diode.
TQ28 is provided. The other electrode of the boost capacitor C3 is further commonly coupled to the gate of the MO3FETQ22. Here, the boost capacitance NC2 is the voltage generating circuit VGI
The boost capacitor ic3 is designed to have a smaller capacitance than the boost capacitor NcI provided in the boost capacitor 1c2, and the boost capacitor ic3 is designed to have an even smaller capacitance than the boost capacitor 1c2. Also, MOS FET Q22 and Q
23, Q27 and Q28 are the voltage generating circuit V
GI MO3FET Q1? It is designed to have approximately the same threshold voltage VTH as Q18. The charge pump circuit whose basic configuration is the boost capacitor @C3 operates in the same way as the voltage generating circuit vci described above, and the MO
What is the drain potential of 3FETQ27? The four-plate back bias voltage V8B acts to become -(Vcc-2×V). On the other hand, in the charge pump circuit whose basic configuration is the boost capacitor 31c2, when the pulse signal φ3 is set to low level, the potential of the other electrode of the boost capacitor 11c2 becomes -(VCC-VTR), and at the same time, the pulse signal φ4 becomes high level. When the potential of the other electrode of the boost capacitor C3 becomes +VTH due to
10 is selectively turned on, and acts so that the value of the substrate back bias voltage VBB becomes -(Vce-Vtu). As described above, the boost capacitor C2 is designed to have a larger capacitance than the boost capacitor C3. Therefore, when the dynamic RAM is in a non-selected state and only the voltage generating circuit VC2 is in an operating state, the value of the substrate back bias voltage VBB is -(Vee-VT).
l). When the dynamic RAM is in a non-selected state and only the voltage generating circuit VG2 having a relatively small current supply capacity is in an operating state, a substantially constant leak current flows through the substrate of the dynamic RAM. Therefore, the absolute value of the substrate back bias voltage vaB, which is set to -(Vcc knee VTR) as described above, is reduced by the leakage IT flow, and becomes substantially approximately -(Vce -2X VTH). Set. As a result, the dynamic type R
When AM is changed from a non-selected state to a selected state, changes in the level of the substrate back bias voltage vha are compressed, resulting in more stable operation of the dynamic RAM. As described above, the boost capacitances C2 and C3 provided in the voltage generation circuit VG2 are designed to have relatively small capacitance. Therefore, boost capacitances C2 and C3
l! is transmitted to the substrate back bias voltage supply point VBe by the charge pump action of ! The load amount is a relatively small value. As a result, the oscillation circuit 03C2 has a relatively small current supply capability. Furthermore, as mentioned above,
The oscillation circuit 03C2 operates when the oscillation circuit control signal oc2 is set to a high level, that is, when the dynamic RAM is set to a selected state, or when the dynamic RAM is set to a non-selected state and the column address strobe No. 8 ζAs is set to a high level. When set to high level, it is selectively activated. At this time, the voltage generation circuit VG2 corrects the fluctuation due to the leakage current to the substrate, and
A relatively small operating current is supplied to put the VM into an operating state. On the other hand, the oscillation circuit 05C2 has the row address strobe signal RAS set to high level and the column address strobe signal ■ set to low level at the same time.
Selectively the operation is stopped. At this time, the substrate back bias voltage generation circuit V BB
As mentioned above, since the operation of voltage generating circuit G1 is also stopped, G is completely stopped. By the way, as described above, the dynamic RAM of this embodiment is brought into a selected state when the row address strobe signal (2) is set to a low level. At this time, in the dynamic RAM, as shown in memory cycles cy, i, and C) 1.2 in FIG. As a result, the ■Before■ refresh mode is established, and as shown in cycle Cy, 3 in Figure 3, the column address strobe signal ■ is set to low level with a slight delay after the row address strobe signal ■, so that the normal This is considered to be the operating mode. On the other hand, while the row address strobe signal (2) is at a high level and the dynamic RAM is in a non-selected state, the column address strobe signal (2) is selectively set at a high or low level within a range that satisfies the above activation condition. Then, the row address strobe signal (■) is set to high level and the column address strobe signal (2) is set to low level at the same time, so that the substrate back bias voltage generation circuit V
The operation of BB G is completely stopped as described above. In the dynamic RAM of this embodiment, although not particularly limited, the following user specifications are defined. That is, as shown in FIG. 3, when a long-cycle refresh operation is performed, the period when the row address strobe signal ■ is at a low level, in other words, the substrate back bias voltage generation circuit VsBG is unconditionally in the operating state. The period during which the row address strobe signal ξ
The period until V as G is brought to a low level, in other words, the period during which the substrate back bias voltage generating circuit V as G is completely stopped is defined as the -■ delay time t crd, which is, for example, 300p3. Ru. Further, the cycle in which the refresh mode is executed is defined as a refresh operation trc, and the time is set to, for example, 400I1g. Needless to say, these user specifications are determined based on the test results of dynamic RAM, and the substrate back bias voltage, which has been lowered once the substrate back bias voltage generation circuit V AS C is activated, is This guarantees the time until the level of vaB is sufficiently recovered or the time during which the substrate back bias voltage Vaa can maintain the required level even when the substrate back bias voltage generation circuit VeeG is completely stopped. be. For these reasons, the column address strobe signal ■ is selectively set to low level in accordance with the above user specifications, and the substrate back bias voltage generation circuit V
By completely stopping asG, the average operating current of the substrate back bias voltage generation circuit VaBG can be reduced without interfering with the operation of the dynamic RAM. As a result, the power consumption of dynamic RAM in refresh mode is reduced, resulting in an ultra-low power consumption dynamic RAM that can be used for battery bank upgrades, etc.
It is possible to achieve this. As described above, the dynamic RAM of this embodiment is
Built-in substrate back bias voltage generation circuit VBeG. The substrate back bias voltage generation circuit VBOG includes a voltage generation circuit vGl having a relatively large current supply capability;
Voltage generating circuit VG2 with relatively small current supply capability
In this embodiment, the substrate back bias voltage generation circuit VeilG is unconditionally put into the kJ state by the row address strobe signal 2 being set to low level, and the time is defined as the 2 pulse @tras. be done. On the other hand, the substrate back bias voltage generation circuit VBRIG
is completely stopped by setting the row address strobe signal ■ to high level and the column address strobe signal ■ to low level, and the time is τX
]・■Delay time t is defined as crd. moreover,
The period in which the refresh mode is executed is defined as a refresh period trc. These user specifications are
It is determined according to the test results of the dynamic RAM, that is, the recovery time or retention time of the substrate back bias voltage VDB. As a result, the dynamic RAM of this embodiment selectively sets the column address strobe signal ■ to a low level within a range that satisfies the above user specifications, and intentionally stops the operation of the substrate back bias voltage generation circuits VB and G. Therefore, the average operating current can be reduced. As a result, the power consumption of the dynamic RAM in the refresh mode can be reduced, and an ultra-low power consumption dynamic RAM that can be used for battery backup etc. can be realized. As shown in the above embodiment, the present invention can be applied to a dynamic type RA equipped with a built-in substrate back bias tail pressure generation circuit.
When applied to a semiconductor memory device such as M, the following effects can be obtained. That is, (1) the operation of the built-in substrate back bias voltage generation circuit can be selectively stopped in accordance with a predetermined combination of activation control signals, and the substrate back bias voltage generation circuit can be selectively stopped according to the combination of the activation control signals. By specifying as user specifications the period during which the system will be in operation and its operation will be stopped.
The advantage is that the built-in substrate back bias voltage generation circuit can be kept in operation for the minimum necessary period without interfering with the operation of the dynamic RAM. (2) According to item (1) above, especially in the long cycle dynamic RA Ni refresh mode,
The effect of reducing the average operating current of the substrate back bias voltage generation circuit can be obtained. (3) Items (1) and (2) above provide the effect that power consumption of a dynamic RAM incorporating a substrate back bias voltage generation circuit can be reduced. (4) Items (1) to (3) above provide the effect of realizing an ultra-low power dynamic RAM that has a built-in substrate back bias voltage generation circuit and can be used for battery backup. Although the invention made by the present inventor has been specifically explained above based on examples, it goes without saying that this invention is not limited to the above-mentioned examples, and can be modified in various ways without getting the gist of the invention. For example, in FIG. 1, various logical conditions for forming the oscillation circuit control signals ocl and oc2 can be realized by combining appropriate timing signals. The level detection circuit LVM also includes one or more N transistors in the form of diodes, for example, in series with the MO'S F E'l'Q 11 and Q12.
By further adding a channel MO3FET, the absolute value of the determination level for the substrate back bias voltage vies can be increased. Voltage generation circuit G1 and VO2 may not include a clamp circuit, and voltage generation circuit VG2 may be configured from a 1 fil charge pump circuit, similar to voltage generation circuit VGI. Good too. In FIG. 2, the memory array MARY may be configured with a plurality of memory mats, or may input/output stored data in units of multiple focus points.Dynamic RAM is a dynamic RAM that generates a substrate back bias voltage. A dedicated control signal for controlling the operation of the circuit vsac,
It may also have dedicated control signals for specifying the refresh mode, in which case the user specifications described above would need to be defined for these control signals. The specific numerical values of each user specification are not particularly limited by this example. Furthermore, the specific circuit configuration of the substrate back bias voltage generation circuit shown in FIG. 1, the block configuration of the dynamic RAM shown in FIG. 2, and! @
Various embodiments may be explored, such as the combination of control signals, address signals, etc. shown in FIG. IuThe above explanation mainly describes the invention made by the present inventor in terms of the dynamic type R, which is the field of application behind the invention.
Although the present invention is applicable to AM, it is not limited thereto, and can also be applied to various semiconductor storage devices such as multi-port memory having a basic configuration of dynamic memory cells. It can be widely applied to semiconductor memory devices incorporating at least a substrate back bias voltage generation circuit and digital devices including such semiconductor memory (R devices). [Effects of the Invention] A brief explanation of the effect is as follows: In a predetermined combination of start control No. 16, the operation of the built-in substrate back bias voltage generation circuit can be selectively stopped; By specifying the period during which the substrate back bias voltage generation circuit is selectively put into operation according to the combination of the start-up control signals and its operation is stopped as a user specification, it is possible to prevent the operation of the dynamic RAM from being hindered. This allows the built-in substrate back bias voltage generation circuit to be in operation for the minimum necessary period.This reduces the average operating current of the substrate back bias voltage generation circuit. Built-in ultra-low power consumption dynamic RA that can be used with panteri bank amplifiers, etc.
It is possible to realize M.

[Brief explanation of the drawing]

Figure 1 shows a dynamic RAM to which this invention is applied.
FIG. 2 is a block diagram showing an example of a dynamic rlAM including the substrate back bias voltage generating circuit of FIG. 1; FIG. FIG. 1 is a timing diagram showing one embodiment of the substrate back bias voltage generation circuit, and FIG. 4 is a circuit diagram showing a substrate back bias voltage generation circuit developed by the inventors of the present invention prior to the present invention. V B, G...substrate back bias voltage generation circuit,
VGI, VO2---Voltage generation circuit, 03CI. 03C2...Oscillation circuit, LVM...Level detection circuit, l)L...Delay circuit. Q1~Q3...P channel MOS FET. Ql, 1-Q28...N-channel MO3FET. N1~N23...Inverter circuit, NAG 1~NA
G9...Nant gate circuit, sOG Tonoa gate circuit, 01-C3...Boost capacitance, C4...Capacitor. MARY...Memory array A, SA...Sense amplifier, CSW...Column switch, RAD...Row address decoder, CAD...Column address decoder, RAB...Row address buffer, -AMX
...Address multiplexer, RF C...Resolution range air address counter, CAH...Column address buffer, 110...Data input/output circuit, TG...Timing generation circuit.

Claims (1)

Claims: 1. A semiconductor memory device comprising a substrate back bias voltage generation circuit whose operation is selectively stopped when a predetermined combination of activation control signals is applied. 2. The semiconductor memory device is a dynamic RAM, the activation control signals are a row address strobe signal (■) and a column address strobe signal (■), and the substrate back bias voltage generation circuit has a relatively large current supply capability. and a second voltage generating circuit having a relatively small current supply capability, the first voltage generating circuit is configured such that the row address strobe signal (1) is set to a low level. When the row address strobe signal ■ and the column address strobe signal ■ are both at high level and the substrate back bias voltage is below the specified value, the operation state is selectively activated, and the row address strobe signal ■ is at high level. and the operation of the second voltage generating circuit is selectively stopped when the column address strobe signal ■ is set to a low level or the column address strobe signal is set to a low level. It is selectively activated when the address strobe signal ■ is set to high level, and its operation is selectively stopped when the row address strobe signal ■ is set to high level and the column address strobe signal ■ is set to low level. 2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is 3. The time period during which the first and second voltage generating circuits of the substrate back bias voltage generating circuit are selectively activated and their operation is stopped according to the row address strobe signal (■) and column address strobe signal (■) is , each defined as a user specification.
3. The semiconductor memory device according to item 1 or 2.