JPS59191194A - Mos storing device - Google Patents

Abstract

PURPOSE:To correlate the temperature characteristics of information extinction of a dynamic type memory cell with the temperature characteristics of automatic refresh period and to perform automatic refreshing at the optimum period by providing a discharge current circuit having a positive temperature resistance coefficient in a delay circuit. CONSTITUTION:A capacitor C is precharged as an initial state and the voltage VC is made to a high level such as the power source voltage Vcc. Consequently, the output signal of an inverter IV1 becomes a low level, and when the output signal of a delay circuit DL changes to the low level, the output signal SLF of an OR gate circuit G2 changes from the high level (logic ''1'') to the low level. By the change of supplied address signals, an edge trigger circuit REG forms a detection pulse. A timing generating circuit TG forms various timing signals necessary for refreshing action by supply of the detection pulse. Consequently, the refreshing action of a memory cell selected by stepped address signals is performed.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a MOS (metal-insulator-semiconductor) memory device, and relates to a technique effective for, for example, a device using a dynamic memory cell that requires a refresh operation. It is.

[Background technology]

A dynamic memory cell is called a capacitor that stores information in the form of charge and an insulated gate field effect transistor (hereinafter referred to as MOSFET or MOS) transistor for address selection. ).

In a memory cell formed on a semiconductor substrate, the charge accumulated in the capacitor decreases over time due to leakage current or the like. Therefore, in order to always store accurate information in memory cells, it is necessary to read out the information stored in memory cells before it is lost, amplify it, and use the amplified information. It is necessary to perform a write operation to the same memory cell again, a so-called refresh operation. For example, refreshing memory cells in a 64-bit dynamic RAM (random access memory) is described in Vol.
123, No. 3, pp. 30-33.

That is, the dynamic RAM is provided with an external terminal for refresh control, and by applying a refresh signal RESH of a predetermined level to this external terminal, a plurality of memory cells in the dynamic RAM are automatically refreshed. That's what I was doing.

The above automatic refresh method uses the external control signal RESH
Therefore, it cannot be said to be a fully automatic reflexology operation.

Further, in the self-refresh operation, no consideration is given to the leakage current in the actual memory cell, so the current consumption becomes larger than necessary. That is, since the leakage current increases as the temperature rises, in order to perform the self-refresh operation over the entire temperature range, it is necessary to set a short period according to the highest temperature with a certain margin.

[Purpose of the invention]

An object of this invention is to provide an MO5 storage device with a fully automatic refresh function.

Another object of the present invention is to provide an MO3 storage device with low power consumption.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

In other words, by providing a discharge current circuit with a positive temperature resistance coefficient as a delay circuit constituting a timer circuit that regulates the automatic refresh cycle, the temperature characteristics related to information disappearance of dynamic memory cells and the temperature of the automatic refresh cycle can be adjusted. By associating this with the characteristics, an automatic refresh operation at an optimal cycle is achieved.

Hereinafter, the present invention will be explained in detail together with examples.

[Embodiment 1] FIG. 1 shows a block diagram of an embodiment of the present invention.

In the figure, each circuit block surrounded by a dotted line is formed on a single semiconductor substrate such as silicon by a known semiconductor integrated circuit manufacturing technique, and includes, for example, terminals DO-D7. AO-A14°WE, C3, RESH, and Vcc and Vss are external terminals, and power is supplied to the terminals Vcc and Vss from an appropriate external power supply device (not shown).

The circuit symbol M-ARY is a memory array in which known 1MO3 type memory cells are arranged in a matrix. In this embodiment, although not particularly limited, the memory cells are arranged in a two-intersection manner with their input and output nodes coupled to a pair of complementary data lines, D, arranged in parallel.

The circuit symbol PCI indicates a data line precharge circuit, which includes, but is not limited to, a MOSFET that receives a precharge pulse φpcl, shorts the complementary data line D, and precharges it to Vcc/2. Consisted of.

In this way, the precharging operation of the memory array can be performed by simply shorting a pair of complementary data lines to an intermediate level of about Vcc/2, which is similar to the conventional dynamic RAM.
The amount of level change is small compared to the one that charges up from 0 volts to the Vcc level, and the gate voltage of the precharge MO3FET is set to the normal logic level (
Since it can be turned on in a fully unsaturated state even when using Vcc), the precharge operation is fast and the power consumption is low.

Can be done under power.

Then, as mentioned above, set the precharge level to approximately Vcc.
/2, so even when reading a memory cell, the memory cell's swift MO3F
Even if a normal logic level (Vcc) is used as the ET gate voltage (word line selection voltage), it can be turned on in a sufficiently unsaturated state, so conventional dynamic RAM
It becomes possible to read out the entire charge of the information storage capacitor without using a bootstrap voltage as in the case of FIG.

Further, since the read reference voltage uses the precharge level of one data line on which no memory cell is selected, there is no need for a dummy cell that forms the read reference voltage as in the conventional dynamic RAM.

The circuit symbol SA indicates a sense amplifier, which is composed of an 0MO3 (complementary MO3) launch circuit in which a power switch MO3FET is provided at each of the power supply voltage Vcc and the circuit ground potential Vss, although this is not particularly limited. , whose pair of input/output nodes are connected to the complementary data line D
is combined with

The timing pulse φpa is the power switch MO3
This is for controlling the FET. power switch M
The O3FET is turned off just before precharging and the complementary data line is connected to Vcc, V with D floating.
Hold ss level. And the above precharge M
It is precharged to Vcc/2 by turning on the O3FET.

Denoted by circuit symbol C-3V is a column switch that couples a selected complementary data line to a common complementary data line according to a column selection signal.

The circuit symbol R-ADH is a row address buffer, which receives an external address signal from an external terminal AO-A8 and forms internal complementary address signals 0 to 8.

The circuit symbol C-ADB is a column address decoder that receives external address signals from external terminals A9 to A14 and outputs internal complementary address signals 9 to a1.
form 4.

The circuit symbol R-DCR is a row address decoder, which receives internal complementary address signals main θ to 8 via a multiplexer MPX, which will be described later, and outputs M-A.
A word line selection signal for RY is formed. This word line selection signal is synchronized with the word line selection timing signal φX.
This will be conveyed to M-ARY.

The circuit symbol C-DCR is a column address decoder, which inputs internal complementary address signals 9 to 114.
In response to this, an M-ARY data line selection signal is formed.

This data line selection signal is synchronized with the □ data line selection timing signal φy.
can be conveyed to.

The circuit symbol PC2 indicates a precharge circuit for the common complementary data line, and although it is not particularly limited, it is constituted by a MOSFET similar to the above, which short-circuits the common complementary data line in response to the precharge pulse ψpc2. .

The circuit symbol MA indicates a main amplifier, which has the same circuit configuration as the sense amplifier described above. The timing pulse φma is the power switch MO3FET
A circuit designated by the symbol DOB for controlling the MA is a data output buffer sofa, which sends read data from the MA to external terminals DO to D7, respectively, in response to a read timing pulse φrW. Note that during writing, the read timing pulse φrw and the data output cover sofa DOB are rendered inactive (output high impedance).

The circuit symbol DIB is a data input cover sofa, which transmits write data from the external terminal DO-D7 to the common complementary data line in response to a write timing pulse φrw. Incidentally, during reading, this data cover sofa DIB is made inactive by the write timing pulse φ.

The various timing signals mentioned above are formed by the following circuit blocks.

Although not particularly limited, the circuit symbol REG is an edge trigger circuit that receives address signals aO to a8 (or 0 to a8) and uses the rising or falling edges thereof.

Although not particularly limited, the circuit symbol CEG is an edge trigger circuit that receives address signals a9 to a14 (or 19 to 114) and detects their rising or falling edges. These edge trigger circuits are not particularly limited to, but may be configured to receive at least one edge signal ao-a8 .
Consisting of exclusive OR circuits that receive address signals a9 to a14 and their delayed signals, and an OR circuit that receives their output signals, any address signal a
O-a8. Edge detection pulse φr synchronized with change timing of address signals a9 to a'14.

φC are respectively formed.

The circuit symbol TG is a timing generation circuit, which forms the main timing signals etc. shown as the representative above. This timing generation circuit receives edge detection pulses φr and φC as well as a write enable signal WE supplied from an external terminal.

The series of timing pulses described above are formed in response to the chip selection signal O8.

The circuit symbol MPX is a multiplexer, which selectively sends internal complementary address signals 10 to 8 formed by the address buffer R-ADB and the automatic refresh circuit REF, which will be described later, to the decoder R-DCR. tell.

The circuit symbol vbb-c is a substrate bias generation circuit.

The circuit symbol REF indicates an automatic refresh circuit, which includes a refresh address counter, an oscillation circuit equipped with a delay circuit having a leakage current simulation function, and the like.

FIG. 2 shows a circuit diagram of an embodiment of the automatic refresh circuit REF.

The circuit symbol C0NT is a refresh address counter, which forms an internal complementary address signal aQ-a'3 for refresh.

Although not particularly limited, impark IVI acts as a voltage detection circuit that uses its rosin threshold voltage V'L as a reference voltage. The output of this inverter IV1 is
applied to the OR gate circuit G2 through the delay circuit DL,
Although not particularly limited, the output of the inverter rV1 is directly applied to the OR gate circuit G2 on the other hand. Although not particularly limited, on the input side of the inverter rV1, a capacitor C, n-channel MO3FETs Q3 to Q6 in series as a discharge circuit for the capacitor C, and a reverse junction diode D for temperature compensation are connected in parallel. provided. The conductance characteristics of the MO3FETs Q3 to Q6 are set small to obtain a desired refresh cycle. The capacitor C includes a p-channel MO3FETQI for precharging,
Q2 is provided in parallel configuration. The gates of the MO3FET QI and the MO3FETs Q3 to Q6 are commonly connected, and the output of the NOR gate circuit G1 is applied thereto. One input of this NOR gate circuit G1 and the above OR gate circuit G2
A refresh signal supplied from an external terminal RESH is applied to. At the gate of MO3FETQ2,
The refresh signal is applied via inverter IV2. In addition, the other manual power of the gate circuit G1 is as follows:
The output of OR gate circuit G2 is applied. Although not particularly limited, the output of the OR gate circuit G2 is used as the self-refresh signal SLF, and is input as a step pulse to the refresh address counter C0NT.

Although not particularly limited, the refresh signal is used as a switching control signal for the multiplexer MPX.

Next, the operation of the automatic refresh circuit REF will be explained according to the operation waveform diagram of FIG.

When the external terminal RE'SH is at a low level (logic "0"), a fresh operation is performed as follows.

By setting the external terminal RESH to low level,
Internal complementary address signal 1 output from multiplexer circuit RIEF
0 to a8 (internal address signals aO to a8 and aO to a8
) to the decoder R-DCH.

In the initial state, the capacitor C is precharged, and its voltage VC is set to a high level like the power supply voltage Vcc. As a result, the output signal of the inverter I1 becomes a low level, and then when the output signal of the delay circuit DL changes to a low level, the output signal SLF of the OR gate circuit G2 changes from a high level (logic "1") to a low level. Although not particularly limited, the counter CONT performs a step operation when the output signal SLF changes from high level to low level. That is, the stepping operation is performed in synchronization with the falling edge. Therefore, as the output signal SLF of the OR gate circuit G2 changes as described above, the incremented address signal is transferred to the multiplexer M.
The signal is transmitted to the decoder R-DCR and edge trigger circuit REG via PX. The edge trigger circuit REG forms a detection pulse by changing the supplied address signal. The timing generation circuit TG forms various timing signals necessary for the refresh operation each time a detection pulse is supplied. As a result, a refresh operation is performed on the memory cell selected by the incremented address signal.

When the output signal J+SLF becomes low level, the output signal of the NOR gate circuit G1 becomes high level. For this reason, the precharge MOS F E 'T' Q 1
is turned off, and the discharge operation of the capacitor C is started. Note that at this time, since the refresh signal is at low level, the MO5FET for precharging
Q2 is turned off.

Therefore, as shown in the figure, the capacitor C is discharged by the current flowing through the MO3FETs Q3 to Q6 and the leakage current of the diode D, and the voltage VC gradually decreases accordingly. When this holding voltage VC becomes lower than the logic threshold voltage VL of the inverter IVI, its output signal is inverted and becomes a high level (logic).
1") and is transmitted to the OR gate circuit G2. Therefore, the output SLF of this OR gate circuit G2 becomes high level, and the output of the NOR gate circuit G1 becomes low level. As a result, the precharge MO5FET Q1 is in the on state. Then, precharging of the capacitor C is started. When the precharging is started and the voltage VC of one electrode of the capacitor C gradually rises, and the voltage VC exceeds the logic threshold voltage of the inverter IVI, the voltage of the inverter rV1 is increased. After the output signal of this inverter IVI becomes low level,
After the delay time of the delay circuit DL, the output signal of the delay circuit DL becomes low level. As a result, the OR gate circuit G
The output signal SLF of No. 2 changes from high level to low level. Due to this change, the counter C0NT is incremented, and the memory cell designated by this incremented address signal is refreshed in the same manner as described above. Thereafter, the oscillation operation for the refresh operation is repeated in the same manner.・The pulse width of the self-refresh signal SLF is the same as that of the delay circuit DL.
is set by the delay time td.

It is desirable that the capacitor C is always precharged to a predetermined value by a precharge operation. That is, it is desirable that the voltage VC (holding voltage VC) at one electrode of the capacitor C is always set to the voltage cc as in the above example by precharging. This is to prevent the refresh period from changing greatly depending on the magnitude of the holding voltage VC of the capacitor C, rather than changing the refresh period due to leakage current due to temperature, etc., and to reduce unnecessary current consumption.

For this reason, in this embodiment, the output of the inverter IVI is applied to the OR gate circuit G2 via the delay circuit DL, and the output of the inverter jV1 is applied directly to the OR gate circuit G2. By doing this, the time during which the output (K SLF is at a high level, that is, the precharge time) is lengthened,
The capacitor C is sufficiently precharged.

In this embodiment, when a clock is input to the external terminal RESH, a so-called auto-refresh operation is performed. That is, when the external terminal RESH is changed from high level to low level, multiplexer MPX is switched to the refresh circuit REF side. In addition, the above terminal RE S
When H is at high level, MO3 for precharging
Since the capacitor C is precharged by the FETQI and Q2, when the level of the terminal RESH changes, the inverter IVI and the delay circuit DL
The output signals of are both at low level.

Therefore, as the level of the terminal RESH changes from high level to low level as described above, the output signal SLF of the ORCATE circuit G2 also changes from high level to low level. As a result, the counter C0NT is incremented and refreshed in the same way as described above.

In the delay circuit of the above embodiment, as shown in the current-temperature characteristic diagram in FIG. On the other hand, the current I2 of the diode D has a positive temperature characteristic in which the current increases. Therefore, the discharge current 11+I2 of the capacitor C has positive temperature characteristics as a whole. This discharge current sets the refresh period, so by adjusting it, the temperature characteristics of the dynamic memory cell can be made to match, and the refresh period can be set.

[Embodiment 2] FIG. 5 shows a circuit diagram of another embodiment of the above delay circuit.

In this embodiment, instead of the diode D mentioned above, a polysilicon high resistance R is used. Since the current-temperature characteristic of this polysilicon resistor R has a positive temperature characteristic similar to the leakage current of the diode D, the same operation as described above can be performed.

〔effect〕

(1) By setting the refresh cycle using a delay circuit that has the same temperature characteristics as that of dynamic memory cells, refresh operations are not performed at the maximum necessary cycle, resulting in significantly lower power consumption. The effect of being able to achieve electric power generation is obtained.

(2) In the above embodiment, since the self-refresh operation is automatically activated without depending on an external control signal, it is possible to realize a completely automatic refresh operation.

(3) Since the normal self-refresh operation is often used in CJ production of bath battery bank amplifiers, from this point of view, the fully automatic refresh operation and low current consumption operation described above are extremely suitable for memory systems with pan battery bank amplifier functions. If it is beneficial, it will be effective.

(4) Since the capacitor C is precharged with the power supply voltage Vcc, the above-mentioned refresh period has the advantage that it can also compensate for fluctuations in the power supply voltage Vcc.

(5) As in the embodiment shown in Figure 1, when a system is adopted in which changes in address signals are detected to form internal timing signals, dynamic memory cells can be viewed from the outside in the same way as static memory. This, together with the fully automatic refresh operation described above, provides the effect of making the MOS storage device extremely easy for the user to handle.

Although the invention made by the present inventor has been specifically explained based on Examples above, this invention is not limited to the Examples described above, and it is understood that various changes can be made without departing from the gist of the invention. Needless to say. For example, the above-mentioned Inharc IV may use a voltage comparison circuit made up of a vibration circuit or the like. In addition, MO for discharge
The 3FETs Q3 to Q6 may be omitted, and the capacitor C may be discharged only by circuit elements having positive temperature characteristics such as the diode D and the polysilicon resistor. Further, the control method for performing the refresh operation using the output of this delay circuit can be modified in various ways.

[Application field]

The above explanation has mainly been about the case where the invention made by the present inventor is applied to the pseudo-static RAM which is the background of the invention, but the invention is not limited thereto, and the invention is not limited to this, and the invention is not limited to this, and the invention is not limited to this, and the invention is not limited to this. It can be widely applied to MO3 storage devices.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram showing one embodiment of the present invention. FIG. 2 is a circuit diagram showing an embodiment of the automatic refresh circuit. It is a circuit diagram. M-ARY: Memory array, PCI: Precharge circuit, SA: Sense amplifier, R-ADB: Row address decoder, C-5W, -1: Column switch, C
-ADB...Column address buffer, R-DCR...
Row address decoder, C-DCR...column address buffer, PC2...precharge circuit, MA...main amplifier, REG, CEG...edge trigger circuit, T
G...timing generation circuit, REF...automatic refresh input circuit, DOB...data output Hanofa, D! I3...
Data person cover sofa, MPX...Multiplexer 1st figure AOA? 2nd figure 0-o~ &ge 3rd figure sty:

Claims (1)

[Claims] 1. A delay circuit including a capacitor, an impedance means that is provided in parallel with the capacitor and has a positive temperature resistance coefficient through which the discharge current flows, and a delay time of this delay circuit. operates according to a time signal formed using
An MO3 storage device comprising: an automatic refresh control circuit that performs a self-refresh operation of a dynamic memory cell according to an address signal generated internally. 2. The MO3 storage device according to claim 1, wherein the impedance means is a reverse junction diode. 3. M according to claim 1, wherein the impedance means is a polysilicon resistance element.
O5 storage. 4. The MO3 storage device according to claim 1, 2 or 3, wherein the automatic refresh control circuit is also activated by an external control signal.